JPS62288974A - vector processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] 1 Detailed description of the invention [Industrial application field] The present invention relates to a vector processing device, and particularly to a vector processing device.

A vector processing method that performs file loading processing at high speed.

Regarding.

[Conventional technology]

Conventional vector processing equipment (for example, Nikkei Ellen) o
In NIKU x Nas1a, PP, 159-185), for a vector load instruction that loads data on main memory into a vector register, a memo IJ IJ quest is sent to the main memory control device at the start of execution of the instruction.

data transfer process from main memory.

Ta. However, the execution of the instruction does not start the data transfer process.

No consideration was given to the point that the instruction is executed before the instruction starts, for example, when it enters the instruction buffer.

[Problem that the invention seeks to solve]

In conventional vector processing devices, data is stored in main memory.

For a vector instruction that refers to a vector register, the data transfer process from main memory to the vector register was started at the start of execution of the instruction. For this reason, the arithmetic unit.

Vector from main memory even though it is free.

Calculation cannot be started because data does not come to the register.

The problem was that there was a lot of time left.

An object of the present invention is to provide an instruction to refer to main memory data.

By recognizing the instruction before the execution of the relevant instruction begins and hastening the start of the transfer processing of the main memory contents referenced by the relevant vector instruction, the time when the arithmetic unit is idle while waiting for data to arrive is minimized, and as a result, the calculation throughput is increased. It's about making it bigger.

[Means for solving the problem] The above purpose is to provide a circuit that decodes a vector instruction that refers to data in main memory before executing the instruction and instructs transfer from the main memory, and a workpiece that stores the data. .

vector register, when a vector instruction is executed, the load instruction is loaded from the work vector register.

This is achieved by providing a circuit for changing the vector move instruction to a vector move instruction.

[Effect]

The data written to the work vector register as 1° by read-ahead from main memory is the actual vector row.

Do not use it at the beginning of the execution stage of a code instruction.

is also possible. For this reason, Vector Pro VII.

Tsusa's startup may be canceled due to an exception.

Even if the prefetched main memory data is rewritten by the store instruction that precedes the vector load instruction,
It is only necessary to discard the contents of the work vector, without destroying the contents of the vector register specified by the program.

〔Example〕

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

be. Read ahead to vector instruction buffer unit 1.

Vector instructions are vector instruction control units.

The command is sent to port 2 and then enters the execution state.

In the case of a vector load instruction that loads data on the main memory into a vector register, the data from the main memory 4 is sent to the main memory controller 6 via the signal line 1a.

- instructs the start of data read processing. reading.

The start address and number of read elements are determined by signal line 1h.

Send. Next, the main memory control device 3 sends a signal to the signal line 9 through 11° to instruct the main memory device 4 to read.

A read address is sent via line 3L. The main memory device 4 sends read data through a signal line 4α.

Instructs and sends read data via signal line 4h.

do. The main memory control unit 5, which received this, sends a message.

A write instruction is given to the work vector register via line 5-, and write data is sent via signal line 3f.

On the other hand, the vector load instruction transferred from the vector instruction buffer unit 1 to the vector instruction control unit 2 is stored in the vector instruction register shown in FIG.

21 and from the main memory control device 3 via the signal line 3α.

It is sent to the read-ahead valid instruction flag and signal line 3b.

The work vector register number sent from.

If the look-ahead is valid, it is changed to a vector move command, and the vector is sent to signal lines 2α, 2h, and 2c.

Sends control information for move processing. .

FIG. 4 shows a detailed configuration diagram of the instruction change circuit 22 shown in FIG. 3.

It was shown to. Vector command coming on signal line 21α.

The result of decoding is shown divided into the write register number and other information. If the prefetch valid instruction information 3a for the instruction indicates "invalid", the selector 24 selects the control information for the originally instructed instruction, and if it indicates "valid", the control information for the vector move instruction is selected. Select information. In any case, since the vector register in which the main memory data is written is the same, the control information sent through the selector 24 is sent to the vector register unit 5 via the signal line 2C. If the look-ahead valid instruction information 3a indicates “invalid”,
46 Control information for vector load instructions through vector 24.

appears, but this control information includes main memory data.

Control information for starting main memory data read processing to storage 3.

Since the information is included, it is read out using the signal line 2α.

and sends an instruction signal to start processing.

FIG. 2 shows the vector instruction buffer unit 1.

This shows a configuration example. Vector instruction back.

The vector instruction entered in a 11 is selected by the selector 13.

is selected and pre-decoded by the decoder 14.

In the case of a load command, a signal line is passed through the control circuit 15.

1α, main memory data is sent to the main memory control device 3.

Issue an instruction to start reading ahead. read address and.

The number of read elements is determined from the register 16 through the signal line 1h.

Send again. Vector instructions are sequentially transferred to the register 12, and when they become executable, they are passed through the signal line 1C.

is sent to the vector command control unit 2.

FIG. 5 shows details of the main storage control device 3. When an instruction to start reading main memory data is received via the signal line 1α, the control circuit 31 checks whether there is a work vector that can be used, and if there is a work vector that can be used, refreshes the memory via the signal line 51α.

A main memory data read instruction signal is sent to the ESTA 34.

At the same time as sending out the signal, registration in the work vector register management table 52 is performed using the signal line 51b.

cormorant. In this table, one row corresponds to one instruction. The memory requester 34 has signal lines 3II and 5J.

A read instruction signal is sent to the main memory.

A read address is sent, and a read data send instruction signal and read data are sent via signal lines 4α and Ah.

When it arrives, it is sent to the vector register 1.1 via signal lines 5c and 5d, or to the work vector register 1.1 via signal lines 3g and 5f.

Write instruction signal and write data to the register.

Send out. The control circuit 31 executes vector instructions.

1°, which is informed by the signal line 1a that it is enabled and enters the vector instruction register 21 (see FIG. 5);
The select signal 51C selects one entry (which can also be called the C row) in the work vector management table, and sends the read valid instruction flag and work vector register number to the vector instruction control unit 2 via the signal line 3α3h. Note that when prefetching from the main memory to the work vector becomes invalid, for example, the data prefetching is preceded.

If the main memory data is rewritten by a vector store instruction, the comparator circuit 33 detects this.

Then, the valid instruction flag of the corresponding entry is dropped, ie, made invalid, by the signal line 33α. As a result, the vector load instruction started to be executed.

A look-ahead valid finger that is sometimes sent via signal line 3α.

The display signal indicates "invalid", and is it a vector load command?

No changes were made to the vector move instructions;

Since it is processed as a load load command, a read instruction signal for main memory data is sent again via signal line 2α.

issue is sent out. In such a case, the effect of data prefetching according to the present invention disappears, and the performance becomes the same as that of processing according to the prior art.

1. Returning to FIG. 1, the data flow when a vector load instruction is changed to a vector move instruction will be described. The pre-read data on the main memory passes through the signal line 5f and the switching circuit 55 under the control of the work vector register control circuit 58.

- written to vector register 56; When the execution of the vector move instruction changed from the vector load starts, the work vector register control circuit 58 and the vector register control circuit 54 operate according to the control information transferred to the signal line 2C, and the data is read from the work vector register 56. Data is written into the vector register 52 through the switching circuit 57 and the switching circuit 51. As a result, the contents of the main memory are written to the vector register specified by the program, and the program sends the data from the main memory control device 3 via the signal line 3d and the switching circuit 51 according to instructions from the vector instruction control unit 2. The difference from the case where the data is written to the vector register 52 is invisible except for the difference in processing speed.

〔Effect of the invention〕

According to the present invention, a vector load instruction, which requires a relatively long processing time among vector instructions and appears relatively frequently, can be processed like a vector move instruction, which takes a shorter processing time. This has a particularly large effect on reducing processing time when the vector 8 processor is started when all of the vectors are empty.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, FIG. 2 is a configuration diagram of a vector instruction buffer unit, and FIG.
4 is a block diagram of a vector instruction control unit, FIG. 4 is a block diagram of a vector instruction change circuit, and FIG. 5 is a block diagram of a main memory control unit. DESCRIPTION OF SYMBOLS 1... Vector instruction buffer unit, 2... Vector instruction control unit, 3... Main memory control device, 4...
...Main memory, 5...Vector register unit,
22... Vector instruction change circuit, 56... Work vector register. Figure 1 Figure 2 Figure 3 Figure '-2C! Rod + Adai 51

Claims (1)

[Claims] 1. In a vector processing device that includes a main memory device, a plurality of vector registers, a main memory control device that transfers data between the main memory device and the vector registers, a vector instruction buffer, and a vector instruction control circuit, A vector processing device characterized by being provided with an unspecified work vector register and an instruction change circuit.