JPS62283748A - Data sink - Google Patents

Abstract

PURPOSE:To eliminate an ineffective signal such an echo signal, etc., by changing suitably the discrimination start time or the decision reference of a received signal. CONSTITUTION:The titled device is provided with a deciding means A for deciding the classification of the received signal, and a control means B for changing suitably the discrimination start time or the discrimination reference of the received signal. In such state, at the time of receiving a signal sent out of the other station, the timing of a receiving start of the signal sent out of the other station is changed in accordance with the kind of the signal. That is to say, at the time of receiving the sent signal out, the reception of a tonal signal is started immediately, and the reception of a binary signal is started after some prescribed time is elapsed. In such way, the signal sent from the other party of communication is received immediately, and without discriminating it, the discrimination start time or the discrimination reference of the received signal is set in accordance with the classification of the received signal, therefore, it does not occur that an ineffective signal such as an echo signal, etc., is read.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a data receiving device that receives control signals and data signals.

[Prior Art] A facsimile machine is widely known as one of this type of data receiving apparatus.

Previously known facsimile machines did not include hardware within themselves to guard against echo signals. However, in the Gl mode and G2 mode procedures, even if an echo occurs, a procedure error does not occur. The reason for this is that the frequency of the signal transmitted by the local station is different from the frequency of the signal transmitted from the other station following that signal.

However, in the G3 mode procedure, if an echo occurs, the binary signal sent by the own station will be received, resulting in a pre-procedure error.

Therefore, in order to avoid such pre-procedure errors in international lines, etc., echo suppressors are set to enable. That is, when the echo suppressor disable tone is sent from the called facsimile machine, the calling facsimile machine responds to the second initial identification signal sent from the called facsimile machine with a receive command signal or a send command. By sending out the signal, a J signal off state is created, thereby creating an echo suppressed state.

However, even in such an echo suppressed state, echoes may occur.

[Problem to be solved by the invention] When an echo occurs in the data line like this,
A major drawback was that the signal transmitted by the own station was received again, resulting in a procedural error.

SUMMARY OF THE INVENTION Therefore, in view of the above-mentioned points, an object of the present invention is to provide a data receiving device that takes eco-friendly measures.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a data receiving device that receives control signals and data signals.
The apparatus includes a determining means for determining the type of the received signal, and a control means for appropriately changing the identification start time or discrimination criterion of the received signal in accordance with the output of the determining means.

[Operation] Instead of immediately receiving and identifying the signal sent from the communication partner, by setting the time to start identifying the received signal or the discrimination criteria according to the type of the received signal, echo signals etc. This prevents the invalid signal from being erroneously read.

[Example] Hereinafter, the present invention will be described in detail based on Examples.

FIG. 1 is an overall configuration diagram of a facsimile apparatus according to the present invention. In other words, by alternately transmitting and receiving, control signals and data signals can be transmitted and received.
A determining means A for determining the type of the 1st sentence in 75 seconds, and identifying the received signal in accordance with the output of the determining means. A control means B is provided for appropriately changing the start time or the discrimination criteria.

When receiving signals sent from the other station in this way,
Depending on the type of signal, the timing of starting reception of the signal sent from the other station is changed. Specifically, when receiving the transmitted signal, the reception of the tonal signal starts immediately, and the reception of the binary signal starts after a certain period of time has elapsed.

The first response received on the called side will be explained using item 1).

First, after transmitting a called station identification signal, an initial identification signal is transmitted. Then, it goes to receive the signal sent from the other station. If no significant signal is detected from the partner station even after 3 seconds have elapsed, the initial identification signal is sent again, and the process returns to receiving the signal sent from the partner station. Here, as a signal sent from the partner station, the tonal signal is GC.
I signal (13001 (Z), GC2 signal (2100H
z), PIS signal (462H2). Furthermore, the binary signal sent from the partner station is a reception command signal (NSS/TSI/DC5 signal).

There is a transmission command signal (NSC/GIG/DTI: signal) and one procedure interruption EOP signal (PRI-EOP signal).

This facsimile machine receives a tonal signal immediately after transmitting the initial identification signal. On the other hand, when receiving a binary signal, the preamble is sent to the head, so for example, 600 m
It is only necessary to start receiving the binary signal after 5 minutes have elapsed.

As a result, no malfunction will occur for echoes of 600 m5 or less. Further, since it is possible to immediately start receiving the tonal signal, there is no possibility of failure in receiving the tonal signal.

Furthermore, when receiving a signal sent from the other station after sending a signal from the own station, depending on the type of signal received, it may be determined that it is an invalid signal (a signal due to an echo or a meaningless signal). standards have been changed. Specifically, when receiving a binary signal sent from the other station after the own station has sent a signal, if the same signal as the one sent by the own station is received for a signal other than the initial identification signal, or, When an initial identification signal is received, an echo signal (or
It is determined that the signal is a meaningless signal).

In other words, as for binary signals, signals transmitted by the own station are no longer received, except for the initial identification signal.

Further, when the present facsimile apparatus is set to the automatic call receiving mode, when an initial identification signal is received after being sent, it is determined that this initial identification signal is a meaningless signal.

Further, when the present facsimile apparatus performs polling reception, for example, instead of automatic call reception, after transmitting an initial identification signal, the facsimile apparatus receives the initial identification signal sent from the other party's station. At this time,
D sent by own station! S signal (Digital Iden
PIF (Facsimile Information Field) in tification Signal: Digital Identification Signal
The 9th bit of is “0”, but the 01 sent by the other station
The 9th bit of FrF in the 5th signal is "1". Here, the 9th bit of the PIF in the 015 signal indicates the presence or absence of a document ([If the 9th bit of the PIF in the 115 signal is ``1 completed, the document exists: PIF in the DIS signal
If the 9th bit is r□, there is no original). That is,
If this facsimile machine is not in automatic call receiving mode,
After sending the initial identification signal, when the initial identification signal is received, the contents of the facsimile information field are checked, and if they match, it is determined that the signal is an echo (or the document is not set at the recipient i). . Due to this,
Malfunctions can be avoided even for echoes exceeding 600 m5.

(Hereinafter, blank spaces) FIG. 2 is a block diagram showing an embodiment of a facsimile apparatus to which the present invention is applied.

In FIG. 2, 2 is a network control unit NCU (Net-
Since the telephone network is used for data communication, etc., it connects to the terminal of the line and performs functions such as controlling the connection of the telephone switching network and switching to a data communication path. Also, signal line 2
a is a telephone line. This NCU 2 inputs the signal of the signal line 38a, and if this signal level is "o", the telephone line is connected to the telephone side (that is, the signal line 2a is connected to the signal line 2b).
Connect to. Further, a signal on the signal line 38a is input, and if the signal level is "1", the telephone line is connected to the facsimile machine side (that is, the signal line 2a is connected to the signal line 2c). Under normal conditions, the telephone line is connected to the telephone side.

4 is a telephone.

6 is a hybrid circuit that separates a transmission system signal and a reception system signal. That is, the transmission signal on the signal line 18a is sent out to the telephone line via the signal line 2c and the NC 112. Also, the signal sent from the other party is
It passes through U2 and the signal line 2c and is output to the signal line 8a.

Reference numeral 8 denotes a reading circuit which sequentially reads image signals for one line in the main scanning direction from the original to be transmitted, and creates a signal string representing binary values of white and black. This reading circuit 8 has CC[l
It consists of an imaging device such as a charge-coupled device (charge coupled device) and an optical system. Further, the signal string that has been binarized into white and black is output to the signal line 8a.

lO is an encoding circuit. This encoding circuit 10 inputs the binarized signal output to the signal line 8a,
The data is encoded (MH (Modified Huffman) encoding or MR (Modified Read) encoding) and the encoded data is output to the signal line IQa.

12 is a modulator that performs modulation based on the well-known (11: ITT recommendation V27ter (differential phase modulation) or V29 (quadrature modulation).
A signal is manually modulated, and the modulated data is sent to signal line 1.
Output to 2a.

14 is a parallel-serial (P/S) conversion circuit. This parallel-serial conversion circuit 14 has two buffers (buffer "0" and buffer "1"). At the beginning, both buffers are empty, so a byte pack clock is generated on the signal line 14a. Then, when byte data is written from the control circuit 38, this data is stored in buffer "0". The data stored in buffer "0" is moved to buffer 1 since the other buffer (buffer "1") is empty. Then, since the buffer "O" becomes empty, a byte pack clock is generated on the signal line 14a. Then, when byte data is written from the control circuit 38, this data is stored in buffer "0". Byte data sent from the control circuit 38 is written into this buffer via the signal line 38b. This P/S conversion circuit 14 performs parallel-to-serial conversion on the byte data stored in the buffer "1", and outputs serial data to the signal line 14b every time a clock is sent to the signal line 16a. When 8-bit serial data is output to the signal line 14b, buffer "1" becomes empty, so the byte data stored in buffer "0" is moved to buffer "1". Then, a byte pack clock is generated on the signal line 14a.

When byte data is written from the control circuit 38 via the signal line 38b, this data is stored in buffer "0".

A procedure signal is bit-packed and sent to the signal line 38b every time a byte-pack clock is sent to the signal line 14a.

16 is a modulator that performs modulation based on the well-known C(:ITT recommendation V21). This modulator 111 outputs a clock representing the data transmission timing to the signal line 16a. The serial procedure signal on line 14b is input and modulated, and the modulated data is output on signal line 16b.

17 is a GI2 signal sending circuit. This circuit 17 is
When a pulse is generated on the signal line 38c, a G signal is applied to the signal line 17a.
Sends I2 signal. Then, when the transmission of the GI2 signal is completed, a pulse is generated on the signal line 17b.

18 is an adder circuit. This adder circuit 18 receives signals from the signal line 12a, signal line 16b, and signal line 17a,
The added result is output to the signal line 18a.

20 is a demodulator that performs demodulation based on the well-known CCITT recommendation V27ter (differential phase modulation) or v29 (quadrature modulation). The demodulator 20 inputs the signal on the signal line 6a, performs demodulation, and outputs demodulated data to the signal line 20a.

22 manually decodes the demodulated data output to the signal Pa20a (MH (Modified Huffman)).
This circuit outputs decoded or MR (modified read) decoded data to the signal line 22a.

24 is a recording circuit that manually inputs the decoded data output to the signal line 22a and records white and black signals line by line.

26 is a demodulator that performs demodulation based on the known CCITT recommendation V21. This demodulator 26 inputs the signal on the signal line 6a, performs V21 demodulation, and sends the demodulated data to the signal line 2.
Output to 6b. The timing clock of the received data is output as a signal Pa26a.

28 is a serial-parallel (S/P) conversion circuit. When the clock is sent to the signal line 26a eight times, 8 bits of data are collected (this data is the signal output to the signal line 26b), so when the 8 bits of data are collected, the serial-parallel The conversion circuit 2B generates a clock on the signal line 28a and transfers the byte data to the signal line 28a.
Output to 8b.

30 is an amplifier that inputs and amplifies the signal of the signal line 6a. The amplified signal is output to the signal line 30a.

That is, since the signal sent from the other party's facsimile machine is attenuated by the telephone line, which is the transmission medium, before reaching the facsimile machine, the signal is amplified by the amplifier 30.

32 is a binarization circuit which inputs the signal of the signal line 30a and performs binarization with respect to a certain reference voltage. The binarized signal is output to the signal line 32a.

34 is a tonal counter which inputs the signal of the signal line 32a and measures the time of one cycle of the signal. This one cycle time allows the frequency of the received signal to be recognized. This tonal counter is used to recognize the frequency of the signal sent to the line by the other party's facsimile machine.

FIG. 3 is a waveform diagram showing the signal on the signal line 6a and the binarized signal on the signal line 32a. Here, the binarized signal is further frequency-divided, the time of one period T is measured,
The frequency is then determined. As a method of measuring one period T, a certain clock (in this example, 77
．． 76kH2). In this case, for example, a 2100 Hz signal corresponds to 37 clocks. That is, when the number of clocks for one period is between 35 and 39, it is determined that the frequency of the signal is 2100112. Here, 35 clock is 222HIz, 39 clock is 1994Hx
corresponds to In this way, from 1994Hz to 2222Hz
When a Hz signal is detected, it is assumed that a signal with one period of 210G11z is detected.

Then, within a certain period of time, the time of one cycle is 2100.
) 1z (the number of clocks is 35 to 39) is detected multiple times, it is determined that a signal of 210011z has been detected.

When one period of measurement is completed, the tonal counter circuit 34 generates a pulse on the signal line 34a and also outputs a pulse on the signal line 34a.
4b outputs data indicating how many locks there are.

36 is a signal presence/absence detection circuit which inputs the signal of the signal line 6a, and outputs a signal of signal level "1" to the signal line 36a when a signal of -43 dBm or more is detected, and -
When a signal of 48 dBm or less is detected, the signal line 38
A signal with signal level "0" is output to a. Further, when the signal on the signal line 6a exceeds -48 dBm and is less than -43 dBm, a signal of signal level "0" or signal level "1" is output to the signal line 36a.

38 is a control circuit that performs the control described below. Here, two cases will be considered as aspects of the signal sent from the other party's facsimile machine.

Below, the explanation will be divided into two parts: control (1) and control (2).

$14 ■: When this facsimile machine is on the image receiving side, it first sends an initial identification signal and then receives the signal sent from the other party's facsimile machine. It is control.

Control (2): When the facsimile machine is the image transmitting side, it first receives the initial identification signal sent from the other party's facsimile machine, and this is the control for receiving the signal in this case.

The above-mentioned control (2) will be explained below with reference to the flowchart shown in FIG.

In FIG. 4, step Sho shows processing at the time of image reception.

In step S52, the timer T1 is set to 35 seconds.

In step S54, (GI2. Group identification)
NSF, non-standard equipment/CS1. Called station identification/DIS
, sends out a digital identification signal. Here, the GI2 signal is not sent the first time, but is sent from the second time.

In step S56, the timer T4 is set to 3 seconds or 4.5 seconds. Here, in the case of automatic reception, set 3 seconds to timer T4, and in the case of manual reception,
Set timer T4 to 4.5 seconds.

Step 558 &: It is ccITT a notice V2
It is determined whether a 1 no high signal has been received.

When the binary signal of CCITT a@V21 is received, the process proceeds to Stellaf S60. CCITT afrV2
If a binary signal of 1 is not received, the process advances to step S82.

Step 560 represents transition to G3 mode binary procedure.

In step S62, the GC2 signal or the PI
It is determined whether an S (procedure interruption) signal is detected. G
When detecting the C2 signal or the PtS signal, the process advances to step S64. If the GC2 signal or the PtS signal is not detected, the process advances to step S68.

Step S64 represents transition to a tonal procedure. The facsimile device according to this embodiment is CCIT
T recommendation G2. G3. Since it is assumed that the device has a function, a GC2 signal and a PtS signal are received as tonal signals. Here, when receiving the GC2 signal,
Transmission is performed in G2 mode, and when a PtS signal is received, the process proceeds to telephone mode.

In step S8B, it is determined whether the timer T4 has timed out. When timer T4 times out, the process proceeds to step 588. If the timer T4 has not timed out, the process advances to step 558.

In step 5611, it is determined whether the timer TI has timed out. When the timer T1 times out, the process proceeds to step 570. If the timer TI has not timed out, the process proceeds to step 554.

In step 570, a DCN (disconnection command) signal is sent.

Step S72 represents line disconnection.

In the schematic flowchart shown in FIG. 4, functions unique to this embodiment are not shown.

Next, the details of the control procedure according to this embodiment are shown in FIG.
This will be explained with reference to (5).

In FIG. 5, step S80 represents processing on the image receiving side.

In step S82, the telephone line is connected to the facsimile machine. Specifically, a signal of signal level "1" is output to the signal line 38a.

In step S84, 5IGTRC(SIGNA
LTRNC0NTR0L) Set the flag to "0".

In step 588, the process waits for 2 seconds.

In step S88, it is determined whether or not the reception is automatic. If the reception is automatic, the process advances to step 590. If it is manual reception, the process advances to step 594.

In step S90, a CHD (called station identification) signal is sent.

In step 592, T4SAV is set to 3 seconds.

In step 594, T4SAV is set to 4.5 seconds, and in step 59B, timer TI is set to 35 seconds.

In step 598, flag 5IGTRC is set to "0".
” is determined. Here, when transmitting the initial identification signal, control is performed such that the GI2 signal is not transmitted only the first time. When flag 5IGTRG is "O", the process advances to step 5102. Also, flag 5 IGTRC
When is not rQJ, the process proceeds to step 100.

In step 5100, the GI2 signal is sent.

Specifically, it generates a pulse on the signal line 38c, starts sending out the GI2 signal, and waits for a pulse to be generated on the signal line 17b. When a pulse is generated on the signal line 17b, the process returns to step 5104.

In step 5102, flag 5IGTRC is set to 1.
Set.

In step 5104, NSF-C5I-
Sends a Dis signal. Specifically, by sending byte data to the signal line 38b every time a pulse is generated on the signal line 14a, the NSF-[:SI-Dis signal is sent. The last flag is one.

In step 5106, the time stored in T4SAV is set in timer T4.

In step 5toa, 00)( is set in the area BIRCO for storing the received data.

In step 5110, OOH is set in the area BIRCI in which the received data is stored.

In step 5112, echo timer E[:H
Set 800m5 to TIM.

In step 5114, two consecutive bytes of 7EH
(01111110B) “1” when a pattern is detected
The flag FLGIDT, which is set in , is set to "0".

In step 511B, the flag FLGDET is set to "
Set "O".

In step 5118, a counter CNTBY is used to count the number of bytes when receiving one frame.
Set "0" to T.

In step 5120, when the frequency of one cycle of the signal is analyzed and it is determined that it is 2100 Hz 788 times, it is determined that the GC2 signal has been detected. The counter CN7210 used to count these 788 times is set to 788. 1 every 2 cycles
It is possible to perform frequency analysis twice in 0.75 seconds.
This corresponds to detecting 00H2.

In step 5122, when the frequency of one period of the signal is analyzed, it is determined that it is 482 Hz.
If it occurs 31 times, it is determined that a PIS signal has been detected. The counter CNT462 used to count these 231 times is set to 231. This corresponds to detecting 462 Hz, which allows frequency analysis to be performed once every two periods.

In step 5124, it is determined whether a 300 b/s byte clock has been generated. Specifically, it is determined whether a clock is generated on the signal line 28a.

When a byte clock of 300b/s occurs (that is, when a clock is generated on the signal line 28a), step 5
Proceed to 160. If a byte clock of 3 QOb/s is not occurring (that is, no clock is being generated on the signal line 28a), the process advances to step 512B.

It is determined whether or not the Stellaf 5126 code is detected as "o", that is, a 2-byte continuous flag pattern (7E old) is detected.FLGI
When DT is "0", that is, when a continuous 2-byte flag pattern (7EH) is not detected, step 51281. :move on. When FLGIDT is “1”, that is, a 2-byte continuous flag pattern (7E
H), the process advances to step 5150;
Tonal signal analysis is not performed.

In step 5128, SED (Signal
It is determined whether or not EnergyDetect) is 1, that is, whether the signal level of the signal line 38a is "1". When SED is 1, that is, signal line 3
When 6a is the signal level "1", step 5130
Proceed to To + Louis 28 (J + I! + 2tFr8: Yu #
7 CCnA<r/1, -va, that is, when the signal line 36a is at the signal level "0", the process proceeds to step 5150 and the tonal signal is not analyzed.

Steps 5126 and 5128 above represent parts unique to this embodiment.

In step 5130, it is determined whether the analysis of one period of the tonal signal has been completed, that is, whether a pulse has occurred on the signal line 34a.

When the analysis of one period of the tonal signal is completed, that is, when a pulse is generated on the signal line 34a, the process advances to step 5132. Further, if the analysis of one period of the tonal signal has not been completed, that is, if no pulse is generated on the signal line 34a, the process advances to step 5150.

In step 5132, tonal data (ie, the signal on signal line 34b) is input.

In step 5134, it is determined whether the currently received one-cycle signal is 2100 Hz. If the received one-cycle signal is now 2100 Hz, the process advances to step 5136. The signal of one period received now is 2100
If it is not Hz, proceed to step 5142.

In step 5136, the value of counter CNT210 is decremented by one.

In step 5138, it is determined whether the value of counter CNT210 is negative, that is, whether the GC2 signal has been detected. When the value of the counter CNT21G is negative, that is, when the GC2 signal is detected, the process proceeds to step 5140. When the value of counter CNT210 is positive or negative, that is, when the GC2 signal is not detected, the process advances to step 5150.

Step 5140 represents determining that the GC2 signal has been received and proceeding to the G2 reception mode.

In step 5142, it is determined whether the currently received one-cycle signal is 462H2. If the received one-cycle signal is 462Hz, step 51
Proceed to step 44. If the received one-cycle signal is not 462 Hz, the process advances to step 5150.

In step 5144, the value of counter CNT462 is decremented by one.

In step 5146, it is determined whether the value of counter CNT462 is negative, that is, whether the PIS signal has been detected. When the value of counter CNT482 is negative, that is, when the PIS signal is detected, the process advances to step 5148. When the value of counter CNT462 is positive or zero, that is, when no PIS signal is detected, the process advances to step 5150.

Step 5148 indicates that it is determined that a PIS signal has been received and that the process proceeds to telephone mode.

In step 5150, it is determined whether timer T1 has timed out. When the timer TI times out, the process proceeds to step 5154. Timer T
If I has not timed out, step 51
Proceed to step 52.

In step 5152, it is determined whether timer T4 has timed out. When the timer T4 times out, the process proceeds to step 598. Timer T4
has not timed out, step 512
Proceed to step 4.

In step 5154, the DCN (disconnect command)
Send a signal. Specifically, the DCN signal is sent by sending byte data to the signal line 38b every time a pulse is generated on the signal line 14a. The last flag is one.

In step 5156, the telephone line is connected to the telephone side. Specifically, the signal level "1" is applied to the signal line 38a.
Outputs the signal.

Step 5158 represents an off state.

In step 5160, echo timer EC:)
Whether ITIM timed out or not, i.e. (G
I2) - NSF - C5I - After sending the DIS signal, it is determined whether 600 m5 has elapsed. If the echo timer EC)ITIM times out, that is, if 600 m5 has elapsed since the sending of the (GI2) - NSF-C3I-Dis signal, the process proceeds to step 5162 to receive the binary signal. On the other hand,
Echo timer EC:) If ITIM has not timed out, i.e. (GI2) ・NSF −(
:If 600 m5 has not elapsed since the sending of the SI-llll5 signal, the process advances to step 5126 and a tonal signal is received. This indicates that when your own aircraft sends a signal and receives a signal sent from the other machine, reception of tonal signals begins immediately, and reception of binary signals begins after a certain period of time has elapsed. ing. This is a part unique to this embodiment. As a result, no malfunction will occur for echoes of 600 m5 or less.

In step 5162, the received binary data (i.e., data on signal line 28b) is transferred to memory BIR.
Store in C2.

In step 5164, a counter BITCTI is used to count the received binary data (8 bits).
Set 8 to .

In step 5168, it is determined whether the value of memory BIRCO is 7EH (ie, flag pattern). When the value of memory BIRCO is 7EI+ (ie, flag pattern), the process proceeds to step 5168. If the value of memory BIR(:O) is not 7EH (ie, flag pattern), the process advances to step 5174.

In step 5168, the flag FLGIDT is set to 0.
It is determined whether or not. When the flag FLGIDT is 0, that is, when two consecutive bytes of 7EH (flag pattern) are not detected, the process advances to step 5170. When the flag FLGIDT is not 0, that is, when a continuous 2-byte 7EH (flag pattern) is detected, the process advances to step 5180.

In step 5170, it is determined whether the value of memory BIRGI is 7EH (ie, flag pattern). If the value of memory BIRCI is 7EH (i.e.
flag pattern), the process advances to step 5172. If the value of memory BIRCI is not 7EH (ie, flag pattern), the process advances to step 5174.

In step 5172, two consecutive bytes of 7E
)I (flag) pattern was detected, so the flag FL[
Set "1" to DT.

In step 5174, it is determined whether the counter BITCTI is "0", that is, whether all the byte data input in step 5162 have been checked. When the counter BITCTI is "0", that is, when all the byte data input in step 5162 have been checked, the process advances to step 5184. On the other hand, if the counter BITCTI is not "O", that is, if all of the byte data input in step 5162 has not been checked, the process advances to 5176.

In step 517B, Mesosu 81RC2, 81
11C1° Move the data of BIRCO to the right one bit at a time. This situation is illustrated in FIG.

In step 5178, counter BIT[:Tl
Decrease the value of by 1.

In step 5180, it is determined whether the value of memory BIRCI is 7EH (ie, flag pattern). If the value of memory BIRCI is 7EH (i.e.
flag pattern), it is determined that the flag patterns are continuous, and the process advances to step 5174. Memory BIRCI value is 7EH (i.e. flag pattern)
If not, it is determined that the transmission of the preamble has ended, and the process advances to step 5182.

In step 5182, the flag FLGDET indicating that the last flag of the preamble has been detected is set to "1".
”.

In step 5184, the flag FLGDET is set to “
0'', that is, whether or not the last flag of the preamble has been detected. flag FLG
When DET is "0", that is, when the last flag of the preamble has not been detected, the process advances to step 512B. On the other hand, when the flag FLGDET is "1", that is, when the last flag of the preamble is detected, the process advances to step 5186.

The process proceeds to step 5186 if a continuous flag pattern of 2 bytes or more is detected, and then a pattern other than the flag pattern is detected.

Here, the final part of the binary signal sent by the machine itself has one flag. Therefore, the flag of the final part of the binary signal sent by the own machine is not detected and the process does not proceed to step 5186.

In step 5186, a binary signal is received. That is, every time a 300 b/s byte clock (byte clock of signal line 28a) is generated, byte data is input, and while calculating 0 delete and Fe2,
Write byte data to memory.

The number of bytes received is indicated in counter CNTBYT. Here, when the timer T1 times out while receiving a binary signal, it sends a DCN (disconnection command) signal, then connects the telephone line to the telephone side and turns it off.
becomes. Further, when the flag of the final portion is detected, the process advances to step 5188. 200 while receiving binary signal
If it is detected that the CD (carrier detect) is "O" for ms continuously, the process advances to step 5108.

Furthermore, the number of bytes in one frame (1, NTBYT) is 12.
If the number exceeds 8, the process also proceeds to step 5108. this is,
This is a function unique to this embodiment. Here, the counter BIT
It also controls CTI, etc.

In step 5188, it is determined whether the number of bytes (CNTBYT) of the currently received frame is less than five. If the number of bytes in the received frame is less than 5, the process advances to step 5108. Also, if the number of bytes of the received frame is 5 or more, step 5190
Proceed to. Here, the number of bytes when correctly receiving the binary signal is at least 5 bytes (address, control, facsimile control, facsimile information field, frame check sequence 2 bytes).

In step 5190, it is determined whether the frame check sequence is correct. If the frame check sequence is correct, proceed to step 5192. If the frame check sequence is incorrect, step 5
Proceed to step 108.

In step 5192, the facsimile information field of the received binary signal is analyzed.

In step 5194, the binary code just received is
It is determined whether the data is a CRP (command retransmission request) signal. If the binary data just received is a CRP signal, the process advances to step 5210. Further, if the binary data just received is not a CRP signal, the process advances to step 5196.

In step 5196, it is determined whether the currently received frame is the last frame.

If the currently received frame is the last frame, the process advances to step 5198. Further, if the currently received frame is not the last frame, the process advances to step 5206.

In step 5198, it is determined whether the currently received binary signal is the same as the previously sent binary signal. If the binary signal just received is the same as the previously sent binary signal, step 52
Go to 00. Further, if the binary signal just received is different from the binary signal sent immediately before, step 5212
Proceed to.

In step 5200, it is determined whether the binary signal just received is a DIS (digital identification signal) signal. Further, if the binary signal just received is a DIS signal, the process advances to step 5202. Furthermore, if the binary signal just received is not an IS signal, it is determined to be an echo and the process proceeds to step 5108.

In step 5202, it is determined whether or not the call is automatically received. If there is no incoming call from your MjJ, step 520
Proceed to step 4. When the call is automatically received, detecting a DNS group signal is meaningless, so step 51
Proceed to 08.

In step 5204, it is determined whether the PIF (facsimile information field) of the binary signal sent just before and the binary signal just received are the same. If the PIF of the binary signal sent just before and the binary signal just received are different, the process advances to step 5212. Furthermore, if the PIF of the binary signal sent just before and the binary signal just received are the same, it is determined that it is an echo, and the process proceeds to step 5108.

Steps 5198 to 5204 are measures against echo. This is a feature unique to this embodiment.

In step 520B, the flag FLGDET is set to “
0”.

In step 5208, the flag CNTBYT is set to “
0”.

In step 5210, step 521 to be described later
V21 signal (7) CD showing 2 to step 5240
After confirming that =0, the process advances to step 398.

In step 5212, timer T2 is set to 10 seconds.

In step 5214, memory BIRCO is 0;
It is determined whether the pattern is ++ (flag pattern). When the memory BIRCO is 7EH (flag pattern), the process advances to step 5216. Also, if the memory BIR (0 is not 7EH (flag pattern)), step 521
Proceed to step 8.

In step 5216, memory BIRCI is 7E.
It is determined whether the pattern is H (flag pattern). When memory B IR[:1 is 7EH (flag pattern), it is determined that the flag signals are continuous, and the process advances to step 5218. Also, memory BIRCI is not 7EH (flag pattern) (memory BIRIO is 7E) l(
flag pattern), it is determined that a closed flag has been detected, and the process advances to step 5236.

In step 5218, counter BIT[:Tl
It is determined whether or not is "O". counter BITC
When TI is "0", the process advances to step 5224. Further, when the counter BITCTI is not "o", the process advances to step 5220.

Step 5220 inputs memory BIRC2, BI
R.C.I.

Move the BIRCO data to the right one bit at a time.

In step 5222, counter BITII:T
Decrease the value of l by 1.

In step 5224, it is determined whether timer T2 has timed out. When timer T2 times out, the process advances to step 5232.

On the other hand, when timer T2 has not timed out,
Proceed to step 5226.

In step 5226, it is determined whether a 300 b/s byte clock is generated, that is, whether a clock is generated on the signal line 28a.

When a byte clock of 300 b/s occurs, that is, when a clock is generated on the signal line 28a, step 5 is performed.
Proceed to 228. Further, when a 300 b/s byte clock is not generated, that is, when a clock is not generated on signal 1528a, the process advances to step 5224.

In step 5228, the received binary data (data output to the signal line 28b) is transferred to the memory BI.
Store in RC2.

In step 5230, a counter BITCTI is set to 8.

In step 5232, the telephone line is connected to the telephone set. Specifically, the signal level "0" is applied to the signal line 38a.
Outputs the signal.

Step 5234 represents an error.

In step 5236, timer T2 is set to 1 second.

In step 5238, the S
It is determined whether ED (Signal Energy Detect) is detected to be "O". Whether this SED is “0” or “1” is determined by the signal line 36.
Input the signal a and make a decision. S continuously for 200m5
When it is detected that ED is "0", step 52
Go forward 42 ni. In addition, for 200m5, the TESED was “0”.
”, step 5240
Proceed to.

In step 5240, it is determined whether timer T2 has timed out. When timer T2 times out, the process advances to step 5242. On the other hand, if timer T2 has not timed out, step 5
Proceed to 238.

Steps 5212 to 5240 indicate functions unique to this embodiment.

Step 5242 indicates that the reception of the 300 b/s binary signal is completed and the process proceeds to the next operation based on the received signal.

In FIG. 5 described above, when the byte clock to 300b is generated (determined in step 5124), 30
Heading to the analysis of 0b/s. In the analysis of 300 b/s, if it is not determined that a binary signal has been received, the process advances to step 5126.

Furthermore, when the analysis of one cycle of the tonal signal is completed (determined in step 5130), the process proceeds to the analysis of the tonal signal.

In the analysis of the tonal signal, if it is determined that no tonal signal has been received, the process advances to step 5124.

In this way, when it is necessary to receive tonal and binary signals simultaneously, it is possible to always receive tonal and binary signals without overlooking all the received signals. This is a feature unique to this embodiment.

Next, the above-mentioned control (2) will be explained with reference to the flowchart shown in FIG.

In FIG. 70, step 5250 represents processing on the image sending side.

In step 5252, a timer Tl is set to 35 seconds.

Step 5254km is [:CITT Recommendation V2]
It is determined whether or not a binary signal of 1 has been received.

[: If a binary signal of CTTT recommendation V21 is received, proceed to step 5256. Also, CCITT Recommendation V
If the 2 Recommendation 21 Recommendation signal has not been received, the process advances to step 5258.

Step 5256 represents transition to G3 mode binary procedure.

In step 5258, it is determined whether the GI2 signal is detected. When the GI2 signal is detected, the process advances to step 5260. On the other hand, if the GI2 signal is not detected, the process advances to step 5262.

Step 5260 represents transition to a tonal procedure. The facsimile device according to this embodiment has a CCI
TT Recommendation G2. Since it is assumed that the device has the G3 function, it is necessary to receive the GI2 signal as the tonal signal.

In step 5262, it is determined whether timer T1 has timed out. Once the timer T1 has expired, the process proceeds to step 5284. Also, when timer T1 has not timed out,
Proceed to step 5254.

Step 5264 represents line disconnection.

In the above-described schematic flowchart shown in FIG. 7, functions unique to this embodiment are not shown. Therefore, Figure 8 (
Referring to the detailed flowcharts shown in 1) to (4),
The control procedure of this embodiment will be described.

In FIG. 8, step 5270 represents processing on the image sending side.

In step 5272, the telephone line is connected to the facsimile machine. Specifically, a signal of signal level "1" is output to the signal line 38a.

In step 5274, timer T1 is set to 35 seconds.

In step 5276, the counter GI2DET for counting how many times the GI2 signal is detected is set to "0".
”.

In step 5278, the area BIRCO1,:OOH for storing the received data is set.

In step 5280, the area BIR (:1 = 00) 1 is set for storing the received data.

In step 5282, 2 consecutive bytes 7E)
The flag FLGIDT, which is set to "1" when l (flag pattern) is detected, is set to "o".

In step 5284, the flag FLGDET is set to r.
Set O.

In step 5286, a counter [:
Set NTBYT to “0”.

In step 5288, when the frequency of one period of the signal is analyzed and it is determined that it is 1850 Hz 463 times, it is determined that one 612 signal has been detected.

The counter used to count these 463 times (:
Set 463 to NT185. It is possible to perform frequency analysis once every two periods, and these 463 times correspond to detecting 1850 Hz for a total of 4 a 3 x −x 2 = Q, 5 seconds.

In step 5290, it is determined whether a 300 b/s byte clock has occurred. Specifically, the signal, tJ! It is determined whether a clock is generated at 28a. When a byte clock of 300 b/s is generated, that is, when a clock is generated on the signal line 28a, the process advances to step 5332. On the other hand, when a 300 b/s byte clock is not generated, that is, when a clock is not generated on the I= line 28a, step 5292 is performed.
Proceed to.

In step 5292, FLGIDT is "o"
It is determined whether or not, that is, whether or not a continuous 2-byte flag pattern (7EH) is detected. When FLGIDT is "0", that is, when a continuous 2-byte flag pattern (7EH) is not detected, the process advances to step 5294. Also, FLGIDT is “1”
In other words, when a 2-byte consecutive flag pattern (
7E) When 1) is detected, the process advances to step 5306 and no analysis of the tonal signal is performed.

In step 5294, SED (Signal
It is determined whether or not EnergyDetect) is "1", that is, whether the signal level of the signal line 36a is "1". When this SED is "1", that is, when the signal line 36a is at the signal level "1", the process advances to step 5296 to analyze the tonal signal. On the other hand,
When SED is "0", that is, when the signal line 36a is at the signal level "0", the process advances to step 5306;
Tonal signal analysis is not performed.

Steps 5292 and 5294 above are features specific to this implementation.

In step 5296, it is determined whether the analysis of one period of the tonal signal has been completed, that is, whether a pulse has occurred on the signal line 34a.

When the analysis of one period of the tonal signal is completed, that is,
When a pulse on signal line 34 occurs, the process proceeds to step 5298. On the other hand, if the analysis of one period of the tonal signal has not been completed, that is, if no pulse is generated on the signal line 34a, the process advances to step 5306.

In step 5298, the tonal data (ie, the signal on the signal line 34b) is input manually.

In step 530Q, it is determined whether the one-cycle signal just received is 1850 Hz. If the currently received one-cycle signal is 1850 Hz, the process advances to step 5302. The signal of one period just received is 1850
If it is not Hz, the process advances to step 5306.

In step 53G2, it is determined whether the value of the counter CNT185 is negative, that is, whether the 18 SOIIz signals have been detected for a total of 0.5 seconds or more. When the value of counter CNT185 is negative, that is, 185
0) When the IZ signal is detected for a total of 0.5 seconds or more, the process advances to step 5306. Also counter CNT1
When the value of 85 is positive or τ, that is, 1850H
If the z signal has not been detected for a total of 0.5 seconds or more, the process advances to step 5304.

In step 5304, the value of counter CNT185 is decremented by one.

In step 5306, it is determined whether or not consecutive 5ED=O of 200 m5 or more have been detected. Here, even if there is background noise, the randomness of the signal is checked to determine if the signal is disconnected.

If a continuous signal disconnection of 200 m5 or more is detected, the process advances to step 5308. Further, if a continuous signal disconnection of 200 m5 or more is not detected, the process advances to step 5326.

In step 5308, it is determined whether the value of the counter CNT185 is negative, that is, whether the 1850IIz signal has been detected for a total of 0.5 seconds or more. When the value of counter CNT185 is negative, that is, 1115
When a 0 Hz signal is detected for a total of 0.5 seconds or more, the process advances to step 5310. When the value of the counter CNT185 is positive or τ, that is, when the signal of 1850)1z has not been detected for a total of 0.5 seconds or more, the process advances to step 5320.

In step 5310, a signal disconnection is detected, and
Since the total signal of 1850 Hz has been detected for more than 0.5 seconds, GI2CNT is incremented by 1.

Stellaf 5312 Nioiteha, FLGIDT Ka "o-"
It is determined whether or not there is a problem. Here, FLGIDT is “
o'', the process advances to step 5314. On the other hand, FI
If JIDT is not "O", the process advances to step 5318.

In step 5314, it is determined whether the counter GI2DET is less than 2, that is, whether the GI2 signal has been received less than twice. If the counter GI2DET is less than 2, that is, the GI2 signal is
Ei Tribute 1. ? , + Yu I ÷ 7 books 1. If the counter GI2DET is 2 or more, that is, if the GI2 signal is received two or more times, the process advances to step 5316.

In step 531B, it is determined that the other device is 62, and the process proceeds to G2 mode transmission.

In step 5318, it is determined whether the counter GI2DET is less than 3, that is, whether the GI2 signal has been received less than three times. If the counter GI2DET is less than 3, that is, if the GI2 signal has been received less than three times, the process proceeds to step 5320. On the other hand, if the counter GI2DET is 3 or more, that is, GI2
If the signal is received three times, proceed to step 5318.

Steps 5300 to 5318 are functions unique to this embodiment.

In step 5320, FL[OT is set to "0".

In step 5322, FLGDET is set to "0".

In step 5324, counter CNT1B5 is set to r463J.

In step 5326, it is determined whether timer T1 has timed out. When the timer T1 times out, the process advances to step 5328. Also, when timer T1 has not timed out,
Proceed to step 5290.

In step 5328, the telephone line is connected to the telephone side. Specifically, the signal level "0" is applied to the signal line 38a.
Outputs the signal.

Step 5330 represents an error.

Steps 5332 to 5362 are shown in FIG.
This corresponds to steps 5162 to 5192 shown in 3,) and (4).

The above-mentioned step 5358 and the determination in step 5358 are functions unique to this embodiment.

In step 5364, it is determined whether the frame just received is the last frame.

If the received frame is the last frame,
Proceed to step 5366. Further, if the currently received frame is not the last frame, the process advances to step 5370.

Step 5366 is step 5 shown in FIG. 5(5).
Detection of carrier disconnection as described in steps 212 to 5240 is performed. This is an effect unique to this embodiment.

Step 5368 represents receiving the 300 b/s binary signal and proceeding to the next operation based on the received signal.

Step 53701. :Oite says to FLGDET “o
”.

In step 5372, CNTBYT is set to "o".

In FIG. 8 described above, when a byte clock of 300 b/s is generated (determined in step 5290),
Heading to the analysis of 300b/s. In the analysis of 300b/S, if it is not determined that a binary signal has been received, the process advances to step 5292.

Furthermore, when the analysis of one cycle of the tonal signal is completed (determined in step 5296), the process proceeds to the analysis of the tonal signal. In the analysis of the tonal signal, if it is determined that no tonal signal has been received, the process advances to step 5290.

In this way, when it is necessary to receive tonal and binary signals simultaneously, it is possible to always receive tonal and binary signals without overlooking all the received signals. This is a feature unique to this embodiment.

In the embodiments described so far, a facsimile machine having a 62.63 function has been described, but it goes without saying that the present invention can also be applied to other communication devices.

(Hereinafter, blank space) [Effects of the Invention] As described above, according to the present invention, by appropriately changing the start time of identifying the received signal or the judgment criteria,
Since the configuration is such that invalid signals such as echo signals are removed, reliable communication can be achieved without causing communication errors.

[Brief explanation of the drawing]

:JS1 is an overall configuration diagram of a facsimile device according to the present invention, and FIG. 2 is a block diagram showing an embodiment of a facsimile device to which the present invention is applied. FIG. 3 is a diagram for explaining a 1-null counter. FIG. 4 is a flowchart showing the order of control to be executed by the control circuit 3B as the image receiving side, and FIGS. 5(1) to 5(5) are the steps to be executed by the control circuit 38 as the image receiving side:! Flowchart showing detailed control procedures. Figure 6 is a diagram showing the operation when storing the received binary data, and Figure 7 is what the control circuit should execute on the image sending side. !
Flowchart showing the order of sub-control, FIG. 8(4) to FIG. 8(4) are flowcharts showing the order of details 2 to controller j to be executed by the control circuit 38 as the image transmitting side. 2...NC1J. 4...' packing machine, 6... Hybrid circuit, 8... Reading circuit, 10... Encoding circuit. 12... V27ter or V29 modulator, 14...
・・Parallel/serial conversion circuit, 1B-V2L 9a
! , 17... [12 signal input/output circuit. 18...Power 0T1 circuit, 20...V27trr or V29 demodulator, 22...
... 1 is an encoding circuit, 24... is a recording circuit. 26...V21 demodulation base, 28...serial/parallel conversion circuit, 30...I
! : 1 width circuit, 32... 2-1 circuit, 34... Tonal counter circuit, 36... Signal presence/absence detection circuit. 38...control circuit. Figure 3 Figure 6

Claims (1)

[Scope of Claims] 1) A data receiving device that receives control signals and data signals, comprising a determining means for determining the type of the received signal, and a determination start time or identification start time of the received signal according to the output of the determining means. A data receiving device characterized by comprising a control means for appropriately changing a discrimination criterion. 2) If the received signal is a tonal signal, the identification is started immediately, and if the received signal is a binary signal, the identification is started after a predetermined time has elapsed. The data receiving device according to item 1. 3) When the received signal is a transmission signal of the own station due to an echo, the criterion for determining that the received signal is invalid is changed.
The data receiving device described in Section 1.