JPS62281462A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To increase working speed by short-channeling and the lowering of the resistance of a gate electrode, and to improve the degree of integration by constituting a gate electrode for an n channel MISFET of an n-type polycrystalline semiconductor film and a high melting-point metallic film and organizing a gate electrode for a p channel MISFET of a p-type polycrystalline semiconductor film and a high melting-point metallic film. CONSTITUTION:A gate electrode for an n channel MISFET consists of an n-type polycrystalline semiconductor film 12 and a high melting-point metallic film 15 formed onto the film 12, and a gate electrode for a p channel MISFET is composed of a p-type polycrystalline semiconductor film 14 and a high melting-point metallic film 15 shaped onto the film 14. The polycrystalline semiconductor films for the gate electrodes are formed, an n-type impurity and a p-type impurity are introduced selectivley into the polycrystalline semiconductor films to shape an n-type region section and a p-type region section, and Ti films are formed onto the polycrystalline semiconductor films. The Ti films and the polycrystalline semiconductor films are patterned and removed partially, thus forming said gate electrode for the n channel MISFET and said gate electrode for the p channel MISFET.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] In the semiconductor device of the present invention, the gate electrode of an n-channel ME S FET is made of a NyIi polycrystalline semiconductor film and a high melting point metal film formed thereon. p channel MI S FE
The gate electrode of T is characterized by being composed of a P-type multicrystalline semiconductor film and a high melting point metal film formed thereon.

As a result, even if the dark value voltage is the same, a higher concentration semiconductor substrate and well region can be used, so the punch-through voltage becomes higher and a short channel can be realized.

Also, since the gate electrode of the n-channel FET and the gate electrode of the p-channel are connected by the high melting point metal of the gate electrode part, PJ! ! There is no need to provide a special contact part for connecting the gate electrode part of the polycrystalline semiconductor film and the gate electrode part of the N-type polycrystalline semiconductor film, and therefore high integration is possible.

Three methods have been proposed for manufacturing the semiconductor device of the present invention. The first manufacturing method is to selectively introduce N-type impurities and P-type impurities into a polycrystalline semiconductor film before forming a high-melting point metal film, thereby forming an N-type polycrystalline semiconductor film and a P-type polycrystalline semiconductor film. The method is characterized in that the refractory metal film and the polycrystalline semiconductor film are then patterned to form the gate electrode of each FET.

The second manufacturing method selectively uses N5! after forming a polycrystalline semiconductor film and a high melting point metal film. Impurities and P-type impurities are introduced into the polycrystalline semiconductor film to form an N-type polycrystalline semiconductor film and a P-type can crystalline semiconductor film.

The method is characterized in that the high melting point gold film and the polycrystalline semiconductor film are then patterned to form gate electrodes of each FET.

In the third manufacturing method, a polycrystalline semiconductor film and a high melting point metal film are formed and then patterned to form the gate electrode of each FET in advance, and then an N-type impurity is implanted into the n-channel MISFET side. A gate electrode made of a type polycrystalline semiconductor film and a high melting point metal film and an N5 source/drain impurity region are formed in a self-aligned manner, while a p-channel M
A feature is that P-type impurities are implanted on the ISFET side to form a gate electrode made of a P-type multicrystalline semiconductor film and a high-melting point metal film and P-type source/drain impurity regions in a self-aligned manner.

The semiconductor device of the present invention can be manufactured by any of the first to third manufacturing methods.

1st. According to the second manufacturing method, the polycrystalline semiconductor film of the gate electrode portion is changed to N type or Py! ! Since L formation and formation of the source and drain impurity regions are performed in separate steps,
This has the advantage that it is easy to control the impurity concentration and the depth of the impurity region. On the other hand, according to the third manufacturing method, converting the polycrystalline semiconductor film in the gate electrode portion to N-type or P-type and forming the source/drain impurity regions are performed at the same time, which has the advantage of shorter process steps. be.

[Industrial application field]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, to an electrode structure of a CMISFET and a method of manufacturing the same.

[Conventional technology]

FIG. 4 is a sectional view of a CMOS structure of a conventional semiconductor device. 1 is an N-type Sl substrate, on which a p-channel FET 8 is formed.

2 is a P-well region formed in the N-type St substrate 1, and an n-channel FET 9 is formed on the P-well region 2.

Note that 3 is the field S+ (hl!l), and 4 is the interlayer insulating film.

5 is gate 51021P! It is.

By the way, when trying to make the p-channel FET 8 a short channel, use P5! as its gate electrode. A polycrystalline Si gate electrode 6 is used. This is because the threshold voltage of the p-channel FET 8 can be made lower (to the depletion side) by making the gate electrode P-type, so even if the same threshold voltage is obtained, the N-type 5 with a higher impurity concentration
This is because one substrate 1 can be used. For this reason, the punch-through voltage between the source and drain increases, so
High-speed P-channel FE that enables short channelization
T can be formed.

Similarly, when short channeling the n-channel FET 9, the n-type polycrystalline S1 gate electrode 7 is used as its gate electrode. In this case, the punch-through voltage can be increased by increasing the impurity concentration in the P-well region 2.

[Problem that the invention seeks to solve]

By the way, when forming an OMO3FET by p-channel FET8 and n-channel FET9, the gate electrode 6 of FET8 and the gate electrode 7 of FET9 must be electrically connected.

Since the impurity types of these gate electrodes are different, if left as is, a PN junction will occur, which is disadvantageous. To solve this problem, an A1 layer is provided to electrically connect the gate electrode 6 and the gate electrode 7, but since a contact area for the connection must be provided, the degree of implantation is reduced. There is.

The present invention has been created in view of the problems of the prior art, and provides a semiconductor device and a method for manufacturing the same that enable high speed and high integration by reducing the resistance of a short channel and gate electrode. For the purpose of providing.

[Means for solving problems]

In the semiconductor device of the present invention, the gate electrode of the n-channel MISFET is composed of an N-type polycrystalline semiconductor film and a high-melting point metal film formed thereon, and the gate electrode of the p-channel MISFET is composed of a P-type polycrystalline semiconductor film and a high-melting point metal film formed thereon. It is characterized by consisting of a high melting point metal film formed on top.

The first method of manufacturing a semiconductor device of the present invention includes gate 'il
a step of forming a polycrystalline semiconductor film for a t-electrode; and a step of selectively introducing an N-type impurity and a P-type impurity into the polycrystalline semiconductor film to form an N-type region and a P-type region. , by forming a high melting point metal film on the Seki polycrystalline semiconductor film, and patterning and partially removing the high melting point metal film and the polycrystalline semiconductor film, the NJfi polycrystalline semiconductor film and the above are formed. A step of forming a gate electrode of an n-channel MI S FET made of a high-melting point metal film to be formed, and a gate electrode of a p-channel MI 5FET made of a P-type polycrystalline semiconductor film and a high-melting point metal film formed thereon. It is characterized by having at least the following.

A second method for manufacturing a semiconductor device of the present invention includes the steps of forming a polycrystalline semiconductor film for a gate electrode, forming a high melting point metal film on the polycrystalline semiconductor film, and forming a high melting point metal film on the high melting point metal film. a step of selectively introducing an N-type impurity and a P-type impurity into the polycrystalline semiconductor film to form an N-type region and a P5 region, and patterning the high-melting point metal film and the polycrystalline semiconductor film. By partially removing the N-type polycrystalline semiconductor film and the refractory metal film formed thereon, the gate electrode of the one-channel MZ S FET, which is made up of the N-type polycrystalline semiconductor film and the refractory metal film formed thereon, and the P-type polycrystalline semiconductor film and the refractory metal film formed thereon are removed. The method is characterized in that it includes at least a step of forming a gate electrode of a P-channel MI S FET made of a high melting point metal film.

The third method for manufacturing a t-conductor device in January of this September includes a step of forming a polycrystalline semiconductor film for a gate electrode, a step of forming a high melting point metal film on the polycrystalline semiconductor film, and a step of forming a high melting point metal film on the polycrystalline semiconductor film. forming a gate electrode by patterning and partially removing the melting point metal film and the polycrystalline semiconductor 1 pattern;
On the side where the n-channel MISFET is to be formed, an N-type impurity is implanted from above the high melting point metal film to make the polycrystalline semiconductor film of the gate electrode part of the n-channel MISFET N-type, and at the same time, it is self-aligned. Step of forming N-type source/drain impurity regions and P-channel M
By injecting P-type impurities from both sides of the refractory metal film to the side where the ISFET is to be formed, the p-channel MIS
The method is characterized by at least the step of converting the polycrystalline semiconductor film of the gate electrode portion of the FET into P-type and simultaneously forming P-type source/drain impurity regions in a self-aligned manner.

[Effect]

In the uninvented semiconductor device, the gate electrode of the n-channel MISFET has an N-type polycrystalline semiconductor film.

Since the gate electrode of the p-channel MISFET has a P-type multi-crystalline semiconductor film, it is possible to increase the punch-through voltage by using a highly doped semiconductor substrate or well region, and this also prevents short channel formation. It becomes the turning part.

Furthermore, since the gate electrodes of each FET are configured to have the same high-melting point metal film, they can be connected as is in the case of a CMO5 configuration. That is, it is not necessary to provide a contact region for connecting an N-type polycrystalline semiconductor film and a P-type polycrystalline semiconductor film as in the conventional case, so that high-density planting becomes possible.

The first aspect of the present invention. According to the second semiconductor device manufacturing method, converting the polycrystalline semiconductor film in the gate electrode portion to N5 or P type and forming the source/drain regions are performed in separate steps, so the concentration and depth of each are controlled. Easy to do.

4: According to the method for manufacturing a semiconductor device of invention No. 53, converting the polycrystalline semiconductor film in the gate electrode portion to N-type or P-type and forming the source/drain regions are performed at the same time, so that the steps are more uniform in width. .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

(Embodiment of the method for manufacturing a semiconductor device according to the first invention) FIG. 1 is a diagram illustrating the method for manufacturing a semiconductor device according to the first embodiment 1J. Note that channel stoppers and the like that are not particularly related to the present invention are omitted.

(+,) Figure (a) is a sectional view of an h conductor device (formed by a well-known process), l is an N-type Sl substrate, 2
5 is a field SiO2 film, 5 is a thin gate 5102 film, and IO is a polycrystalline S1 film formed thereon.

(2) Next, after coating the entire surface with the resist film 11.

The resist film is patterned, and the region from which the resist is removed is slightly wider than the predetermined gate electrode region.

Next, phosphorus ions (Po) are implanted. As a result, polycrystalline S+Ii! An N-type region 12 is formed in Jll (FIG. 2(b)).

(3) Next, after the resist film 11 is completely removed, another resist film 13 is coated on the entire surface and patterned. In this case as well, the area from which the resist film is removed is slightly wider than the predetermined gate electrode area. It is.

Next, poron ions (Bo) are implanted. As a result, a P-type region is formed in the polycrystalline S, [10 (FIG. 1(c)).
.

(0th order resist) After removing the pattern 13 on the entire surface, 1, for example, T, 1fi 15 is deposited by sputtering technique (the same figure (
d)) In addition to the Ti film, other high melting point metal films such as an MO film or a W film may be used.

(5) Next, after the resist film 16 is deposited, the resist film is patterned (FIG. 4(e)).

(6) Next, using the resist film 16 as a mask, the T1 film 15 is
and etching the polycrystalline Si film 10 ((f) in the same figure).
).

(7) Next, after removing the entire surface of the resist film 16, another resist film 17 is covered, and the resist film 17 is patterned. Furthermore, arsenic ions (As) are implanted using the resist film 17 as a mask (see FIG. (g)).

(8) Next, after removing the entire surface of the resist film 17, another resist film 18 is deposited, and this resist film is patterned. Furthermore, poron ions (B) are implanted using the resist film 18 as a mask (see FIG. h) ).

(9) Next, after the resist film 18 is completely removed, heat treatment is performed to implant ions (B.

As.) is activated to form the source/drain 25 of the n-channel FET and the source/drain 26 of the p-channel FET ((i) in the same figure).

Thereafter, a living room insulating film, A-crossings of wiring layers, etc. are formed by well-known steps, and a predetermined FET is completed.

In this way, an n-channel FET whose gate electrode is composed of the polycrystalline Sl film 12 and Ti film 15 in the N-type region, and a P-channel FET whose gate electrode is composed of the polycrystalline S1 film 14 and Ti film 15 in the P-type region are formed. be able to.

In other words, when it comes to n-channel FETs, polycrystalline Si
By making the film N-type, the impurity concentration in the P well region 2 can be increased by the amount that the work function is shifted. As a result, the punch-through voltage between the source and drain can be increased, so that the channel can be made shorter and the speed of the n-channel FET can be increased.

Similarly, for p-channel FETs, N
The impurity concentration of type S1 substrate 1 can be increased. This makes it possible to increase the punch-through voltage between the source and drain, making the channel more short and connecting the P
The speed of the channel FET can be increased.

In addition, when connecting the gates of an n-channel FET and a p-channel FET to form an 0MO3 structure, the N-type region (polycrystalline S1 film) 1 of the n-channel FET is
2 and p-channel FET P type (polycrystalline 5illlJ) 1
4 can be connected to each other, there is no need to form a special contact region as in the conventional case, and thus high integration can be achieved.

(Embodiment of the method for manufacturing the semiconductor device 1 of the second invention) FIG. 2 is a diagram illustrating the method for manufacturing the semiconductor device 1 of the second invention. Note that FIG. 1 is referred to for the steps common to the manufacturing method of the first invention.

(1) After the process shown in FIG. 1(a), the polycrystalline S1 film 10
A T1 film 15 is then formed on the entire surface, and then a resist film 20 is deposited on the entire surface, and then the resist film 20 is patterned. After that, as shown in FIG. 2(a), phosphorus ions (
P') is implanted through the rtg15 to form an N-type region 12 in the polycrystalline Si film 10.

(2) Next, Regis)! After removing I20 from the entire surface, another resist film 21 is deposited and patterned. Then, as shown in FIG. 2(b), boron ions (B) are applied to the TI film 15. to form a P-wall region 14 in the polycrystalline S1 film io.

The subsequent steps are the same as those shown in FIGS. 1(d) to (i), so their explanation will be omitted.

In this manner, the semiconductor device (FIG. 1(i)) according to the embodiment of the present invention is also formed by the manufacturing method of the second invention. be able to.

(Embodiment of the method for manufacturing a semiconductor device according to the third invention) FIG. 3 is a diagram illustrating the method for manufacturing a semiconductor device according to the third invention. Note that FIG. 1 is referred to for the steps common to the manufacturing method of the first invention.

(1) After the process shown in FIG.
0, a T film 15 is formed, and then a resist! I! 2
After applying 2 on the entire surface, the resist +1! Patterning of fi 22 is performed (FIG. 3(a)).

(2) Next, using the resist film 22 as a mask, Ti MI5
and etching the polycrystalline Si film IO (Fig. 3(b)
)).

(3) Next, after removing the entire surface of the resist film 22, another resist film 23 is deposited, and this resist film 23 is further patterned.Next, phosphorus ions (P) are implanted using the resist film 23 as a mask. At this time, phosphorus ions enter the polycrystalline Sr film 10 via T, 1115, and P
It is injected into the surface of the well region 2 (FIG. 3(c)).

(4) Next, after removing the entire surface of the resist film 23, another resist film 24 is covered, and the resist film 24 is further patterned.Next, poron ions (Bo) are implanted using the resist film 24 as a mask (the same figure). (d)) At this time, poron ions pass through the T1 film 15 to the polycrystalline S1 film 10.
and into the surface of the N-type S1 substrate 1.

(5) After that, the resist film 24 is removed and a rough heat treatment is performed to remove the implanted ions (P.

By activating B=) and forming the source and drain of each FET, a semiconductor device as shown in FIG. 1(i) can be formed.

According to the method for manufacturing a semiconductor device according to the third aspect of the invention, the process is shortened because the process of injecting impurities into the polycrystalline SI film 10 of the gate electrode and the process of forming the source/drain are both performed. There are advantages.

〔Effect of the invention〕

As explained above, in the semiconductor device l of the present invention, the gate electrode of the n-channel MISFET has an N-type multi-crystalline semiconductor film.
Furthermore, since a P-type polycrystalline semiconductor film is formed on the gate electrode of the p-channel MISFET, short channeling is possible, and therefore high-speed operation is possible. In addition, since each gate electrode is formed with a high-melting-point full-reflection film, when creating a CMIS structure, ohmic contact can be made without providing a special contact area, allowing for high integration. Can be done.

In addition, the first aspect of the present invention. The semiconductor device of the present invention can be manufactured by the second semiconductor device manufacturing method.

Similarly, the semiconductor device of the present invention can be manufactured by the third semiconductor device manufacturing method of the present invention, and in particular, the manufacturing process can be shortened by this method.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention (FIG. 1(i) is a cross-sectional view of a semiconductor device according to an embodiment of the present invention), and FIG. FIG. 4 is a cross-sectional view of a conventional semiconductor device. FIG. (Explanation of symbols) ■...N-type Si substrate. 2...P well region. 3...-field s, O2 film, 5... gate 5iOzll≦1. 10... Polycrystalline Si [, 11, 13, 16, 17, 18, 20, 21° 22.2
3.24...Resist film, 12...N type region (polycrystalline Si film), 14...P required region (polycrystalline Si film), 15...T, film. 25.26... Source drain region.

Claims (5)

[Claims] (1) The gate electrode of an n-channel MISFET consists of an N-type polycrystalline semiconductor film and a high-melting point metal film formed on this, and the gate electrode of a p-channel MISFET consists of a P-type polycrystalline semiconductor film and a high-melting point metal film formed on this. A semiconductor device comprising a high melting point metal film. (2) The semiconductor device according to claim 1, wherein the high melting point metal film is made of Ti, Mo, or W. (3) Forming a polycrystalline semiconductor film for a gate electrode, and selectively introducing an N-type impurity and a P-type impurity into the polycrystalline semiconductor film to form an N-type region and a P-type region. forming a high melting point metal film on the polycrystalline semiconductor film; and patterning and partially removing the high melting point metal film and the polycrystalline semiconductor film to form an N-type polycrystalline semiconductor film. A gate electrode of an n-channel MISFET made of a high-melting point metal film formed on this, a p-channel MISFET made of a P-type polycrystalline semiconductor film and a high-melting point metal film formed on this.
1. A method of manufacturing a semiconductor device, comprising at least a step of forming a gate electrode of an SFET. (4) forming a polycrystalline semiconductor film for a gate electrode; forming a high melting point metal film on the polycrystalline semiconductor film; N-type impurities and P-type impurities are introduced into the N-type region and P-type impurities.
By forming a type region portion and patterning and partially removing the high melting point metal film and the polycrystalline semiconductor film, the N-type polycrystalline semiconductor film and the high melting point metal film formed thereon are separated. A semiconductor device comprising at least a step of forming a gate electrode of an n-channel MISFET consisting of a P-type polycrystalline semiconductor film and a refractory metal film formed thereon. Production method. (5) forming a polycrystalline semiconductor film for a gate electrode; forming a high melting point metal film on the polycrystalline semiconductor film; and partially patterning the high melting point metal film and the polycrystalline semiconductor film. forming a gate electrode by removing the polycrystalline semiconductor of the gate electrode portion of the n-channel MISFET by injecting an N-type impurity from above the high melting point metal film on the side where the n-channel MISFET is to be formed; A process of converting the film to N-type and simultaneously forming N-type source/drain impurity regions in a self-aligned manner, and implanting P-type impurities from above the high melting point metal film to the side where the p-channel MISFET is to be formed. A semiconductor device comprising at least the step of converting a polycrystalline semiconductor film in a gate electrode portion of the p-channel MISFET into a P-type, and simultaneously forming P-type source/drain impurity regions in a self-aligned manner. manufacturing method.