JPS62278474A - Logic circuit tester - Google Patents

Abstract

PURPOSE:To achieve a higher efficiency in the time for testing of a logic circuit, by inputting a reset signal from outside to apply the same signal to input terminals of all state memory circuits in a plurality of shift paths. CONSTITUTION:AND circuits 25 and 26 and a reset terminal 28 are added to a logic circuit tester. When a state memory circuit is not to be reset, 'H' is inputted into the terminal 28. The 'H' is inputted into the circuits 25 and 26 and hence, the circuit 25 outputs an input signal from an input terminal 12 in the scan mode as intact while the circuit 26 outputs an input signal from an input terminal 27 in the normal mode as intact. Then, when the state memory is to be reset, 'L' is inputted into the terminal 28 as reset signal indicating a reset state. The circuits 25 and 26 output the 'L' leaving out the terminal 12 in the scan mode and the terminal 27 in the normal mode. Therefore, by not using the input of a mode changeover signal input terminal 13, 'L' is outputted at an output terminal 14 by way of AND circuits 22 and 23 and an inversion OR circuit 21.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a logic circuit testing device that is capable of scan-in and scan-out.

[Conventional technology]

Figure @2 shows an example of a logic circuit testing device that is capable of scan-in and scan-out. A scan/normal mode switching device (1), and a 7-rig front (hereinafter referred to as FFF) located at the subsequent stage that captures data, holds it, and outputs the held data in synchronization with the clock.
+2) constitutes a set of seat fly nose fronts (hereinafter referred to as SFF). A chain of multiple SFFs (four shift paths (3a, 3b, 3a, 3b,
3c and 3d) are configured in parallel. 7ftpass (3b,
3c, 3d) are configured in the same way as the inside of the shift path (3a). Shift node specification terminal (lla, ll
b) are these shift no(s) (3a.

3b, 3c, 3d) to specify which one to scan in or scan out, and is connected to a decoder (4) and a multiplexer (5).

The decoder (4) specifies which shift path (3a, 3b, 3c, 3d) clock signal from the clock terminal αl+ is to be sent via the AND circuit (6), and the multiplexer (5) Which shift path (3
a, 3b, 3c+3d) to scan out terminal (
8) There is a setting to specify whether to scan out. In addition, the mode switching terminal (9) specifies the normal mode for normal operation of the 5FFt, or the scan mode for operating the 7ft pass to set data in the SFF.
It is equipped with (7) is a scan-in terminal for inputting data to be scanned-in.

@Figure 3 shows the conventional scan/normal mode switching device (1
) shows an example of the internal structure of This is an OR circuit.
It consists of an AND circuit, cn'j6, and an inverter circuit. (6) is an input terminal in scan mode, 10,000 is an input terminal in normal mode (not shown in Figure 1), and each scan/normal mode switching device (
(Ll is the mode switching signal input terminal that inputs the signal from the mode switching terminal (9), α4 is F
The output terminal to F is shown.

A conventional logic circuit testing device equipped with a scan/normal mode switching device is configured as described above.

Next, the operation will be explained. When setting to scan mode and performing scan-in/scan-out.

Input IHI from the mode switching terminal (9). Mode switching signal (2) of scan/normal mode switching device 11)
), IF5 is input, AND circuit is input manually by IHL,
ILI is connected to the AND circuit via an inverter circuit (towards).
enters. Therefore, the input terminal in scan mode @
Since the input data of is output from the output terminal α4)7)), it looks like the SFFs shown in Fig. 2 are connected in a chain ζ
Data propagates. Shift path specification terminal (lla, 1l
b) Scan-in/scan-out is either a power of 1
When one shift path (3a, 3b, 3c, 3d) is specified, the decoder (4) outputs one Hl only from the AND circuit (6) located in the previous stage of that shift path, and
'L' is output to the ND circuit (6). Therefore, the clock signal from clock terminal 4 is transmitted only to the designated shift path via the AND circuit (6).

Multi-F L/tab (5) is set to the specified shift path (3a-
F F (21
Connect the output to the scanout terminal (8). Data is manually inputted from the scan-in terminal (7) to the designated shift lot in synchronization with a clock signal, and is outputted from the scan-out terminal (9).

When setting to the normal mode and causing each F'F 121 to operate normally, ILI is input from the mode switching terminal (9).

``Ll'' is inputted to the mode switching signal input terminal (to) of the scan/normal mode switching device (1), so 1L'' is inputted to the AND circuit, and 'H1 is inputted to the AND circuit via the inverter circuit c148. do. Therefore, the output terminal (14
D> is output. The input terminal @ in normal mode is provided independently for each scan/normal mode switching device (1), and the configuration in normal operation (r shown in the figure) is ri.
The data is propagated in the same way. In addition to the clock signal from the clock terminal α07), the system clock is connected to each F F1
21 (not shown) and each F F' [21
normally operates in synchronization with this system clock.

In this conventional logic circuit testing device, the total F' F t2 in 3
To reset 1, set it to scan mode, specify the shift path, write TE'L' by scan-in, specify the other shift paths, and do the same in sequence. .

[Problem that the invention seeks to solve]

Conventional logic circuit testing equipment is configured as described above, but in order to reset all the state storage circuits, four shift paths are individually selected for each, and the states of all "C" in the shift paths are checked. It is rarely necessary to return 4 signals to scan in lL' to the memory circuit. This invention was made to solve the above-mentioned drawbacks, and all of the The purpose of this study is to obtain a logic circuit testing device in which a uniform signal is input to the state storage circuit of the circuit to reset the state.

Means for Solving Problem C] The present invention provides a scan/normal mode switching device which includes a reset terminal and is configured to output a uniform signal when a reset signal is input. The entire state storage circuit is configured such that the uniform signal is inputted as a clock signal of only one period and simultaneously reset.

[Effect]

The scan/normal mode switching device according to the present invention responds to a reset signal from a reset terminal to set all state storage circuits in a plurality of shift paths to a reset state.
i It acts like rubbing.

〔Example〕

An embodiment of the present invention has been illustrated above, and a description will be given based on it.

FIG. 1 shows an example of a scan/normal mode switching device in a logic circuit testing apparatus 1 of the present invention. Input terminal (6) in scan mode, mode switching signal input terminal □□□, input terminal - in normal mode -, FFI2]
Output terminal α to, OR circuit ■, AND circuit, lJ3
, and the inverter circuit (2) are the same as those with the same reference numerals in Figure 1, and their functions are exactly the same. AND circuit S, QB and reset terminal CS
is sold as something added to realize this invention.

The tecoder (4) in Fig. 2 is configured so that the signal from the cent terminal is input manually (not shown in detail), so that the input l of the reset signal becomes 'H' for all outputs, and the AND A clock signal from all FFs (second lock terminal 0Q) is transmitted through the circuit (6).

Figure 3) As shown in Fig. 2 (Fig. 2) In place of the conventional scan/normal mode switching device, one scan/normal mode switching device shown in Fig. @1 is assembled into the logic circuit testing device shown in Fig. 2. An embodiment of the present invention will be described as an embodiment of the present invention.However, although the center terminal c9 in Figure 1 is not shown in Figure 2, it is connected to each scan/normal mode switching device it fLI. All the signal lines to the reset terminal (to) are connected, and the external reset signal is simultaneously transmitted to the scan/normal mode switching device (
1).

If all FFs do not return to the 21% recent state, input 'Hl to the reset terminal (to). Since 'H' is input to the AND circuits ■ and @, the AND circuit Qs outputs the input signal from the input terminal @ to υ) as it is in the scan mode,
The AND circuit (to) outputs the input signal of the input terminal - in the normal mode as it is. Therefore, the operation when IF5 is input to the reset terminal (support) is as follows.

The operation 1 of the scan/normal mode switching device shown in FIG. 3 shown in the conventional example is completely equivalent, and the operation of the logic circuit testing device according to the present invention is completely equivalent to that of the conventional one.

Next, all FF f21i reset state (when scraping, input 'L' as a reset signal indicating the reset terminal - (reset state). In this case, AND circuit field, input terminal (6 in scan mode) -MaA/ (The input terminal at the time of need (ILI is output regardless of the input terminal. Therefore, the mode switching signal input terminal does not require manual input from the output terminal α through the AND circuit 123 and OR circuit 0. fLI. That is, the scan/normal mode switching device (1) always outputs ILI.

As a result, 'L' is applied to the data input terminal of each F F t21.
' is applied. However, this data ILl is not captured until a clock signal is input. If you input the reset signal and set the shift mode, all shift paths (3a
, 3b, 3c, 3d) all F'F'! 2
1i clock signal is transmitted. All F F (21
Since ILI is applied to , all Flzzl ('L
I is taken in and the state is reset.

Although the FF is cited here as an example of the state memory circuit, it goes without saying that other state memory circuits C can also be implemented.

In this case, when the reset signal is input manually, the scan/normal mode switching device (1) is uniformly outputted (as described above, but even when outputting 'H18, the circuit configuration is changed). However, in the case of outputting 'L', the reset state f can be cleared more efficiently, so it is intentionally omitted in the case of outputting @#H#.

In the above embodiments, all the scan/normal mode switching devices were those of the present invention. However, there is also a method in which the present invention is used only for the scan/normal mode switching device located at the forefront of each shift lot, and the other devices are used as conventional devices. In this case, in order to reset all FFs, a clock signal is required for the number of cycles of the FFs in the shift path.

[Effects of the Invention] As described above, according to the present invention, a uniform signal is applied to the input terminals of all state storage circuits in a plurality of shift paths in response to input of a reset state from the outside. , all the state storage circuits can be put into a reset state with a clock signal of only one cycle, which has the effect of making the testing time of logic circuits more efficient.

[Brief explanation of the drawing]

FIG. WE1 is a circuit diagram showing the internal structure of a scan/normal mode switching device according to an embodiment of the present invention. ! Figure @2 is a circuit diagram showing a logic circuit testing device capable of scan-in/scan-out, and the third factor is a circuit diagram showing the internal structure of a conventional scan/normal mode switching device. In the figure, 129. (E) is an AND circuit, (support)
indicates the reset terminal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

[Claims] (1) A logic circuit testing device in which state memory circuits with a shift function are connected in a chain to form a shift path that allows scan-in and scan-out. (2) causing the state storage circuit to operate as a shift path;
Setting and reading data (referred to as scan mode)
or a scan/normal mode switching device for specifying whether to cause the state storage circuit to perform normal operation (normal mode), and an external terminal for controlling the scan/normal mode switching device. A logic circuit testing device according to claim 1. (3) The scan/normal mode switching devices are equipped with a reset terminal, so that when a signal indicating a reset state (referred to as a reset signal) is input, all the scan/normal mode switching devices output a uniform signal. A logic circuit testing device according to claim 1, characterized in that it is configured as follows.