JPS62274729A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS62274729A JPS62274729A JP11845786A JP11845786A JPS62274729A JP S62274729 A JPS62274729 A JP S62274729A JP 11845786 A JP11845786 A JP 11845786A JP 11845786 A JP11845786 A JP 11845786A JP S62274729 A JPS62274729 A JP S62274729A
- Authority
- JP
- Japan
- Prior art keywords
- film
- etching
- silicon nitride
- photoresist
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 22
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 20
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910052681 coesite Inorganic materials 0.000 abstract 6
- 229910052906 cristobalite Inorganic materials 0.000 abstract 6
- 229910052682 stishovite Inorganic materials 0.000 abstract 6
- 229910052905 tridymite Inorganic materials 0.000 abstract 6
- 239000002184 metal Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 3、発明の詳細な説明 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に関する。[Detailed description of the invention] 3. Detailed description of the invention [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
従来の半導体装置の製造方法をMOS)ランジスタを例
として示すと以下のとおりであった。すなわち、2−(
A)図のようなソース、ドレイン202およびゲート2
04より成るMOS)ランジスタを形成した半導体基板
201上に2−(B)図のように絶縁膜として二酸化ケ
イ素膜(以下Si0g膜と略記)205を形成した後、
2−(C)図のようにフォトレジスト207により開孔
パターンを形成する。次に2−(D)図のように前記フ
ォトレジスト207をマスクとし、前記5i02膜をエ
ツチングした後に、2−(E)図のようにフォトレジス
ト207を除去することにより、MOS)ランジスタの
ソース、ドレイン202部分に導通をとるためのコンタ
クト孔を形成していた。A conventional method for manufacturing a semiconductor device using a MOS transistor as an example is as follows. That is, 2-(
A) Source, drain 202 and gate 2 as shown
After forming a silicon dioxide film (hereinafter abbreviated as Si0g film) 205 as an insulating film on the semiconductor substrate 201 on which a MOS transistor consisting of 04 was formed, as shown in Figure 2-(B),
2-(C) An opening pattern is formed using photoresist 207 as shown in FIG. Next, as shown in Fig. 2-(D), the 5i02 film is etched using the photoresist 207 as a mask, and then the photoresist 207 is removed as shown in Fig. 2-(E). , a contact hole was formed in the drain 202 portion for establishing electrical conduction.
しかし、従来の技術において、2−(D)図に示すとお
り、前記SiO,膜205のエソチングをドライエツチ
ングによって行なった場合、エツチングは深さ方向にの
み進行し、横方向にはほとんど進まないため、コンタク
ト孔の形状は2−(E)図に示す如く垂直となってしま
い、コンタクト孔を介してソースあるいはドレイン10
2と他の素子との接続を金属配線により行なおうとする
場合に、コンタクト孔部分で金属配線が断線してしまう
ことがあった。However, in the conventional technology, as shown in Figure 2-(D), when the SiO film 205 is etched by dry etching, the etching progresses only in the depth direction and hardly in the lateral direction. The shape of the contact hole is vertical as shown in Figure 2-(E), and the source or drain 10 is connected through the contact hole.
2 and other elements using metal wiring, the metal wiring sometimes breaks at the contact hole portion.
本発明は、このような従来の半導体装置の製造方法にお
ける問題点を解決するもので、その目的とするところは
、容易に理想的な傾斜形状を存するコンタクト孔を形成
することにより金属配線の断線を防止し、より安定した
信虻性の高い半導体装置の製造方法を提供することにあ
る。The present invention solves these problems in the conventional semiconductor device manufacturing method, and its purpose is to easily form a contact hole having an ideal inclined shape to prevent disconnection of metal wiring. An object of the present invention is to provide a method for manufacturing a semiconductor device that is more stable and reliable.
本発明の半導体装置の製造方法は、トランジスタ、ダイ
オード、抵抗などの素子を形成した半導体基板上に、第
一の絶縁膜として二酸化ケイ素膜を形成する工程、前記
二酸化ケイ素膜上に、第二の絶縁膜として窒化ケイ素膜
を形成する工程、前記窒化ケイ素膜上にフォトレジスト
による開孔パターンを形成する工程、前記フォトレジス
トをマスクとして、前記窒化ケイ素膜を等方的にエツチ
ングする工程、および、引き続き前記フォトレジストを
マスクとして、二酸化ケイ素膜を異方的にエツチングす
る工程を有することを特徴とする。The method for manufacturing a semiconductor device of the present invention includes the step of forming a silicon dioxide film as a first insulating film on a semiconductor substrate on which elements such as transistors, diodes, and resistors are formed, and forming a second silicon dioxide film on the silicon dioxide film. a step of forming a silicon nitride film as an insulating film, a step of forming an opening pattern using a photoresist on the silicon nitride film, a step of isotropically etching the silicon nitride film using the photoresist as a mask, and The method is characterized in that it subsequently includes a step of anisotropically etching the silicon dioxide film using the photoresist as a mask.
本発明の上記構成によれば、絶縁膜2層構造、すなわち
、第一の絶縁膜として二酸化ケイ素膜、第二の絶縁膜と
して窒化ケイ素膜を形成することにより、窒化ケイ素膜
は容易に等方性のエツチングができるため、傾斜を有す
るコンタクトホールが容易に形成でき、コンタクトホー
ル部分での金属配線の断線を大幅に減少することができ
る。According to the above structure of the present invention, by forming the two-layer structure of the insulating film, that is, the silicon dioxide film as the first insulating film and the silicon nitride film as the second insulating film, the silicon nitride film can be easily formed isotropically. Since the etching can be carried out in a uniform manner, a contact hole having an inclination can be easily formed, and disconnection of the metal wiring at the contact hole portion can be greatly reduced.
1−(A)図〜1−(G)図は、本発明の実施例におけ
る半導体装置の製造工程に従う断面図であってMO3I
−ランジスタ上の絶縁膜およびコンタクトホール形成を
例として示した。1-(A) to 1-(G) are cross-sectional views according to the manufacturing process of a semiconductor device in an embodiment of the present invention, and are MO3I
- Formation of an insulating film and contact hole on a transistor was shown as an example.
本発明の実施例では、最初1−(A)図のように半導体
基板101上にMOS)ランジスタが形成されており、
102はソース、ドレイン、103はゲート膜化膜、1
04はゲート電極である。In the embodiment of the present invention, a MOS transistor is first formed on a semiconductor substrate 101 as shown in FIG. 1-(A).
102 is a source, a drain, 103 is a gate film, 1
04 is a gate electrode.
以下、絶縁膜および、コンタクトホールの形成の方法に
ついて詳細に述べていく。The method for forming the insulating film and the contact hole will be described in detail below.
1−(B)図のように、MOSトランジスタがすでに形
成されている半導体基板10上に、第一の絶縁膜として
S + Oz膜105を形成した後、1−(C)図に示
す如く、前記5iOz膜105の上に第2の絶縁膜とし
て直接窒化ケイ素膜(以下s i3 N4 W!Jと略
記)を形成し、2層構造の絶縁膜を完成させる。As shown in Figure 1-(B), after forming the S + Oz film 105 as a first insulating film on the semiconductor substrate 10 on which a MOS transistor has already been formed, as shown in Figure 1-(C), A silicon nitride film (hereinafter abbreviated as s i3 N4 W!J) is directly formed as a second insulating film on the 5iOz film 105 to complete a two-layer insulating film.
次に、1−(D)図に示すように、フォトレジスト10
7によりパターン形成を行なう。Next, as shown in Figure 1-(D), a photoresist 10
Pattern formation is performed in step 7.
次に、1−(E)図に示すように、フォトレジスト10
7をマスクとして、Si N 膜+06のエツチン
グを行なう。このエツチングの際に、ドライエツチング
法によりエツチングを行なうと、エツチング条件により
、完全異方性のエツチング、すなわち、コンタクトホー
ルの形状が垂直となるようにすることも可能であるが、
この場合、傾斜を有する形状を得るために、等方性エツ
チングを行ない、SiN膜が除去され、SiO□膜10
5が露出したときにエツチングを中断する。ここで今度
は、5102膜をエツチングする条件に変更し、引き続
き5ift膜105をエツチングすると1−(F)図に
示すようになる。このとき、SiO□膜のエツチングは
完全異方性で行なわれるため、Sin、膜105部分で
の形状はほぼ垂直となる。最後に、フォトレジスト10
7を除去することにより、1−(G)図の断面構造を得
る。Next, as shown in Figure 1-(E), a photoresist 10
Using 7 as a mask, the Si N film +06 is etched. If this etching is performed using a dry etching method, it is possible to achieve completely anisotropic etching, that is, the shape of the contact hole is vertical, depending on the etching conditions.
In this case, in order to obtain a sloped shape, isotropic etching is performed to remove the SiN film and remove the SiO□ film 10.
Etching is interrupted when 5 is exposed. Now, if the conditions are changed to etching the 5102 film and then the 5ift film 105 is etched, the result will be as shown in Figure 1-(F). At this time, since the SiO□ film is etched completely anisotropically, the shape of the Si film 105 is almost vertical. Finally, photoresist 10
By removing 7, the cross-sectional structure shown in FIG. 1-(G) is obtained.
〔発明の効果〕
以上述べたように、本発明によれば二酸化ケイ素膜と窒
化ケイ素膜の2層より成る絶縁膜を形成し、しかも上層
部に等方性エツチングの容易な窒化ケイ素膜を用い、こ
れを等方性エツチングした後、下層の二酸化ケイ素膜と
寸法制御性の良い異方性のエツチングによりエツチング
することにより、寸法制御性がよくしかも理想的な断面
形状を有するコンタクトホールが得られ、このことによ
りさらに上層に金属配線を行なおうとする場合の金属配
線が断線する確率を極端に減少させることができる。[Effects of the Invention] As described above, according to the present invention, an insulating film consisting of two layers, a silicon dioxide film and a silicon nitride film, is formed, and a silicon nitride film that can be easily isotropically etched is used as the upper layer. By isotropically etching this and then etching it with the underlying silicon dioxide film using anisotropic etching with good dimensional control, a contact hole with good dimensional control and an ideal cross-sectional shape can be obtained. This makes it possible to extremely reduce the probability of metal wiring breaking when attempting to provide metal wiring in an upper layer.
さらにまた、従来の二酸化ケイ素膜1層の絶縁膜を使っ
た場合と比べて、窒化ケイ素膜を併用しているために、
素子に悪影響をおよぼす、不純物イオンの阻止能力が向
上するため、半導体装置の信館性も大きく向上している
。Furthermore, compared to the conventional insulating film of a single layer of silicon dioxide film, since a silicon nitride film is also used,
Since the ability to block impurity ions that adversely affect devices is improved, the reliability of semiconductor devices is also greatly improved.
第1図(A)〜(G)は、本発明の実施例による半導体
装置の製造工程断面図である。
第2図(A)〜(E)は、従来の半導体装πの製造工程
断面図である。
101.201・・・・・・半導体基板102.202
・・・・・・ソース、ドレイン103.203・・・・
・・ゲート膜
104.204・・・・・・ゲート電極105.205
・・・・・・二酸化ケイ素膜106・・・・・・・・・
・・・・・・・・・窒化ケイ素膜107.207・・・
・・・フォトレジスト以 上
出願人 セイコーエプソン株式会社
代理人 弁理士 最 上 務゛N他1名、・′・″FIGS. 1A to 1G are cross-sectional views of the manufacturing process of a semiconductor device according to an embodiment of the present invention. FIGS. 2(A) to 2(E) are cross-sectional views showing the manufacturing process of a conventional semiconductor device π. 101.201...Semiconductor substrate 102.202
...Source, drain 103.203...
...Gate film 104.204...Gate electrode 105.205
...Silicon dioxide film 106...
......Silicon nitride film 107.207...
・・・Photoresist and above Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Mogami Tsutomu N and 1 other person,・′・″
Claims (1)
半導体基板上に、第一の絶縁膜として二酸化ケイ素膜を
形成する工程、前記二酸化ケイ素膜上に、第二の絶縁膜
として窒化ケイ素膜を形成する工程、前記窒化ケイ素膜
上にフォトレジストによる開孔パターンを形成する工程
、前記フォトレジストをマスクとして、前記窒化ケイ素
膜を等方的にエッチングする工程、および引き続き前記
フォトレジストをマスクとして、二酸化ケイ素膜を異方
的にエッチングする工程を有することを特徴とする半導
体装置の製造方法。A step of forming a silicon dioxide film as a first insulating film on a semiconductor substrate on which elements such as transistors, diodes, and resistors are formed, and a step of forming a silicon nitride film as a second insulating film on the silicon dioxide film. , forming an opening pattern with a photoresist on the silicon nitride film, isotropically etching the silicon nitride film using the photoresist as a mask, and subsequently etching a silicon dioxide film using the photoresist as a mask. 1. A method for manufacturing a semiconductor device, comprising the step of etching anisotropically.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11845786A JPS62274729A (en) | 1986-05-23 | 1986-05-23 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11845786A JPS62274729A (en) | 1986-05-23 | 1986-05-23 | Manufacturing method of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62274729A true JPS62274729A (en) | 1987-11-28 |
Family
ID=14737121
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11845786A Pending JPS62274729A (en) | 1986-05-23 | 1986-05-23 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62274729A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7517738B2 (en) | 1995-01-17 | 2009-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor |
US7615786B2 (en) | 1993-10-01 | 2009-11-10 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor incorporating an integrated capacitor and pixel region |
US8835271B2 (en) | 2002-04-09 | 2014-09-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
US8946718B2 (en) | 2002-04-09 | 2015-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
US9366930B2 (en) | 2002-05-17 | 2016-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Display device with capacitor elements |
-
1986
- 1986-05-23 JP JP11845786A patent/JPS62274729A/en active Pending
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7615786B2 (en) | 1993-10-01 | 2009-11-10 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor incorporating an integrated capacitor and pixel region |
US7517738B2 (en) | 1995-01-17 | 2009-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor |
US9666614B2 (en) | 2002-04-09 | 2017-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
US10700106B2 (en) | 2002-04-09 | 2020-06-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
US8946717B2 (en) | 2002-04-09 | 2015-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
US9105727B2 (en) | 2002-04-09 | 2015-08-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
US8946718B2 (en) | 2002-04-09 | 2015-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
US9406806B2 (en) | 2002-04-09 | 2016-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
US8835271B2 (en) | 2002-04-09 | 2014-09-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
US10050065B2 (en) | 2002-04-09 | 2018-08-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
US10083995B2 (en) | 2002-04-09 | 2018-09-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
US11101299B2 (en) | 2002-04-09 | 2021-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
US10854642B2 (en) | 2002-04-09 | 2020-12-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
US9366930B2 (en) | 2002-05-17 | 2016-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Display device with capacitor elements |
US10527903B2 (en) | 2002-05-17 | 2020-01-07 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
US10133139B2 (en) | 2002-05-17 | 2018-11-20 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
US11422423B2 (en) | 2002-05-17 | 2022-08-23 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH10135331A (en) | Method for forming contact hole in semiconductor device | |
JPS62274729A (en) | Manufacturing method of semiconductor device | |
JPS63269535A (en) | Method for flattening the surface of semiconductor devices | |
JP2672596B2 (en) | Method for manufacturing semiconductor device | |
JPH1012868A (en) | Semiconductor and its manufacture | |
JP2950857B2 (en) | Method for manufacturing semiconductor device | |
JPH02133924A (en) | Semiconductor device and its manufacturing method | |
JPH01253254A (en) | Manufacture of semiconductor device | |
JPH05267336A (en) | Forming method for wiring layer using alignment mark | |
JPH01235352A (en) | Manufacture of semiconductor device | |
JPH0287621A (en) | Manufacture of semiconductor device | |
JP3227722B2 (en) | Method for manufacturing semiconductor device | |
JPH01230252A (en) | Contact-hole forming method | |
JPH02112233A (en) | Formation of multilayer interconnection | |
JPH03191521A (en) | Manufacture of semiconductor device | |
JPH0713999B2 (en) | Method for manufacturing semiconductor device | |
JPH01302751A (en) | Semiconductor device | |
JPH02105519A (en) | Manufacture of semiconductor integrated circuit | |
JPH03276725A (en) | Manufacture of semiconductor device | |
JPH04348516A (en) | Method of forming contact hole | |
JPH03148121A (en) | Etching | |
JPH03205825A (en) | Manufacturing method of semiconductor device | |
JPS6360531A (en) | Manufacture of semiconductor device | |
JPH11214326A (en) | Manufacturing for semiconductor device | |
JPH06177069A (en) | Manufacture of semiconductor device |