JPS62272619A - delay circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Detailed description of the invention Fields of use of Ichime-produced soil〕 The present invention relates to a video tape recorder (VTR).

The present invention relates to a variable delay circuit suitable for correcting time axis fluctuations occurring in a reproduced signal in a video disc player or the like.

[Conventional technology]

The playback signal played back from a video disc player is affected by the eccentricity of the disc, and the playback signal played back from a VTR is affected by uneven rotation of the rotating magnetic head, causing expansion and contraction in the time axis, resulting in a correct image. In order to reproduce it, it is necessary to correct the time axis fluctuation. Conventionally, circuit configurations for correcting the time axis using a charge-coupled device (hereinafter referred to as COD) have been disclosed in Japanese Patent Publication No. 56-60216, Japanese Patent Publication No. 56-207422, and the like.

[Problem that the invention seeks to solve]

The conventional technology disclosed in Public Utility Model Publication No. 1983-60216 controls the delay time of the video signal by changing the clock frequency of the CCD. However, when the clock frequency of the CCD is changed, the normal output There are problems such as DC voltage fluctuations and AC amplitude fluctuations occurring in the video signal, and brightness flicker on the screen being detected. There is a method of correcting the time axis in the P/M signal band (modulated by a video signal without using COD) that uses a delay circuit composed of a plurality of inverters. As shown in Publication No. 57-207422, the delay time is controlled by changing the power supply voltage of the CMOS inverter.

However, since this circuit drives a large number of inverters at the same time, a large current flows from the power supply, making it difficult to control the number of inverters. Furthermore, it is necessary to use a buffer circuit that can flow a large current, and it is necessary to construct external elements with large driving capabilities using individual components. Furthermore, there is a possibility that interference with other elements may occur due to the large control current.

An object of the present invention is to provide a delay circuit that has a light load on a control power source that controls delay time and is easy to control.

[Means for solving problems]

In the present invention, the power supply voltage of the CMOS inverter is set to a constant voltage, and the delay time is controlled by changing the potential of the well of the MOS transistor constituting the inverter, the semiconductor substrate, or both.

[Effect]

C) The delay time of the VIOS inverter is proportional to the time constant τ determined by the product of the on-resistance ROM of the MOS transistor, the capacitance C parasitic to the gate of the MOS transistor, and the phase capacitance C of the parasitic capacitance of the output diffusion layer. ON resistance ROM
can be expressed by equation (1).

Ros=17 (Bo(Vcs-Vth))
-(1)VGS:MOS) transistor gate to source voltage,
vth: Threshhold! , pressure, W: gate width.

L: Gate length, Bo: Constant determined by process, (1
) As is clear from the equation, the on-resistance Rob of the VI OS transistor changes depending on the change in voltage Vcs or vth. The voltage vth changes in proportion to the square root of the change in the potential of the well or substrate of the MOS transistor, ie, the back gate. The current flowing through the bank gate is considerably smaller than the current of the power supply of the CMOS inverter. Therefore, delay time control that changes the delay time by changing the back gate potential does not require a buffer circuit with a large drive capacity to flow a large current, compared to control that is performed by changing the power supply voltage. Delay time can be easily controlled.

[Embodiments of the invention]

:A) One embodiment of the present invention is shown and explained in FIG. 11 is a delay line configured by connecting a plurality of inverters in series;
12 is an FM demodulator, 15 is a synchronization separation circuit, 14 is a phase comparator 715, which is a control terminal for the delay time of the delay line 11, and 16 is a reproduction signal of a video disc player, etc.

An input terminal 17 is an output terminal for receiving an FM modulated video signal including fluctuations in the time axis. After the FM modulated video signal input from the terminal 16 is delayed by the delay line 11, its horizontal synchronization (iW signal) is detected by the sync separation circuit 16, and the phase is compared with the reference signal by the phase comparator 14. A signal corresponding to the detected deviation of the time axis is applied to the control terminal 15.The time axis correction operation is well known to those skilled in the art and will therefore be omitted.Next, the delay line 11
The detailed circuit will be explained below. 21 is a P-type MOS transistor, 22 is an N-type MOS transistor, and 23 is a power supply. MOS transistors 21 and 22 constitute a CMOS inverter. The delay line 11 is constructed by connecting the input and output of a plurality of CMOS inverters in series.

Control terminal 15 is connected to the backgate of PWMOS transistor 21. When the output voltage of the phase comparator 14 connected to the other end of the terminal 15 changes, the P-type MO
The back gate potential of the S transistor 21 changes, which appears as a change in the threshold voltage (vth), and the MO
The on-resistance ROM of the S transistor 21 changes. As a result, the delay time is controlled. FIG. 2 shows another embodiment.

Components with the same symbols as in FIG. 1 have the same functions. The operation of the entire block diagram is similar to that in FIG. Control terminal 15 is N
connected to the back gate of the type MOS transistor 22,
Similarly to FIG. 1, the delay time is controlled by changing the voltage vth of the N-type h/j OS ) transistor 22. In FIGS. 1 and 2, the delay time is controlled by the back gate of one of the two MOS transistors constituting the CMOS inverter, but it is also possible to control both at the same time.

The CMOS inverter 1 shown in Figure 81!1 is shown in Figure WJ3.
An example of a vertical structure cross-sectional view of a semiconductor chip in stages is shown.

61 is a P-type semiconductor substrate, 32 is an N-type well, 33.3
4 is the diffusion layer of the P-type MOS transistor, 35.3 (S
37 is a diffusion layer of an N-type MOS transistor, and a gate electrode.

38 is an input terminal of the inverter, and 59 is an output terminal.

Components with the same reference numerals as in FIG.
The delay time is controlled by changing the voltage vth of the OS transistor. FIG. 4 schematically shows the delay characteristics of the CMOS inverter configured as shown in FIG. The horizontal axis is the control voltage Vc, and the vertical axis is the delay time τ. In FIG. 6, since the well 52 and the diffusion layer 35 form a PN junction, the delay time is controlled by changing the control voltage of the terminal 15 within a voltage range higher than that of the inverter power supply 23. The value of the current flowing from the phase comparator 14 connected to the control terminal 15 to the control terminal 15 is extremely small compared to the current value of the power supply 26 . FIG. 5 shows an example of a longitudinal cross-sectional view of a semiconductor substrate of a CMOS inverter configured to perform delay control by applying a control power source to the back gate of the N-type MOS transistor shown in FIG. Components with the same symbols as in FIGS. 2 and 6 have the same functions.

The potential of the well 32 is fixed to the power supply potential, and control is performed by changing the potential applied to the terminal 15 connected to the substrate 31. In this configuration, P is generated between the diffusion layer 36 and the substrate 31.
Since it is an N junction, the potential of the control terminal 15 is the same as that of the diffusion layer 3.
The voltage is changed in a range lower than the potential of 6.

Even in this circuit configuration, no current flows through the substrate 31 during normal circuit operation, and the current flowing from the control terminal 15 has an extremely small value.

Although the above example is constructed using a P-type semiconductor substrate, it can also be constructed using an N-type semiconductor substrate. An example is shown in FIG. 6 and will be explained. 61 is an N-type semiconductor substrate.

62 is a P-type well, 63.64 is a diffusion layer of a P-type MOS transistor, 65.66 is a diffusion layer of an N-type MOS transistor, 67 is a gate electrode, and 68 is a power source that determines the potential of the substrate 61, which is used for normal logic. It is the same as the voltage of the circuit power supply. Components with the same symbols as in FIG. 5 have the same functions. The delay time is controlled by changing the voltage at terminal 15 and changing the voltage vth of the N-type MOS transistor. Since the voltage applied to the control terminal 15 at this time is applied to the PN junction between the well 62 and the diffusion layer 66, control is performed in a range lower than the potential of the diffusion layer 66. In FIGS. 5 and 6, since the N-type diffusion layers 66 and 66 are at ground potential,
The control voltage has a negative level, but if the first potential of the power supply 23, 6a and the N-type diffusion layer 56, 66 is set to a high potential, the control potential can be changed to a positive potential, and other circuits Connection with blocks (not shown) can be easily made.

FIG. 7 shows a configuration diagram in which the delay time is controlled by changing the substrate 61. Components with the same reference numerals in FIG. 3 have the same functions. This configuration is similar to that explained in Fig. 3.
The delay time is controlled by changing the voltage vth of the o s i transistor. The control voltage applied to the control terminal 15 at this time is applied to the diffusion layer 65 due to the PN junction between the diffusion layer 63 and the substrate 61.
Control takes place at a higher range. In these examples as well, the control becomes easy.

Figure 8 (Here, the inverter is a deregression type MOS)
An example of a configuration using transistors will be shown and explained. The configuration is similar to that of FIG. 1, using a P-type semiconductor substrate and controlling the delay time by changing the voltage vtb of the PmMOS transistor. Components with the same symbols as in FIG. 4 have the same functions. P type M, P in the channel part of the OS transistor
An N-type buried channel 81 is provided in the channel portion of the N-type MOS transistor, and each MOS transistor is made into a deregression type. In Figures 3 and 7, we explained that the delay control voltage varies in a range higher than the inverter power supply voltage, but in order to widen the variable range, it is necessary to make the inverter power supply voltage as low as possible. . The lower limit of the power supply voltage at which the inverter operates is determined by the voltage vth of the M i-, ) S ) transistors. Therefore, if the MOS transistor is made into a deregression type transistor so that the MOS transistor turns on and operates as an inverter even when the input voltage is extremely small, the inverter's power supply voltage will be the same as when it is at the normal voltage vth. It is possible to set the value to be much smaller than the lower limit. This makes it possible to widen the control range of the delay time. In addition to this, power consumption can also be reduced. The power consumption P of the inverter is expressed by equation (2).

■ fCv2+f-□ga+v・more c (2) f
: Operating frequency, C: Parasitic capacitance, ■=Power supply voltage.

RON: MOS) transistor on-resistance, I
nc: DC current The first term in equation (2) is the power consumed to drive the parasitic capacitance, the second term is the through current that flows during the transition when the inverter reverses, and the third term is the threshold of the MOS transistor This is power due to leakage current that flows depending on the voltage. In equation (2), the first term is proportional to the square of the power supply voltage. For example, if a power supply voltage of 3.5V is used at normal vth, if vth can be lowered and the power supply voltage of the inverter can be reduced to 1V, the first term in equation (2) will be reduced to about one-tenth. Furthermore, in the second term, the power decreases in proportion to the power supply voltage. M.O.S.
Even if we take into account the opposite effect of increasing the third term in equation (2) because current always flows through the inverter and consumes power by using a deregression type transistor, power consumption can be reduced to a fraction of what it used to be. . Debresion type MO8): By using a t resistor, power consumption can be reduced and the control range can be expanded, not only in this example, but also when changing the substrate voltage with a P-type substrate, Needless to say, this also appears in the case.

Also at this time, the current flowing from the control power supply is extremely small and control is easy.

〔Effect of the invention〕

According to the present invention, since the delay time of the inverter can be controlled by the potential of the back gate, the configuration of the delay time control circuit becomes easy.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a delay circuit according to one embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment of the present invention, and FIG. 3 is a circuit diagram of a delay circuit according to an embodiment of the present invention. Figures 5, 6, 7, and 8 are commercials in the present invention.
FIG. 4, which is a sectional view of the semiconductor substrate of the OS inverter, is a delay characteristic diagram of the inverter. 11...Delay line 12...FM demodulator 13...
Synchronous separation circuit 14... Phase comparator 15... Control terminal 31... P type semiconductor substrate 52... N type well 61... N type semiconductor substrate 62... P type well ゝ・Agent Patent Attorney Ogawa
Katsuo゛～□ ・7th residence 3 ki ■Kyou V. 15th note Mu ■ l 7 flash λ b 8 note

Claims (1)

[Claims] 1. A first conductivity type semiconductor substrate, a first second conductivity type semiconductor layer provided at a certain interval on the surface thereof, and a second conductivity type semiconductor layer provided on the surface thereof at a certain interval.
A conductive type semiconductor layer, a first gate electrode provided on a first conductive type semiconductor substrate between the first and second second conductive type semiconductor layers with an insulating film interposed therebetween, and a first conductive type semiconductor substrate. a third second conductivity type semiconductor layer provided on the surface; and a first semiconductor layer provided at a certain interval on the surface of the third second conductivity type semiconductor layer.
a first conductivity type semiconductor layer and a second first conductivity type semiconductor layer;
a first conductivity type semiconductor substrate, having a second gate electrode provided on a third second conductivity type semiconductor layer between the first and second first conductivity type semiconductor layers via an insulating film; A second semiconductor layer composed of first and second second conductivity type semiconductor layers and a first gate electrode.
CMO with a first conductivity type MOS transistor composed of a conductivity type MOS transistor, a third second conductivity type semiconductor layer, first and second first conductivity type semiconductor layers, and a second gate electrode.
An S inverter is configured, which has a plurality of the above CMOS inverters, a delay line configured by connecting a plurality of inputs and outputs in series, and a time to detect fluctuations in the time axis connected to the output of the delay line. It comprises at least an axis error detection circuit, and the output signal of the time axis error detection circuit is applied to the first conductivity type semiconductor substrate, the third second conductivity type semiconductor layer, or both, which constitute the CMOS inverter. delay circuit.