JPS62271525A - Code compression conversion system - Google Patents

Abstract

PURPOSE:To improve the digital signal processing capability by providing a register storing a sign code and a register storing a sign after addition correction between a digital signal processing processor and a code compression converting circuit. CONSTITUTION:A digital signal processing processor 1a outputs a sign in a linear code to a register 8 as it is. Then the processor 1a applies absolute processing to the linear code, adds a prescribed value and the result is outputted to a register 9. The sign code and the code subjected to addition and correction set to the registers 8, 9 are converted into a nonlinear PCM code by the code compression conversion circuit 4 and outputted with further inversion. Through the system above, since the number of program step number in the processor 1a is effectively reduce with a constitution minimizing the increase in the hardware, the digital signal processing capability is improved.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a method for converting a linear code into a non-linear PCM code.

(Prior art) Conventionally, as a technology in this field, "Application of digital signal processing" (Published by Institute of Electronics and Communication Engineers, pp. 140-14)
There are some listed in 3). This will be explained below.

Conventionally, the codes used when converting linear codes to non-linear codes are the 8-bit μ-law (μ=225) or the 8-bit μ-law (μ=225)
Bitto’s law (A=87.6) fold-line non-linear PCM
There is a sign. To convert linear codes to these non-linear PCM codes, in the case of μ-law non-linear PCM codes, the code value obtained by adding "-)-33j or [+32 J" to the linear code is also added to the A-law non-linear PCM code. In the case of PCM codes, conversion processing is performed by hardware or software by utilizing the fact that the original code values have a correspondence relationship as shown in FIGS. 2 and 3, respectively.

Generally, the processing procedure for converting into a μ-law nonlinear PCM code is as follows.

1) Find the absolute value of the linear code.

2) Add “+33J or l+32J to the absolute value.

3) Conversion into an 8-bit non-direct IMPCM code based on the correspondence shown in FIG. 2 using the 13-bit addition-corrected code and 1-bit sign code (P) representing the polarity of the input.

4) Invert the converted non-linear PGM code.

IM for converting the above-mentioned linear code into a non-linear PCM code
! (hereinafter referred to as code compression conversion processing) is often used after digital signal processing using a digital signal processing processor, and it is also possible to perform all of these processings on the digital signal processing processor using software. It is possible.

However, in a digital signal processor, there is a limit to the time (or time percentage) that can be used to perform the code compression conversion process, and if the code compression conversion process is implemented entirely by software, this limit will be exceeded. In such a case, 1 in the process of 3) and 4) above.
The part that converts and inverts the sign code of bits and the 13-bit code after addition correction to an 8-bit non-linear PCM code is realized by hardware, and other absolute value processing,
Numerical addition processing was implemented using software.

FIG. 4 shows an example of a device using a digital signal processing processor. In the figure, 1 is a digital signal processing processor, 2 is a decoder (DEC), 3 is a register, and 4 is a code compression conversion circuit. . Further, FIG. 5 is a flowchart regarding code compression conversion processing in the digital signal processing processor 1.

In the device, linear codes a1, a2, . . .
... a14 is a non-linear PGM code AI, A2, --...
- When converting to A8, first, the processor 1 temporarily stores the sign code a1 in the linear code to be converted, and converts the linear codes a1 to a14 into absolute values, that is, if the sign code a1 is positive, Leave it as is, and if it is negative, “−
Multiply by 1” and then r+33J (or 1”+32J)
are added, and the signs a2-, a3-, ...... a14
', and add the memorized sign code ^1 to it,
The sign code a1 is passed through the signal line 5, and the 13-bit code a2- to 814' which has been added and corrected is sent to the signal line group 6.
It is output to register 3 via. Also, at this time, a set signal (pulse) is output from the decoder 2 to the cp terminal of the register 3 via the signal line 7, and the signs @82' to 814' that have been added and corrected to the sign code a1 are sent to the register 3. Set.

The sign code a1 set in the register 3 and the addition-corrected codes a2' to 814' are converted into an 8-bit nonlinear PCM code AI by the code compression conversion circuit 4.

A2. . . . is converted to A8, further inverted and output. Note that the code compression conversion circuit 4 includes:
For example, as described in the above-mentioned document, it is constituted by a plurality of bonded memories and the like.

(Problems to be Solved by the Invention) However, according to the above configuration, the sine code a1 in the linear code is once memorized and stored, and the codes a2' to a14-, which are converted into absolute values and subjected to numerical addition processing, are The simple procedure of adding the memorized sign code a1 to the digital signal processor is performed by a digital signal processor. There was a problem that the usage efficiency of the signal processing processor was poor.

The present invention eliminates the above problems, reduces the number of program steps for code compression conversion processing in a digital signal processing processor without significantly increasing the amount of hardware, and improves the utilization efficiency of the digital signal processing processor. The purpose is to provide a conversion method.

(Means for Solving the Problems) In order to solve the above problems, the present invention uses a digital signal processor to convert a linear code including a sign code indicating the polarity of the input into an absolute value, and then adds a certain numerical value. death,
In a code compression conversion method in which the sine code and the code after addition correction are input to a code compression conversion circuit and converted into a non-linear PCM code, the sine code is input between the digital signal processing processor and the code compression conversion circuit. a first register that stores the code, and a second register that stores the code after the addition correction.
The digital signal processing processor first outputs and sets a sign code to the first register, and then performs the absolute value conversion and numerical addition processing,
The code after addition correction is output to the second register and set.

(Function) According to the present invention, the sine code in the linear code is directly outputted to the first register by the digital signal processing processor and set therein, while the linear code is converted into an absolute value by the digital signal processing processor. Then, a certain numerical value is added, outputted to and set in the second register, and the first and second registers output the sine code and the addition-corrected code to the code compression conversion circuit, and the non-linear PCM converted to code.

(Embodiment) FIG. 1 shows an embodiment of the present invention, and in the figure, the same components as those of the conventional example are denoted by the same reference numerals.

That is, 1a is a digital signal processing processor, 2a is a decoder (DEC), 4 is a code compression conversion circuit, 8 and 9.
are the first and second registers.

The digital signal processor 1a is connected to a register 8 via a signal line 5, and is also connected to a register 9 via a signal line group 6. It is designed to output a code.

Further, the decoder 2a is connected via signal lines 7a and 7b,
They are connected to the cp terminals of registers 8 and 9, respectively, and output a set signal for setting the sign code in register 8 and a set signal for setting the addition-corrected code in register 9. Further, the outputs of the registers 8 and 9 are all connected to the input of the code compression conversion circuit 4.

Note that FIG. 6 is a flowchart of the code compression conversion process in the digital signal processing processor 1a.

Next, as in the conventional example, linear codes a1, a2,...
...a14 is a non-linear PCM code AI, A2, ・
The operation when converting to =-A8 will be explained.

First, the digital signal processor 1a outputs the 1-bit sign code a1 in the linear code to the signal line 5 as it is. At this time, the cp of register 8 is input from the decoder 2a.
A set signal is output to the terminal, and the sign code a1 is set in the register 2.

Next, the digital signal processor 1a converts the linear codes a1 to a14 into absolute values, and further converts them into "+33" (or l
-+32J), and the signs a2-, a3-.

. . . a14' and outputs it to the register 9 via the signal line group 6. At this time, a set signal is output from the decoder 2a to the cp terminal of the register 9 via the signal line 7b, and the added and corrected codes a2--a14
' is set in the register 9.

The sign code a1 and the addition-corrected code a2 =~a14- set in registers 8 and 9 are converted into 8-bit nonlinear PCM code AI,
A2, . . . A8 are converted, and further inverted and output.

According to the embodiment, there is no need for the digital signal processor to temporarily store the sine code in the linear code, perform other processing on the linear code, and then perform the process of adding the sine code again. The number of program steps is correspondingly reduced, and the processing time required for code compression conversion processing is reduced.

FIG. 7 shows another embodiment of the present invention, in which an example in which processing is performed for excessive values of linear codes is shown. That is,
In the figure, 10 is a register for storing a signal instructing excessive value processing, and the signal is output from the digital signal processor 1a to the register 10 via a signal line 11 and set therein.

Based on the signal, the code compression converter 5 fixes the output non-linear PCM code to the maximum positive value or the maximum negative value. Note that the other configurations and operations are the same as those in the previous embodiment.

(Effects of the Invention) As explained above, according to the present invention, the number of program steps in the digital signal processing processor can be effectively reduced with a configuration that minimizes the increase in hardware. There are advantages such as the processing time is reduced, the processing time can be allocated to other digital signal processing, and the digital signal processing ability can be expected to be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the code compression conversion method of the present invention, FIG. 2 is a diagram showing the correspondence between linear codes and non-linear PCM codes in the 8-bit μ law, and FIG. 3 is an 8-bit A Figure 4 is a diagram similar to Figure 2 in the law, Figure 4 is a diagram showing an example of a conventional code compression conversion method, Figure 5 is a flowchart of processing in the circuit of Figure 4, and Figure 6 is a diagram of the circuit of Figure 1. The process flowchart, FIG. 7, is a block diagram showing another embodiment of the present invention. 1a...Digital signal processing processor, 2a...
Decoder, 4... Code compression converter, 8... First register, 9... Second register. Patent applicant: Oki Electric Industry Co., Ltd. Patent attorney Furu 1) Takashi Sei Figure 1 Flowchart of processing in the circuit shown in Figure 4 Figure 6 Figure 7

Claims (1)

[Claims] A digital signal processor converts a linear code including a sign code indicating the polarity of the input into an absolute value, adds a certain numerical value, and compresses the sign code and the code after addition correction. In a code compression conversion method that inputs the sine code into a conversion circuit and converts it into a non-linear PCM code, a first register that stores the sine code and a first register that stores the sine code after the addition correction is provided between the digital signal processing processor and the code compression conversion circuit. The digital signal processing processor first outputs and sets the sign code to the first register, then performs the absolute value conversion and numerical addition processing, and after the addition correction 1. A code compression conversion method characterized in that the code of is output to and set in a second register.