JPS62266681A - Semiconductor device - Google Patents

Abstract

PURPOSE:To test a digital delaying means independently by incorporating a coincidence discriminating means in a semiconductor device in which a picture signal processing circuit a digital delaying means of (n) line is incorporated. CONSTITUTION:When picture signals of the same content are inputted to an input terminal 2 repeatedly every one line, after lapse of period of two lines from the start of inputting, the input picture signals perfectly coincide with two-line delay signals if operation of a two-line memory 3 is normal, and accordingly, signals of L level are outputted from a coincidence circuit 6. Conversely, when the input picture signals and two-line delay signals are discordant even 1 bit, H level is outputted from the coincidence circuit 6. Accordingly, normality of the two-line memory 3 can be tested by output signal of the coincidence circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device incorporating an image signal processing circuit including a digital delay means.

[Prior Art] FIG. 5 is a schematic block diagram showing a semiconductor device incorporating a conventional image signal processing circuit. In FIG. 5, an image signal processing integrated circuit 1 includes a two-line memory 3 and a signal processing circuit 4. As shown in FIG.

The 2-line memory 3 delays the 8-pit digital image signal input to the input terminal group 2 by 1 line (1 day) and 2 lines (2H), and outputs each delayed output by 8 pits. The signal is supplied to the signal processing circuit 4. The signal processing circuit 4 performs predetermined image processing based on the 8-pit digital image signal input to the input terminal group 2 and the 8-pit 1-line delayed output and 2-line delayed output delayed by the 2-line memory 3. Let's do it.

[Problems to be Solved by the Invention] The conventional image signal processing integrated circuit 1 is configured as described above, and the delayed output of the 2-line memory 3 is directly given to the signal processing circuit 4 without being taken out to the outside. Therefore, there was a drawback that it was not possible to test only the two-line memory 3 alone.

Therefore, a main object of the present invention is to provide a semiconductor device in which an image signal processing circuit including a digital delay means is built, in which the digital delay means can be easily tested.

[Means for Solving the Problems] The present invention provides a semiconductor device incorporating an image signal processing circuit including an n-line digital delay means, in which a coincidence determination means is built-in, and an input signal input to the digital delay means is The first line delay signals output from the digital delay means are compared to determine if they match.

[Effect]

Since the semiconductor device according to the present invention determines whether the input signal input to the digital delay means matches the delayed output signal, it is determined whether the digital delay means is defective based on the match determination output. You can easily test whether it is true or not.

[Embodiment of the invention] FIG. 1 is a schematic block diagram of an embodiment of the invention.
FIG. 2 is a concrete block diagram of the matching circuit shown in FIG. 1.

First, the configuration of an embodiment of the present invention will be described with reference to FIGS. 1 and 2. In addition, in Figure 1,
The 2-line memory 3 and the signal processing circuit 4 are the same as those in FIG. 5 described above, and the difference is that a minus number circuit 6 is provided. The minus number circuit 6 determines whether the 8-pit input image signal input to the 2-line memory 3 and the 8-pit 2-line delayed signal output from the 2-line memory 3 match or do not match. The match determination output of the -number circuit 6 is output from the output terminal 7.

As shown in FIG.
0 to 27 and 8 manual NOR gate 28 and inverter 2
It consists of 9. EXNOR gates 20 to 27
One input terminal of each of the 8-pit input image signals (OH7 in order from MSB) input to the 2-line memory 3
~0HO) is input, and the other input terminal receives an 8-pit 2-line delay signal (MSB
287 to 2HO) are input in order.

FIG. 3 is a timing diagram for explaining the operation of one embodiment of the present invention.

Next, number one! The specific operation of an embodiment of the present invention will be described with reference to FIGS.

When a uniform signal with the same content is repeatedly input to the input terminal 2 line by line, as shown in FIG. If the operation is normal, the input i-image signal and the two-line delayed signal completely match. When the input image signal and the 2-line delayed signal match in this way, EXNO
The outputs of the R gates 20 to 27 are all at the °4LH level, and an L'' level signal is output to the coincidence output terminal 7.

Conversely, if the input image signal and the 2-line delay signal do not match even by one pit, for example, if there is a mismatch between OH3 and 2H3, the output of the EXNOR gate 23 becomes "H" level, and as a result, the match output terminal 7, the "H" level appears (point A in FIG. 3). Therefore, it is possible to easily test whether the two-line memory 3 is operating normally by the signal output to the coincidence output terminal 7 of the - number circuit 6.

FIG. 4 is a schematic block diagram of another embodiment of the invention. In the example shown in FIG. 4, the present invention is applied to an image signal integrated circuit 11 having a built-in A/D converter 13. An analog image signal is input to the A/D converter 13 from the input terminal 12, and this analog image signal is converted into a digital signal by the A/D converter 13, delayed by the 2-line memory 3, and
- It is also given to the number circuit 6. - The number circuit 6 is the first circuit described above.
Coincidence of the digitized image signal and the digital image signal delayed by two lines by the two-line memory 3 in the same manner as in the embodiment shown in the figure.

A test is performed to determine whether the 2-line memory 3 is operating normally by determining the mismatch.

In the above embodiment, two digital delay means are used.
Although the line memory 3 is used, the present invention is not limited to this, and other circuit means such as a shift register may be used. Further, the number of lines to be delayed is not limited to two lines, and may be any number of lines.

Further, in the above embodiment, it is determined whether the delayed output of the last line and the input image signal match, but it is also possible to determine whether the delayed output of any line matches the input signal. For example, a plurality of bears for matching determination may be set. In that case, matching circuits equal to the number of bears are required, but the portion where the error occurs can be more accurately identified.

Furthermore, the image signal is not limited to 8 bits, and may be any number of bits.

[Effects of the Invention] As described above, according to the present invention, the coincidence determination means for comparing the input image signal to the digital delay means and the delayed output signal to determine whether they match or not is incorporated, so that at least one By simply providing output terminals for individual match determination means,
Digital delay means included in the image signal processing circuit can be tested independently.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention. FIG. 2 is a concrete block diagram of the matching circuit shown in FIG. 1. FIG. 3 is a timing diagram for explaining the operation of one embodiment of the present invention. FIG. 4 is a schematic block diagram of another embodiment of the invention. FIG. 5 is a schematic block diagram of a conventional image signal processing circuit. In the figure, 1 is an integrated circuit for image signal processing, 2 is an input terminal group, 3 is a 2-line memory, 4 is a signal processing circuit, 6 is a coincidence circuit, 7 is a coincidence output terminal, and 13 is an A/D converter.

Claims (1)

[Scope of Claims] A semiconductor device incorporating an image signal processing circuit including an n-line digital delay means, wherein an input signal input to the digital delay means and an m-th line delay signal outputted by the digital delay means (
1. A semiconductor device, comprising a match determining means for comparing m≦n and determining whether the respective matches match.