JPS6226486B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Among the instructions used in microcomputers (especially 4-bit instructions) is a skip instruction. This means that when the condition specified in this skip instruction is met, the instruction placed next to this skip instruction is skipped (ignoring the next instruction), and then the next instruction is executed. This is an instruction that performs processing that leads to the execution of an instruction (second instruction counting from the skip instruction). For example, now "A register is 0"
If we arrange in order a skip instruction that says "skip when ," and a branch instruction that follows this skip instruction that says "branch to address X," we get
When the A register is 0, the branch instruction is skipped and the branch is not taken.
If not, the next branch instruction is executed and branched to address X because the skip is not performed. Therefore, by arranging these two commands as described above,
If the A register is not 0, branch to address X,
If it is 0, do not branch (execute the next instruction)
A conditional branch instruction can be constructed.
In addition, this skip instruction can be executed by combining the next instruction with various other instructions to execute that instruction only when the conditions specified by this skip instruction are not met. When a condition is met, the command can be ignored in a wide variety of ways. By using a general conditional jump instruction and selecting the jump destination as the next instruction after this conditional jump instruction,
Although the same effect as this skip instruction can be obtained, the jump instruction has the advantage of being able to specify an arbitrary jump destination, but it is necessary to specify the address of the jump destination. On the other hand, the skip instruction has the advantage that it can be used without specifying the address of the next instruction after the skip instruction at all, no matter how many bytes the next instruction to ignore is. Skip instructions for performing such processing are widely and conveniently used, especially in 4-bit microcomputers, etc., which have fewer types of instructions. Furthermore, the above-mentioned process of ignoring instructions other than the skip instruction can be effectively used in the following cases.

In other words, if instructions of the same type are stored in memory sequentially, one instruction at the address specified first is executed, and if the next instruction is defined as the same type of instruction as the first instruction. If the command has been executed, this function ignores this command (the second command) and proceeds to the next command (without executing this command). With such a function, you can use it conveniently as follows. For example, at the beginning of the current subroutine, put an instruction to put 3 in the A register, the second instruction put 4 in the A register, and then the third instruction put 5 in the A register.
Line up the commands to place . Suppose that a routine is then placed that performs processing using the contents of the A register as a parameter. When entering this subroutine now, if you enter from the first instruction to put 3 in the A register, this subroutine will first put 3 in the A register, but the next instruction, that is, the instruction to put 4 in the A register, will Since it is the same type of instruction as the above-mentioned instruction that places 3 in the A register that was executed first (this is defined as the same type of instruction), it is ignored by the above-mentioned function and further adds 5 to the next A register. I proceeded with the order to leave. However, this instruction is also ignored because it is the same type of instruction as the previous instruction, and in the end, in this case, the subroutine is executed with the initially given 3 as the value of the A register and using that as a parameter. It turns out. However, when entering this subroutine for the first time, if it is entered from an instruction to place 4 in the second A register, the subroutine will be executed with 4 as a parameter because of the same processing as described above. Become. Similarly, when this subroutine is entered from an instruction to place 5 in the third A register, this subroutine is executed with 5 as a parameter. In this way, when entering a subroutine, you can easily create a subroutine that performs processing with different parameters simply by changing and specifying the first entry address. In this way, if a group of instructions is defined as the same type of instructions, and the same type of instructions appear consecutively,
The above-mentioned function of executing the first command but ignoring subsequent commands will be referred to as the command stacking function.

When performing the above-mentioned skip command or command stacking function, if the appropriate conditions are met (i.e., in the case of a skip command, if the conditions specified by this command are met, or when the command stacking function is executed) In a conventional microprogram control device, the instruction is ignored during the execution of the instruction that should be ignored (if the condition is that the instruction is of the same type as the instruction before it). The method is to activate a prohibition circuit that prohibits the execution effect, thereby rendering the command ineffective. For this reason, for example, if you want to make an instruction that requires 6 machine cycles to execute have no effect, in conventional devices, even if you make it have no effect, it will take the same 6 machine cycles as if the instruction was normally executed. This method has the disadvantage that machine cycles are expended before proceeding to the next instruction, and the processing time is longer than necessary. The object of the present invention is to provide a microprogram control device that eliminates such drawbacks.

The microprogram control device of the present invention includes a program counter that specifies a memory address, a decoder that decodes an instruction that makes the next instruction ineffective when a specified condition is met, and a decoder that decodes the instruction. means for suppressing the execution of the next instruction after the instruction when the condition specified by the instruction is met, and means for normally executing the next instruction when the instruction does not exist in the above-mentioned case. and means for setting the contents of the program counter to specify the address of the instruction following the next instruction within fewer machine cycles than required for the next instruction.

Next, the microprogram control device of the present invention will be explained in detail using the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. Reference numeral 1 indicates a microinstruction memory circuit. When executing a certain instruction, in the first machine cycle of that instruction, from among the microinstructions stored in this instruction,
The first byte of this instruction at the address specified by the program counter 3 is first read and stored in the instruction register 2. When the first byte of the microinstruction is thus read into the instruction register 2, it is decoded by the decoder 4 and this instruction is
Depending on whether the instruction is a byte instruction, a 2-byte instruction, or a 3-byte instruction, the control circuit 5 controls the program counter control circuit 6 to increase the program counter 3 every machine cycle required to further decode this instruction. The contents of the instruction register 2 are advanced by one and all bytes belonging to that instruction are stored in the instruction register 2.
are sequentially read and deciphered. The execution control circuit 5 executes the process specified by the microinstruction thus decoded. Thus, after a further number of machine cycles necessary for the execution of this instruction have elapsed, the control circuit 5, via the program counter control circuit 6, increments the contents of the program counter 3 by one more. Then, in the next machine cycle, the first byte of the next instruction located at the address specified by the contents of this program counter 3 is read out,
In this way, execution proceeds to the next new instruction.

Now, suppose that a skip instruction is read into instruction register 2. This is decoded by the instruction decoder 4 as described above, but by specifying that this is a skip instruction, the logic level of the skip instruction designation line 7 is set to "1". Further, a portion of this skip instruction specifying a skip condition is supplied to a skip condition selection circuit 8, and the condition signal specified by this skip instruction is selected from among various skip condition signals 9. (This condition signal 9
For example, if the content of the A register mentioned above is 0, the logic level will be "1", and if the content of the A register is not 0, the logic level will be "0". Various condition signals are included, such as a signal whose logic level is "1" when there is input data in the port that has been input, and whose logic level is "0" when there is no input data. ) The condition signal selected by the skip condition selection circuit 8 is combined with the signal on the skip instruction designation line 7 using an AND circuit 10 and applied to the set terminal of the flip-flop 11.

Therefore, flip-flop 11 is set when the skip instruction is decoded and the condition specified by the skip instruction is satisfied. Now, when the control circuit 5 has finished processing the skip command as described above, it increments the contents of the program counter 3 by 1 via the program counter control circuit 6. Then, in the next machine cycle, the first byte of the instruction starting from the address next to this skip instruction is read into the instruction register 2. By decoding the first byte of a certain instruction in this way,
Information on how many bytes this instruction consists of can be obtained, so extract the information that specifies the number of bytes of this instruction and add it to the byte count output line 1.
2 to one input of the adder 13. The other input of this adder 13 is supplied with the contents of the program counter 3. Now, the execution control circuit 5 reads the first byte of the instruction in this way,
When the byte number of the instruction has been decoded and the adder 13 has completed adding the byte number input and the contents of the program counter 3, a program counter write pulse is output via the program counter write pulse line 14. do. This program counter write pulse line 14
and the output line of the flip-flop 11 are combined in a second AND circuit 15, and thus only when the flip-flop 11 is set (i.e., the previous instruction is a skip instruction and the skip condition is satisfied). only occasionally)
At the output of the second AND circuit 15, the write pulse outputted via the program counter write pulse output line 14 appears. This write pulse controls the program counter control circuit 6 to write the output of the adder 13 into the program counter 3. Thus, the contents of the program counter 3 specify the first byte of the second instruction counted from the skip instruction. The above processing is generally completed within the machine cycle when the first byte of the instruction following the skip instruction is read. Now, the first byte of the second instruction thus specified is read out to the instruction register 2 in the next machine cycle, and the first machine cycle of this instruction is started again.

After generating a write pulse on the program counter write pulse line 14, the execution control circuit 5 generates a reset pulse near the end of this machine cycle, and sends it to the flip-flop via a reset pulse line 16. 11 to reset the flip-flop 11. Furthermore, the output of the flip-flop 11 becomes one input of the second AND circuit 15, and is also supplied as an instruction execution suppression signal to the execution control circuit 5 via the instruction execution suppression signal line 17. During the period when the logic level of the line is "1", except for the generation of the program counter write pulse and reset pulse, which are performed by the execution control circuit 5,
Other processing that should be performed as a result of decoding the first byte is suppressed. At the same time, the trailing edge portion of this signal is used to set the execution control circuit 5 to treat the byte read into the instruction register 2 in the next machine cycle as the first byte of a new instruction. .

Of course, even if the skip instruction is decoded, if the condition specified by the skip instruction is not satisfied, the flip-flop 11 will not be set, so the instruction following the skip instruction will be executed according to the normal process mentioned above. Ru.

In this way, the function of the skip instruction described above is realized, but as is clear from the above explanation, if the skip condition of the skip instruction is satisfied, regardless of the instruction following the skip instruction. It always takes one machine cycle (regardless of how many machine cycles it takes to properly execute this instruction) to disable the instruction and proceed to the second instruction.

The time relationship of the above-mentioned processing is shown in FIG. FIG. 2A shows an example of a conventional device. If the memory address where the skip instruction is stored is n, the contents of the program counter will read out the skip instruction at n first. Assume that the skip condition is not satisfied. In the next machine cycle, the contents of the program counter become n+1 and the first byte of the next instruction is read. For example, the following command requires 6
Assume that it is a 3-byte call instruction that requires machine cycles. In this case, the contents of the program counter advance to n+3 in successive machine cycles to read all three bytes of this instruction, and it takes three more machine cycles to complete execution of this instruction. Then, in the next machine cycle, the program counter advances to n+4, reads the first byte of the next instruction following the skip instruction, and starts executing this instruction anew. The processing in this case is shown in the second diagram of FIG. 2A when the skip condition is not satisfied. If the skip condition is satisfied, a 1-operation instruction (NOP) is executed instead of the original call instruction during the machine cycle in which the next instruction (the call instruction) after the skip instruction is to be executed. This is repeated, and after 6 machine cycles are effectively spent without any processing, execution of the next next instruction begins. This is shown as a diagram when the skip condition is met in FIG. 2A.

On the other hand, the case of this embodiment is shown in FIG. 2B. In this case as well, when the skip condition is not satisfied, the process is exactly the same as in the conventional example as shown in the figure. However, if the skip condition is met, as shown in the diagram when the skip condition is met in Figure 2B, in one machine cycle following the skip instruction, the program counter is updated by the number of bytes of the instruction following the skip instruction. (In this example, the program counter is advanced by 3 at a time.) In the next machine cycle, the next instruction after the skipped instruction is executed. It shows that you can enter.

Note that in the above embodiment, by adding the contents of the program counter and the number of bytes of the next instruction after the skip instruction using an adder, the second
Although the address of the th instruction is directly obtained and thereby the skip processing is performed in the minimum processing time, it is also possible to perform the skip processing as follows instead. That is, the output of the flip-flop 11 and the output of the byte number output line 12 are directly applied to the program counter control circuit 6, and when the output of the flip-flop 11 reaches logic level "1", the byte number output line It is also possible to adopt a configuration in which the contents of the program counter 3 are advanced in a faster cycle than when normal instruction processing is performed by the number of bytes specified by the output of the program counter 3.

As described above, by using the present invention, it is possible to provide a microprogram control device that can perform processing in a shorter processing time than conventional devices when a skip instruction makes the next instruction ineffective. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a diagram illustrating the progress of execution of a skip instruction. In FIG. 1, 1... micro instruction memory circuit, 2... micro instruction register, 3... program counter, 4... instruction decoder, 5... execution control circuit, 6... program counter control circuit,
7... Skip command designation line, 8... Skip condition selection circuit, 9... Skip condition, 10... AND circuit, 11... Flip-flop, 12...
Byte number output line, 13... Adder, 14...
Program counter write pulse line, 15
. . . second AND circuit, 16 . . . reset pulse line, 17 . . . instruction execution suppression signal line.

Claims (1)

[Claims] 1. Specify a memory containing a control instruction defined to invalidate a multi-byte instruction scheduled to be executed next when a predetermined condition is met and execute another instruction, and the address of the memory. an addressing circuit; an address incrementing circuit that increments the addressing circuit in accordance with execution of an instruction; a detection circuit that detects that the control instruction is read from the memory; and the predetermined condition is satisfied. the number of bytes of the instruction to be invalidated in the first byte of the instruction to be invalidated; , and when the establishment signal is generated from the condition determination circuit, the number information indicating the number of bytes provided in the first byte of the instruction to be invalidated and the address designation circuit. The microprogram control device is characterized in that the adding circuit adds the contents of the instruction and the content of the instruction to be invalidated using the addition result as an address to access an instruction next to the instruction to be invalidated.