JPS6225508A - Pll control device - Google Patents

Abstract

PURPOSE:To give compatibility of a PLL circuit between a conventional control system and a new control system by using a control data of an exclusive format and also that of a different format so as to control the PLL circuit. CONSTITUTION:A format discriminating means 60 supervises a signal of a latch line LAT of a bus line 32 at all times and when no latch signal comes, it is discriminated that an exclusive data of the 1st format is transferred to the PLL circuit 42 via the bus line 32. In this case, the format discriminating means 60 operates switch means 51, 55 to input the data in a memory circuit 52, the format of the output data is converted into the 1st format exclusive to the PLL circuit 42 from the 2nd format by the format conversion circuit 54 and the result is sent to the PLL circuit 42 through the switches 51, 52.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A: Industrial field of application B: Outline of the invention C: Conventional technology (Figs. 4 and 5) D: Problem to be solved by the invention (Fig. 5) E: Means for solving the problem (Fig. 1) ) F Effect (Figure 1) G Example (Figures 1 to 3) H Effect of the invention A Industrial field of application Is the present invention pLLilIJ? The present invention relates to an Ill device, and can be applied to, for example, a television receiver.

B Overview of the Invention The present invention is based on PLL (phase 1ooked
1oop) The frequency division ratio of the circuit is controlled by a microcomputer.In the control device, the PLL circuit, which is conventionally configured to be controlled by a dedicated microcomputer using control data in a first format, is changed to a different second format. The aim is to maintain compatibility between the conventional control system and the new control system by making it possible to control the system using the same control data.

C. Conventional Technology For example, in a television receiver, each component is integrated into an IC to make it suitable for mass production and to reduce the size of the circuit board.

That is, in a conventional television receiver, as shown in FIG. 4, a broadcast wave of a channel received by a tuner circuit section 2 via an antenna 1 is amplified by an intermediate frequency circuit section 3, and then converted into a video signal. The SV is supplied to the cathode ray tube 5 through the video circuit section 4, and the audio signal SA is supplied to the speaker 7 through the audio circuit section 6.

The tuner circuit section 2 is provided with a PLL circuit 11, and this PLL circuit 11 is a PLL circuit configured with a microcomputer.
It is controlled by a control circuit 12.

Here, the PLL circuit 11 divides the frequency of the oscillation signal of the VCO using a programmable frequency divider and supplies the divided signal to the phase comparator circuit.In this way, by controlling the frequency division ratio of the programmable frequency divider, the output of the vCO and therefore the local The frequency of the oscillation signal can be controlled.

The PLL control circuit 12 is connected to a PLL bus line 13, and a channel selection command circuit 14 is connected to the PLL bus line 13.
are combined. The channel selection command circuit 14 selects the PLL bus line 1 by operating the channel selection switch 15.
3, channel data having a format exclusive to the PLL circuit is sent to the PLLlliIIJ circuit 12.
Enter.

In addition, the channel selection command circuit 14 receives the channel data selected by the remote control operator 16 and transmits P.
The signal can be supplied to the PLL control circuit 12 through the LL bus line 13.

The PLL control circuit 12 transfers control data to the PLL circuit 11 via the PLL bus line 13 based on the tuning data supplied from the tuning command circuit 14.
By controlling the frequency division ratio of the programmable frequency divider of the L circuit 11, the tuner circuit unit 2 is responsively operated to receive the selected channel.

A nonvolatile memory 17 is coupled to the PLL bus line 13, and the nonvolatile memory 17 can be used to store tuning command data when the power is turned off.

Here, the PLL bus line 13 is as shown in FIG.
The PLL control circuit 12 is composed of a latch line LAT, a clock line CLK, and a data line DAL.
The channel selection command circuit 1 transmits the data sent to the data line DAL and the clock signal to the clock line CLK.
4. Non-volatile memory 17, PLL control circuit 12 to PL
By transferring data to the L circuit 11 and sending a latch signal to the latch line LAT, the data line DAI
, the data is latched to the transfer destination.

In addition to such conventional configurations, recently there has been a method in which each circuit section of a television receiver is integrated into an IC, and the IC circuit section is controlled by a central processing unit (CPU) configured as a microcomputer. It is considered.

For example, it is conceivable that the intermediate frequency circuit section 3 is configured with an IC consisting of an IF processor, and at the subsequent stage, an IC consisting of a video processor is used as the video circuit section 4, and an IC consisting of an audio processor is used as the audio circuit section 6. It will be done. In this case, the tuner circuit section 2 also includes the PLL circuit 11, the reception band switching circuit, the AGC
It is conceivable to convert each circuit into an IC.

In this way, if each circuit section can be integrated into an IC, the television receiver can be controlled as a whole by the CPU, making it possible to further reduce the size of the television receiver, and making adjustments to each circuit section during manufacturing easier. It is believed that this can be easily performed using a CPU.

D Problems to be Solved by the Invention As described above, it is conceivable to use an I"C bus (inner ICbus) as a method of controlling a large number of devices such as microcomputers and ICs with one CPU. ``The C bus consists of a clock bus line and a data bus line, and is configured so that a destination address is added to data and sent to the data bus line, and a device with the address takes in the data from the data bus line. ing.

However, using such an I"C bus, each circuit section is
When trying to control the PLL circuit using the PLL bus method, the bus configuration and data format do not match the PLL bus method that has been put into practical use for PLL circuits in the past, so there is an inconvenience that the conventional PLL circuit cannot be used as is.

The present invention has been made in consideration of the above points, and aims to make it possible to utilize the PLL circuit, which has been put into practical use in conventional tuner circuits, also in IIC bus type control systems with different data formats. It is.

Means for Solving the EMB Point In order to solve this problem, in the present invention, the input terminals T1 to T3 connected to the bus line 32 consisting of the data line DAL, the clock line CLK, and the latch line LAT, The PLL circuit 42 is connected to the input terminal T3 corresponding to the latch line LAT, and the data supplied from the bus line 32 is connected to the PLL circuit 42 which controls the division ratio of the programmable frequency divider in response to data in the first format.
a format determining means 60 for determining whether the data has the same format or a second format different from the format, a memory circuit 52 for storing data when data is supplied from the bus line 32, and an output of the memory circuit 52. The data supplied from the bus line 32 is controlled by a format conversion circuit 54 that converts the data format from the second format to the first format and outputs the converted data, and a determination output from the format determination means 60, so that the data supplied from the bus line 32 is converted into the first format. When a discrimination output indicating that the format is the second format is obtained, the data of the input terminals T1 to T3 is directly sent to the PLL circuit 42, or when a discrimination output indicating that the format is the second format is obtained. The data of ~T3 is input to the memory circuit 52, and the output data obtained by being converted into the first format by the format conversion circuit 54 is input to the PLL.
A switch means (51, 55) for sending the signal to the circuit 42 is provided.

The F-action format determining means 60 constantly monitors the signal on the latch line LAT of the bus line 32, and when the latch signal does not arrive, the data in the dedicated format for the PLL circuit 42, that is, the first format, is transferred to the bus line 3.
It is determined that the message was transferred through 2. At this time, the format determination means 60 operates the switch means (51, 55), thereby inputting the data taken in from the bus line 32 to the memory circuit 52, and changing the format of the output data to the second one in the format conversion circuit 54. The format is converted into a dedicated first format by the PLL circuit 42, and the switch means (51, 55
) to the PLL circuit 42.

On the other hand, when the latch signal does not arrive, the format determining means 60 determines that data in the second format has been transferred to the bus line 32.At this time, the format determining means 60 determines that the data of the second format has been transferred to the bus line 32. 51,5
5), thereby allowing the data fetched from the bus line 32 to be directly input to the PLL without format conversion.
The signal is sent to the circuit 42.

Thus, according to the above-mentioned PLL control device, the PLL circuit 4
In both cases, when data having a first format dedicated to 2 arrives, and when data having a second format different from this dedicated format arrives, the conventional PLL circuit 42
can be used to enable the PLL circuit 42 to be controlled even by data having a format different from its dedicated format.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

Figure 2 shows the overall configuration of a television receiver.
As shown by assigning the same reference numerals to parts corresponding to those in FIG. 4, an intermediate frequency signal obtained in an IC tuner circuit section 2 is supplied via an antenna 1 to an intermediate frequency circuit section 3 having an intermediate frequency processor configuration. By supplying the video signal obtained at the output terminal to a video circuit unit 4 having a video signal processor configuration, the RGB signal obtained at the output terminal is supplied to the cathode ray tube 5. Furthermore, the audio signal SA obtained at the output end of the intermediate frequency circuit section 3 is given to an audio circuit 6, and its audio output is supplied to a speaker 7.

Here, each circuit section is coupled to a bus line 32 of the CPU 31 and is controlled as a whole by the CPU 31.

An adjustment terminal 35 is connected to the bus line 32, and an adjustment device 36 configured with a computer, for example, is connected to this adjustment terminal 35 at the time of factory shipment, and each circuit unit is controlled based on the adjustment operation data supplied from the adjustment device 36. can be set to a predetermined adjustment state.

In the configuration shown in FIG. 2, the bus line 32 of the CPU 31 is composed of an I''C bus. 3.4.6 are commonly used to exchange data with the CPU 31, and thus control the circuit portions connected to the bus line 32 as a whole under the control of the CPU 31.

The data line of the bus line 32 consisting of this I"C bus carries data having the format shown in FIG.
31 to each circuit section.

That is, following the start bit D1, the CPU 31 sends out address data D2 (consisting of 8 bits) attached to the device to which data is to be transferred, and receives a 1-bit answer signal D3 from the device. . Thereafter, 3 consecutive bytes of 1 byte data consisting of 8 bit data and 1 bit answer signal are transferred, thus completing the data transfer to the device specified by address data D2. is being done.

When data having the format shown in FIG. 3 is sent from the CPU 31 to the bus line 32, the address data D2 included in the sent data is taken into the assigned device, and thereby each circuit section is Using a common bus line 32, data for a plurality of devices is sequentially transferred to the device itself.

In addition to the above configuration, the PLL circuit 1 of the tuner circuit section 2
1 and the bus line 32, as shown in FIG. 1, a tuner interface circuit 41 each composed of an IC is provided. Circuit 42, band switching circuit 43, AGC voltage generation circuit 44
, is supplied to the AGC detection circuit 45.

Here, the band switching circuit 43 receives band switching data from the bus line 32 via the tuner interface circuit 41, and the tuner selects a predetermined band for the band to which the selected channel belongs (i.e., VHF low band or high band, UHF band). The resonant constant of the resonant circuit provided in the tuner is changed and controlled so as to exhibit the frequency characteristics of the tuner.

Further, the AGC detection circuit 45 detects the signal level of the intermediate frequency signal obtained on the output side of the tuner, and further transmits the signal level to the bus line 32 via the tuner interface circuit 41.
The data is transferred to the CPU 31 via the . At this time, the CPU 31 sends AGC voltage control data to the bus line 32.

This AGC voltage control data is supplied to an AGC voltage generation circuit 44 via a tuner interface circuit 41, and this AGC voltage generation circuit 44 generates an AGC voltage to be fed back to the input end of the tuner.

The tuner interface circuit 41 has a PLLM control circuit 50, and connects the bus line 32 to the memory circuit 52 via its input terminals T1 to T3 and further via the switch circuit 51. After data is once loaded into the memory circuit 52, processing within the tuner interface circuit 41 is executed based on the loaded data. Also, when transferring data from the tuner interface circuit 41 to the CPU 31, the data is first taken into the memory circuit 52 and then transferred to the CPU 3 via the bus line 32.
Send and issue to 1.

In this embodiment, from the bus line 32 to the memory circuit 52
As described above with reference to FIG. The corresponding timing signals AD1, AD2, AD3, AD4 are generated.The timing signal ADI is generated by the format conversion circuit 54.
A dedicated format, that is, a first format, which allows data stored in the memory circuit 52 to be taken into the format conversion circuit 54 and the PLL circuit 42 to operate in response when the timing signal ADI is applied. Convert to data. The data D1 thus converted in the format conversion circuit 54 is supplied from the tuner interface circuit 41 to the PLL circuit 42 through the switch circuit 55.

Similarly, the address of the data taken into the memory circuit 52 is transferred to the band switching circuit 43 and the AGC voltage generation circuit 44.
, AGC detection circuit 45, timing control circuit 53 outputs timing signals AD2, AD3, AD4, respectively.
is generated and applied to the band switching control circuit 49, the digital/analog conversion circuit 5G, and the analog/digital conversion circuit 57, respectively, and the corresponding data is supplied from the memory circuit 52 to the band switching circuit 43 and the AGC voltage generation circuit 44, or The detection signal detected by the AGC detection circuit 45 is taken into the memory circuit 52 and transferred to the bus line 32.

PLL1! l? The timing control circuit 53 and CPU 31 of one circuit 50 include a video signal processor 4 (FIG. 2).
While the received video signal is in the vertical synchronization period, data is transferred from the CPU 31 to the tuner interface circuit 41 via the bus line 32, and synchronized with this. Then, the timing control circuit 53 sends out the timing signals ADI to AD4, so that each circuit of the tuner circuit section 2 executes a data import operation or a data transmission operation in synchronization with the vertical synchronization signal VSYNC. Control over each circuit of the tuner circuit section 2 can be executed during the vertical synchronization period. As a result, unnecessary beat signal components can be prevented from being mixed into the tuner circuit section 2 while processing minute video signals.

In addition to the above configuration, the tuner interface circuit 41 has a format determination circuit 60, and the PLL circuit 4
2 is supplied from the bus line 32 in a dedicated format that allows the PLL circuit 42 to perform a responsive operation.
be able to supply the

The format determination circuit 60 divides the frequency of an oscillation output pulse to the oscillation circuit 61 using a frequency divider 62, and counts the frequency-divided output pulses using a counter 63. counter 63
is connected to the latch line LAT constituting the bus line 32, and when a latch signal arrives from the latch line LAT, it is received at the count enable terminal and starts a counting operation. Here, the counter 63 is set to send out a carry signal in a time shorter than the rise width of the latch signal coming from the latch line LAT, generates a switching control signal SWC based on the carry signal, and sends it to the switch circuit 51 and Give to 55.

When the switching control signal SWC is not generated, the switch circuit 51 inputs signals inputted from the data line DAL, the clock line CLK1, and the latch signal line LAT through the input terminals T1, T2, and T3 to the memory circuit 52 through the contact a. . At this time, the switch circuit 55 similarly supplies the converted output D1 of the format conversion circuit 54 to the PLL circuit 42 through the contact a.

On the other hand, when the switching control signal SWC is generated, the switch circuits 51 and 55 switch from the contact a side to the contact side, thereby transmitting the signals input through the input terminals T1, T2, and T3 to the switch circuits 51 and 55. are sequentially sent directly to the PLL circuit 42.

In the above configuration, when a 1"C bus is used as the bus line 32, the bus line 32 transfers data using the data line DAL and the clock line CLK, and therefore the data is transferred to the tuner interface circuit 41. The incoming data has a second format that does not allow PLL circuit 42 to act responsively.

In this state, since no latch signal arrives at the latch signal line LAT, the format discrimination circuit 60 discriminates this. That is, the counter 63 maintains a state in which it does not generate the switching control signal SWC by not starting a counting operation. Therefore, the switch circuits 51 and 55 have contact a
This causes the data line DAL and the clock line C to be connected through the input terminals T1 and T2.
Data and clock signals coming from LK are stored in memory circuit 52.

At this time, the data stored in the memory circuit 52 is converted by the format conversion circuit 54 into a second format in which the PLL circuit 42 can operate in response, and then supplied to the PLL circuit 42 through the switch circuit 55.

Thus, the PLL control circuit 50 receives from the bus line 32,
When the data of the second format, which the PLL circuit 42 cannot respond to, arrives, it is transferred to the second format, which can respond to the PLL circuit 42.
By converting the data into the format and supplying it to the PLL circuit 42, the PLL circuit 42 can be applied as is even to a bus system using data in a different format.

In this state, other circuits constituting the tuner circuit section 2 use the data stored in the memory circuit 52.
That is, the band switching circuit 43 and the AGC voltage generation circuit 44
, AGC detection circuit 45, and therefore I
``The PLL circuit 42 can be adapted to a system such as a C bus that uses a common bus line for a large number of devices and is controlled by a common CPU.

On the other hand, when data having a dedicated format arrives at the PLL circuit 42 via the bus line 32, as described above with reference to FIG.
When the latch signal arrives at the input terminal T3 from AT (FIG. 5), the counter 63 of the format discrimination circuit 60 performs a counting operation and generates the switching control signal SWC.

At this time, the switch circuits 51 and 55 have input terminals T1,
The data arriving from T2 and T3 is sent directly to the PLL circuit 42, so that the PLL circuit 42 can be operated responsively in this case as well.

Therefore, if the PLL*J control circuit 50 having the configuration shown in FIG. Even when using the supplied bus system, the PLL circuit 42
It is possible to provide compatibility so that the system can be shared without changing the configuration of the system.

Incidentally, when controlling the PLL circuit 42 with control data having a format dedicated to the PLL circuit 42, other circuits of the tuner circuit section 2, that is, the band switching circuit 43,
The AGC voltage generation circuit 44 and the AGC detection circuit 45 are controlled using dedicated control circuits, respectively.

In the above description, the present invention has been applied to a PLL circuit of a television tuner circuit, but the scope of application is not limited to this. It can be widely applied to PLL circuits that control frequency.

H Effects of the Invention As described above, according to the present invention, the PLL circuit is operated not only in response to control data having a dedicated format, but also in response to control data having a format different from the dedicated format. By being able to do this, the PLL circuit can be easily adapted to a system that includes a bus line that uses data in a particular format.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a PLL control device according to the present invention, FIG. 2 is a block diagram showing the configuration of a television receiver using the PLL control device of FIG. 1, and FIG. FIG. 4 is a block diagram showing a conventional television receiver, and FIG. 5 is a route map showing the configuration of the bus line 13. 2...Tuner circuit section, 11...PL
L circuit, 31...-CPU, 32...Bus line, 41...Tuner interface circuit, 42...PLL circuit, 43...
・Band switching circuit, 44...AGC voltage generation circuit, 45...AGC detection circuit, 51.55...
...Switch circuit, 52...Memory circuit,
53... Timing control circuit, 54...
・Format conversion circuit, 49... Band switching control circuit, 56... Digital/analog circuit, 57... Analog/digital circuit, 60...
...Format discrimination circuit.

Claims (2)

[Claims] (1) an input terminal connected to a bus line consisting of a data line, a clock line, and a latch line, and a PLL circuit that controls the division ratio of a programmable frequency divider in response to data in a first format; connected to the above input terminal corresponding to the above latch line,
a format determining means for determining whether data supplied from the bus line has the first format or a second format different from the first format; and when the data is supplied from the bus line; A memory circuit that stores the data, and a format of the output data of the memory circuit as described above.
is controlled by a format conversion circuit that converts the format from the above format to the first format and outputs it, and a discrimination output of the format discrimination means, and is controlled by a discrimination output of the format discrimination means to detect that the data supplied from the bus line is in the first format. When a discrimination output representing the second format is obtained, the data at the input terminal is directly sent to the PLL circuit, or when a discrimination output indicating the second format is obtained, the data at the input terminal is sent to the memory circuit. A PLL control device characterized by comprising: switch means for inputting and outputting data obtained by converting into the first format in the format conversion circuit to the PLL circuit. (2) A timing control circuit for receiving a vertical synchronization signal of a television signal is inserted on the output side of the format conversion circuit, and the output of the format conversion circuit is transmitted to the above through the switch means during the vertical synchronization period. A PLL control device according to claim 1, which is configured to supply the signal to a PLL circuit.