JPS62252591A - High speed memory device - Google Patents

Abstract

PURPOSE:To access a memory at a high speed by using an address determined in an early time and starting the access of the memory even when the time determined by a part of the address is later than the time determined by other part of the address. CONSTITUTION:The address of a dynamic RAM (DRAM) 10 is multiplexed to a row address and a column address through a multiplexer 5. When the row address and the column address are given to the DRAM 10, by using the fact that the time difference is necessary, an address determined earlier is given to the row address of the DRAM 10, and the address determined later is made into the address to decode to the column address and the memory device selecting signal. When the address for ascessing occurs and a memory device is not selected, the access to the memory is started, and only when the memory device selecting signal is generated by the address determined earlier, the reading or writing of the data are executed. Thus, the memory access can be executed at a high speed.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to high speed memory devices.

(Summary of the Invention) Even if the time at which some addresses are determined is later than the time at which some other addresses are determined, by starting memory access using addresses determined at an earlier time, , which allows high-speed memory access.

(Prior Art) In a conventional memory device, as shown in FIG. 6, a memory address 61 is decoded from an address 60 used to access the memory device, and a memory address indicating whether or not this memory device is selected is decoded. By receiving the select signal 64 and enabling the bus gate 65 that connects the memory 62 and data 67 to be input/output to the memory to an external data bus 66, read and write access to the memory device becomes possible.

However, in this method, if part of the address is determined later than other addresses, the memory device select signal 64 cannot be decoded until all addresses are determined, which delays the start of memory access, resulting in The disadvantage is that memory access time is generally long.

(Means for solving the problem) In the present invention, the address of a dynamic RAM (hereinafter referred to as DRAM) is multiplexed into a row address and a column address, and the row address and column address are
Taking advantage of the fact that a time difference is required when giving to RAM, give an address that is determined quickly to the row address of DRAM,
The address that is determined later is used to decode the column address and memory device select signal, and if an address that cannot be accessed occurs, access to the memory is started without selecting the uplink device, and the address that is determined soon This configuration allows high-speed memory access by executing data read or write only when a memory 5A location select signal is generated based on the address.

(Example) Fig. 1 is a block diagram of the present invention.
This is an embodiment in which a RAM is used to quickly determine an address of 9 bits or more, and FIGS. 2 and 3.4.5 are time charts showing this example of operation. Section 2.3, 4.5
The signal names given in the figure are the same as those shown in FIG.

The operation will be explained in detail below with reference to FIG. 1 and FIG. 2.3.4.5.

FIG. 2 is a time chart when a memory device is selected as a read.

Now, when FAO: ()7 store address - whichever address is determined earlier) becomes valid, this address is transferred to DRAMI by MA6: (memory address) through multiplexer 5.
It is given to O as a row address. On the other hand, FA(0)
The signal FAS2 ()7 store address strobe indicating the determination of R starts the timing controller 14 and
ASll: (Row address strobe) is generated.

The row address of DRAMIO is determined by MA6 and RASll. Then, when DAl: ('y'' erase address - address to be determined later) becomes valid, the one input to multiplexer 5 among this address is
Since the multiplexer 5 has been switched to the A side by the MUX8 signal, it is not input to DRAMlo. or,
The address of the other DAl input to the decoder 7 is
In the example shown in the figure, the content is to select a memory device, so 5
EL9: (Memory device select signal) is output. On the other hand, the timing controller 14 indicates the determination of DAl.
When the signal DAS4 is input, first a signal to switch the multiplexer 5 to the B side is generated to MUX8, and a signal to switch the multiplexer 5 to the B side is generated to MA6.
It operates so that the contents of AI are output and given to DRAMlo as a column address. Next, the timing controller 14 is slightly delayed and the CAS 12:
(column address strobe) and DRAMlo
Confirm the column address. At the same time, bus gate 1 connects external data bus 18 and memory data 17.
6 to DIR19: (direction signal) to read direction
15: (gate signal) and operates to output the data of DRAMlo to the outside.

With the above-described operation, data can be read from the time determined by the slow address DA1 only by delaying the column address access time of DRAMlo, so that high-speed access is possible.

Note that the RAS11 signal is transmitted to the timing controller 14.
It is negated when the required pulse width is generated by .

Also, CAS12. G15 is negated when DAS4 is negated.

FIG. 3 shows the time difference when a device accessing this memory device performs read access to another device.

Now, when FAO becomes valid and then FAS2 is applied, the row address and RASll are applied to DRAMlo at the previous timing, and the row address is determined.

Next, DAI becomes valid, but since this address selects another device, the output 5EL9 of the decoder 7 is not output.

Therefore, the timing controller 14 does not assert σAS12 or G15, so the memory device does nothing to the external bus 18.

Note that RASll is outputted from the timing controller 14 with the required pulse width.

FIG. 4 is a time chart when the memory device is selected for writing.

Now, when FAO is enabled, the timing controller 14
As in the previous explanation, use this as the row address,
FAS2 generates ml1 to determine the DRAMIO row address.

At this time, since the device accessing the memory device is asserting the W113 signal indicating that it is a write, the timing controller 14 gives WE13 to the DRAMlo. Also, the WR2 signal is asserted and F A S
2 is also asserted, the timing controller 14 sets the DIR 19 of the bus gate 16 to the write side and sets the G
15 signals are given.

As a result, the data 17 of DRAMlo is given the data to be written.

Next, when DAl becomes valid, the timing controller 14 operates to determine the column address of DRAMlo, as in the case of reading.

This allows writing to DRAMIO to be executed at high speed.

FIG. 5 is a time chart when a device accessing this memory device performs write access to another device.

Now, when FAO becomes valid and then FAS2 is applied, the timing controller 14 determines the row address of DRAMIO at the same timing as before. At the same time, since the timing controller 14 has been given the signal WR3 indicating write, it generates the WL13 signal for the DRAMlo.

At this time, the timing controller 1
4 gives the data to be written to DRAMlo,
Generates signals to DIR19 and G15.

Next, DAl becomes valid, but since this address selects another device, the output 5EL9 of the decoder 7 is not output.

For this reason, the timing controller 14
Since CAS12 is not asserted for o, DRAM
Writing to lo is not performed.

Further, RASll is outputted by the timing controller 14 only with a necessary pulse width.

(Effects of the Invention) As explained above, in a memory access device such as a CPU, even if some of the addresses become effective after a delay, the row address and column address of the DRAM are multiplexed and Taking advantage of the fact that these must be given in a staggered manner, the address to be determined first is given as the row address to avoid confirmation, and the address determined later is used to determine whether or not to confirm the column address. If the device is selected, memory access can be made at high speed.

Furthermore, although the explanation has omitted the explanation of the refresh operation necessary for the DRAM, this does not impede the content of the present invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention. FIG. 2 is a time chart for explaining read access to a memory device. FIG. 3 is a block diagram for explaining read access to a device other than a memory device. Figure 4 is a time chart for explaining the write access of a memory device. Figure 5 is a time chart for explaining the operation when write access is made to a device other than the memory device. 1 Block diagram showing a conventional example 5...Multiplexer 7...Decoder 10...DRAM 14...Dynamic controller 16...Busgate Applicant Seiko Electronics Co., Ltd. )IU22222M]:]2WE (13
3 Met') Sort of 51τ Time chart of the 7th encounter Fig. 2 One breath (2) -1 Ninini Nini H-cho Memoso 1 or more Tato and read access and time + Mart 3rd [Fig. Tie at the time of the first shift, 4-5-yards A I+1 -FA-(δ) 2 (1 effect (2)) U22222M-

Claims (1)

[Claims] a multiplexer that multiplexes an address that occurs first and an address that occurs later; a dynamic ram that is accessed by this multiplexed address;
A decoder that generates a signal indicating that the i-memory device has been selected, a signal indicating that the memory device has been selected, a previously generated address confirmation signal, a later generated address confirmation signal, and the memory. The memory device includes a timing controller that generates control signals for the dynamic RAM and the bus gate according to signals indicating read and write operations, and the timing controller starts accessing the dynamic RAM based on the address that is generated first regardless of the selection of the memory device. , if the memory device is not selected by the address that occurs later, stop the access,
A high-speed memory device characterized in that access continues if the memory device is selected.