JPS62250597A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent finely divided components from being destructed by constituting a voltage limiting circuit with a P-channel MOSFET of diode connection to set a clamp voltage in small steps. CONSTITUTION:A clamp level of an output voltage of a voltage limit circuit is decided by the threshold voltage of a P-channel MOSFETQ1 of diode connection. Since a substrate gate of the P-channel MOSFETQ1 is connected in common to a source having a voltage higher than the gate potential at the on-state, the threshold voltage Vthp of the P-channel MOSFET is a comparatively small value and a boosting voltage Vpp' is selected by a comparatively small voltage step. In order to switch the voltage of output terminals Vcc/Vpp' depending on the operation mode, a P-channel switch MOSFETQ8 is provided between the output terminal Vcc/Vpp' and a low-voltage power supply Vcc. In turning on/off the MOSFETQ8 in response to the operating mode of an EPROM, a control voltage formed by the next level conversion circuit is supplied to the gate.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device. (Memory cell) mpRoM (erasable & programmable read-only memory) etc.

[Conventional technology]

EP that uses semiconductor elements like FAMO3 as memory cells
Regarding ROM, for example, Japanese Patent Application Laid-Open No. 54-152933
The method is described in the No. 3 publication, etc., and is publicly known. I like this
F, P ROM is provided with a booster circuit to generate a relatively high internal power supply voltage required for writing and erasing memory cells, and a voltage limiting circuit is provided to clamp the voltage to a desired voltage. It will be done.

[Problem that the invention seeks to solve]

FIG. 3 shows an EPROM booster circuit and an output voltage limiting circuit developed by the inventors of the present invention prior to the present invention. One electrode of the bootstrap capacitor CB is periodically supplied with the power supply voltage VC from the oscillation circuit O8C.
A high level pulse signal such as C is supplied. The other electrode of the bootstrap capacitor CB is EPRO
In the write operation mode of M, the high power supply voltage Vpρ-V
th (vth is the threshold voltage of the N-channel N40SFET), so when the pulse signal supplied from the 11 oscillation circuit osc becomes high level, the potential is (Vpp - V th) + Vcc. Moreover, the voltage becomes even higher. This voltage is clamped to a voltage such as Vpp+21/th by a voltage limiting circuit consisting of MOS FET 0218 and Q30 in diode form, and further
By passing through F E TQ31, Vpp+Vth
A desired high ``!!R voltage Vpl)'' is obtained.

The inventors of the present invention have discovered that such a voltage limiting circuit has the following problems. In other words, N
In a channel MOSFET, since the ground potential of the circuit is supplied to its substrate gate, it is affected by the substrate bias effect, so its threshold voltage vth is approximately 2.5.
The threshold voltage has a relatively large value as shown in (2), and the fluctuations in the threshold voltage due to process variations are also large. For this reason, a desired high power supply voltage cannot be obtained with small voltage steps, and the boosted voltage also fluctuates greatly. This not only deteriorates the writing characteristics of EFROM, but also causes damage to the device as the manufacturing technology of semiconductor integrated circuits improves, the degree of integration increases and the device becomes finer. .

An object of the present invention is to provide a semiconductor integrated circuit device including a voltage limiting circuit that allows highly accurate voltage setting.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the voltage limiting circuit is constituted by a P-channel MOSFET in the form of a diode.

[For production]

According to the above-mentioned means, the P-nayan channel MO is less affected by the substrate bias effect and has a relatively small threshold voltage.
By configuring a voltage limiting circuit using SFET', it is possible to set the clamp voltage in small steps, and it is possible to realize a semiconductor integrated circuit device such as F, PROM, etc. with stable write characteristics and high reliability.

〔Example〕

FIG. 2 shows a circuit diagram of an example of an E F ROM memory array and its peripheral circuits to which the present invention is applied. Although not particularly limited, each circuit element in the figure is formed on a single semiconductor substrate such as single crystal P-type silicon by a known C1vics (complementary MO3) integrated circuit manufacturing technique. N channel M OS
FET is a source region, a drain region formed on the surface of such a semiconductor substrate, and a polysilicon film formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. It consists of a gate electrode consisting of: P channel MOS FET is
It is formed in an N-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes the substrate gate of the P-channel MOSFET formed thereon.

Although not particularly limited, in the EPROM of this embodiment, complementary address signals formed by an address buffer receiving X and Y address signals supplied from external terminals (not shown) are supplied to the address decoder DCR. In the figure, an address buffer and an address decoder are shown as the same circuit blocks XADB-OCR and YADB-OCR, respectively.

Address buffers XADB and YADB are activated by an internal chip selection signal ce, take in an address signal supplied via an external terminal, and receive an internal address signal in phase with their external address signal and an internal address signal in opposite phase. A complementary internal +dress signal is formed.

Address decoder XDCR decodes the X-system complementary internal address signal to form a word line selection signal of memory array M-ARY.

Address decoder YI3CR decodes the Y-system complementary internal address signal to form a selection signal for the data line of memory array M-ARY.

A memory array (M-ARY is a plurality of FAMO5 shown as a representative) transistors (non-volatile memory elements...MOS F'ET Q14 to Q19), word lines W1. W2 and data lines D1 to Dn. In memory array M-ARY, FAMO3I-transistors Q14. Q
16. Q10 (or Q15. Q17. Q1
The control gates of FAMO3) transistors Q14.9) are connected to the respective word lines W1 (or W2), and are arranged in the same column. Q15~Q1
8. The drains of Q19 are connected to corresponding data lines D1 to Dn, respectively. Although the common source line C8 of the FAMos+- transistors is not particularly limited,
Internal control signal to that gate? It is grounded via a depletion type MO5FET Q23 which receives τ. The conductance of this MOSFET Q23 is made relatively small by the internal control signal τ which is set to a low level in the write operation mode of the EFROM. As a result, the potential of the common source line CS is set to a relatively high potential. By making the potential of the common source line C3 relatively high, the threshold voltage of the FAMO transistor 5) is made relatively high. Therefore, even if a high write voltage is supplied to the data line, the effective threshold voltage of the FAMO transistor 5) connected to the non-selected word line is increased, so that the resulting leakage current can be reduced. This allows the write @ current supplied from the external terminal only to the selected FAMOS transistor! shared,
Efficient write operations can be performed. In addition, EP
In the ROM read operation mode, 1, the above internal control signal; τ is set to high level, so MOSFETQ
The conductance of 23 is made relatively large. Thereby, the read speed can be increased.

Each of the data lines D1 to Dn has a column selection switch MOSFET Q20 to Q20 which receives a data line selection signal formed by an address decoder YDCR at its gate.
It is connected to the common data line CD via Q22. The common data line CD is connected to an output terminal of a data buffer DIB that receives write data input from an external terminal I10, and is also provided with a first stage increase circuit of a sense amplifier SA.

That is, the common data line CD is connected to the source of the N-channel type amplification MOSFET Q27.

The drain of this amplification MO5FETQ27 and the power supply voltage Vc
There is a negative p-channel type between c and c? tJMO5FE
T Q26 is provided. Above load MOSFET Q26
supplies the precharge current of the common data line CD necessary for the read operation. Above amplification MOSFETQ2
In order to increase the sensitivity of 7, the voltage of the common data line CD is
It is supplied to the gate of a drive MO5FETQ25, which is an input of an inverting amplifier circuit consisting of an N-channel type drive MOSFETQ25 and a P-channel type load MOSFETQ24. The output voltage of this inverting amplifier circuit is
It is supplied to the gate of SFETQ27. Furthermore, in order to prevent wasteful current consumption during the non-operation period of the sense amplifier, an N-channel MO5FETQ2 is provided between the gate of the amplification MO5FETQ27 and the ground potential point of the circuit. A timing signal sc for operating the sense amplifier is supplied to the gates of this MOSFETQ28 and the P-channel MO5FETQ24. When reading a memory cell, the sense amplifier operation timing signal SC is set to a low level, MOSFETQ24 is turned on, and MOSFETQ2B is turned off.

The memory cells selected by address decoders XDCR and YDCR are made to have a threshold voltage higher or lower than the selection level of the word line according to write data.

If the selected memory cell has a threshold voltage higher than the selection level of the word line, that memory cell will be in the off state even in the selected state, so the potential of the common data line CD will be lower than the current supplied from MOSFETs Q26 and Q27. It is considered to be at a relatively high level. On the other hand, if the selected memory cell has a threshold voltage lower than the selection level of the word line, that memory cell is in the on state in the selected state, so the potential of the common data line CD is set to a relatively low level. .

The high level of the common data line CD in the read operation is caused by the relatively low level output voltage formed by the inverting amplifier circuit that receives this high level potential.
27, it is limited to a relatively low potential. On the other hand, the low level of the common data line CD is a relatively high level voltage formed by an inverting amplifier circuit that receives this low level potential.
7, it is limited to a relatively high potential. By limiting the high level and low level of the common data line CD in this way, it is possible to speed up the read operation despite the presence of stray capacitance etc. that limit the signal change speed in the common data line CD etc. can.

That is, when data is read out one after another from a plurality of memory cells, the time required for the level of the common data line CD to change can be shortened. For such a high-speed read operation, the conductance of the load MOSFET Q26 is set relatively large.

The amplifying MOSFET Q27 operates as a gate-grounded source input type amplifying circuit, and its output signal is transmitted to the sense amplifier SA constituted by a CMOS inverter circuit. The output signal of this sense amplifier SA is sent out from the external terminal I10 via the data output sofa DOB.

The timing control circuit C0NT receives a chimbu enable signal GE, an output enable signal δ, a program signal PGM, and a high voltage VP for writing, which are supplied from the outside.
fl, the various internal control signals co, ma τ, sc
Or an address decoder.

Low voltage for reading/high voltage for writing selectively supplied to data buffer DIB, etc. (Vcc/VPI)'
form etc. For example, if the chip enable signal 100 is at a low level, the output enable signal OE is at a high level, and the program signal Στ is at a low level, the write mode is set, the internal control signal i is at a low level, and ce is at a high level. In addition, address decoder circuits XDCR, YDCR and data manual buffer DI
B has a high voltage Vpp” boosted as its operating voltage.
is supplied.

Chip enable signal δ1- is low level, output enable signal σ10 is low level, program signal P
When GM is at a high level and the high voltage terminal vpp is at a high voltage for writing, the verify mode is set, and the internal control signals 1τ and co are both set at a high level. Further, the address decoder circuits XDCR, YDCR and the data manual buffer DIB are supplied with a relatively low power supply voltage Vcc as their operating voltage.

Furthermore, the chimbu enable signal σ is at a low level, the output enable signal is at a low level, the program signal PGM is at a high level, and vpp is a low voltage for reading (
If it is the same level as Vcc), the read mode is set, and the internal control signal 71 and ce are both set to high level.

FIG. 1 shows a high voltage generation circuit HVG including a voltage limiting circuit, a booster circuit, and a voltage switching circuit for the operating voltage Vcc/VPg)' to which the present invention is applied, and a word line selection circuit of a memory array M-ARY. A circuit diagram of one embodiment is shown.

The high voltage supplied from the high voltage terminal vpp is supplied to one electrode of the bootstrap capacitor CB via the N-channel switch MOSFET Q3. The other electrode of the putot clamp capacitor CB is provided with a periodic pulse signal formed by the oscillation circuit O3C, which sets the relatively low power supply voltage VCC to a high level and sets the ground potential of the circuit to a low level, although this is not particularly limited. Supplied. The switch MOSFET Q3 is turned on in the EPROM (7) write mode when an internal control signal WE' set to the same level as the high voltage vpp is supplied to its gate. This internal control signal WE'' is formed by a circuit similar to the level conversion circuit described later.MO
When SFETQ3 is turned on and the output signal of the oscillation circuit O8C is at a low level, the bootstrap capacitance CB becomes the voltage Vpp-Vth (Vth is MO5FET
Q3 threshold voltage). and,
When the output signal of the oscillation circuit O8C changes from low level to high level, due to the charge pump action of the Pootstrap capacitor CB, one electrode that is used as the output terminal has a
A boosted voltage such as (Vpp - Vth) + Vcc (7) is obtained. Note that at this time, the MO5FET Q3 has a high voltage vp whose internal control signal WE' is lower than this boosted voltage.
Since the potential is set to p, it is in an off state.

A voltage limiting circuit consisting of a diode-shaped P-channel MOSFET Q1 and an N-channel MOSFET Q2 is provided between one electrode serving as the output terminal of the Pootstrap capacitor IcB and the high power supply voltage vpp. The substrate gates of the P-channel MOSFET QI are commonly connected to their sources in order to make the potential of the substrate gate higher than the gate potential in the on state. These MOSFETs QI and Q2 have the above boosted voltage of Vpp+V.
thp +Vth (Vthp is P channel + 7 channel MO8F
ETQI threshold voltage, vth is N-channel MOS
When the voltage is increased to a value higher than the threshold voltage of FETQ2, the transistor turns on, so that the boosted voltage is level-clamped to the above voltage.

This boosted voltage is applied to a backflow prevention N in the form of a diode.
Channel MOSFETQ4 further increases Vth(
The threshold voltage of the N-channel MO8FET Q4 decreases and is transmitted to the voltage switching output terminal Vcc/Vpp'. As a result, in the case of a write mode to be described later, a voltage vpp' boosted from the high voltage Vl)P, such as vpp+vthp, is output to the output terminal Vcc/Vpp'.

In the voltage limiting circuit of this embodiment, the clamp level of its output voltage is determined by the threshold voltage of the P-channel MOSFET QI, which is in the form of a diode as described above. Since the substrate gates of the P-channel MO5FETQ 1 are commonly connected to the sources, which have a voltage higher than the gate potential in their on state, the threshold voltage v th of such a P-channel MO5FE'T''
p has a relatively small value, such as 0.5. Therefore, the boosted voltage VPP'' can be selected in relatively small voltage steps.

In order to switch the voltage of this output terminal Vcc/Vpp' according to the operation mode, a P-channel type switch MO is connected between the output terminal Vcc/Vpp' and the low power supply voltage Vcc.
SFETQa is provided. This MOSFETQ8 is
In order to turn it on/off depending on the operating mode of the PROM, its gate is supplied with a control voltage formed by the next level conversion circuit.

That is, the internal control signal we is transmitted to the output terminal Vcc/Vp via an N-channel cut MOSFET Q5 whose gate is constantly supplied with the low power supply voltage Vcc.
P-channel MOSFE whose operating voltage is the voltage of P'
It is supplied to the input terminal of a CMOS inverter circuit consisting of TQ7 and N-channel MO3FETQll. The output signal of this CMOS inverter circuit is transmitted to the gate 1- of the switch MOSFET Q8 on the one hand;
On the other hand, the input terminal and the output terminal Vcc/Vp
P-channel MOS F E provided between ρ°
Supplied to the gate of TQ6.

In the write operation mode of EPROM, the high voltage terminal V
A high voltage for writing is supplied to l) l), and the switch MOSFE is turned on by the high level of the internal control signal WE'.
TQ3 is turned on and the boosting operation as described above is started. When the internal control signal we for specifying the write mode is set to low level, a low level such as the ground potential of the circuit is supplied to the input of the CMOS inverter circuit via MOSFET Q5.
5FETQII is off and P channel MOSF
ETQ7 is turned on. As a result, the output signal becomes the boosted voltage Vpp according to the output terminal Vcc/Vpp'.
' (Vpp+Vthp), so the P-channel MOSFET Q8 is turned off. therefore,
Unit circuit UXD that constitutes the X address decoder described later
The boosted voltage vpp'' (Vpp+Vthρ) is supplied to the Y address decoder YDCR and the data cover sofa DIB shown in CR and 11m.

Next, when the EPROM enters the verify mode and the internal control signal; 1- is set to high level, MOSFETQ5
Since a high level such as the low power supply voltage Vcc of the circuit is supplied to the input of the CMOS inverter circuit through the inverter, the N-channel MOSFET Q11 is turned on. At this time, P-channel MO5FETQ7, which receives a high level such as the above-mentioned low power supply voltage Vcc at its gate, also maintains the on state, so its output level is equal to that of MOSFETQ7.
It is set to a relatively high low level according to the conductance ratio of 7 and Qll. However, since the P-channel MOSFETQ6 is turned on by this low-level signal, the gate of the P-channel MOSFETQ7 is
The sources are shorted. By this, P channel M
The OS FETQ7 is completely turned off, and the P-channel MO5FETQB is turned on when a low level, such as the ground potential of the circuit, is supplied to its gate.

Due to the ON state of this MOSFETQ8, the output terminal V
cc/Vps)" is set to a level equal to the low power supply voltage Vcc, and is applied to a unit circuit UXDCR constituting an X address decoder, which will be described later, and a Y address decoder YD shown in FIG.
A low power supply voltage Vcc is supplied to CR and data input buffer DIB.

Unit circuit UXDC that constitutes address decoder XDCR
R is constituted by, for example, a NAND gate circuit G1 receiving internal address signals axQ, axi and an internal control signal ce. The output signal of this Nant gate circuit G1 is sent to the input terminal of a CMOS inverter circuit consisting of a P-channel MOSFET Q10 and an N-channel MOSFET Q13 via an N-channel type C1-M05FET Q12 whose gate is constantly supplied with the power supply voltage Vcc. Supplied. A P-channel MOSFET Q9 is provided between the input terminal of the CMOS inverter circuit and its operating voltage terminal Vcc/Vpp'.

The gate of this MOSFETQ9 is the output terminal of the CMOS inverter circuit, in other words, the word line W1
is combined with High voltage Vl from the voltage switching circuit
) P” is sent out, if the output signal of the Nant gate circuit G1 is low level, the P channel MOSFET
QIO is turned on and the word line W1 is set to high voltage VPI.
)' selection level. This selection level turns P-channel MOSFET Q9 off.

On the other hand, if the output signal of the Nant gate circuit Gl is at a high level, the N-channel MOS FET Q13 is turned on, and the word line W1 is set at a low level like the ground potential of the circuit. In response to the low level of the word line W1, the P-channel MOSFET Q9 is turned on, and the input terminal of the CMOS inverter circuit is at a high voltage vpp''.
P-channel MOS
FETQIO is turned off. Further, by setting the input terminal of the CMOS inverter circuit to the high level as described above, the N-channel MOSFET Q12 is turned off. As a result, the level converter circuit can prevent direct current from flowing from the high voltage Vl)p' toward the power supply voltage Vcc of the Nant gate circuit G1 by an operation of 0 or more. It is possible to convert a decoded output signal consisting of a low level to a relatively high level such as a high voltage vpp'.

As shown in the above embodiment, when the present invention is applied to a semiconductor integrated circuit device such as an EPROM having an internal booster circuit and a voltage limiting circuit, the following effects can be obtained.

That is, (1) By using a P-channel MOS FET as a diode, which is less affected by the substrate bias effect and has a relatively small threshold voltage, and configuring a voltage limiting circuit such as an internal boosted voltage, the clamp voltage can be reduced. This has the effect of being able to be set in small increments.

(2) Due to item (1) above, it is possible to generate a stable high voltage that is relatively resistant to deterioration due to process variations, and it has stable write characteristics and other operating characteristics.
The effect of realizing a semiconductor integrated circuit device such as FROM can be obtained.

(3) Due to item (1) above, the desired voltage can be obtained without increasing the boosted high power supply voltage unnecessarily, which reduces the risk of destroying elements that have been miniaturized due to high integration. Therefore, it is possible to realize a highly reliable semiconductor integrated circuit device such as an EPROM.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it is possible to make various changes without departing from the gist of the invention. Not even. For example, the memory cell is not a FAMO3 element, but may be of any type as long as it has a floating gate and information is written into the floating gate by hot carrier injection or tunnel injection. In addition, in the voltage limiting circuit shown in FIG. 1, the clamp voltage of the boosted voltage is determined by the threshold voltage of one P-channel MOS FETQl, but depending on the desired boosted voltage, multiple P-channel MOS MOS FET or N-channel MOSFE
T may be used in combination. Further, in FIG. 1, the drain of the P-channel MO5FET QI is coupled to the high power supply voltage Vl)P, but it may be coupled to the power supply voltage Vcc, for example, depending on the voltage generated. Furthermore, the configuration of the booster circuit may take various embodiments, and the voltage switching circuit may not be provided.

In the above explanation, the invention made by the inventor of the present application was mainly explained in the case where it was applied to the voltage limiting circuit of EPRO-1, which is the background technical field, but it is not limited to this, and for example, EEPROM, etc. The present invention can also be applied to various other semiconductor integrated circuit devices having a built-in booster circuit.

The present invention is applicable to a semiconductor integrated circuit device having at least an internal booster circuit and a voltage limiting circuit for its output voltage.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, it is a P-channel MO5FET with less influence Δ of the substrate bias effect and a relatively small threshold voltage.
By using a diode in the form of a voltage limiting circuit such as an internal boosted voltage, the clamp voltage can be set in small steps. EFRO has stable operating characteristics and is highly reliable because it can generate a stable high voltage that is less susceptible to fluctuations due to
It is possible to realize a semiconductor integrated circuit device such as M.

[Brief explanation of drawings]

1 is a circuit diagram showing an embodiment of a voltage limiting circuit of an EFROM device to which the present invention is applied; FIG. 2 is a block diagram showing an embodiment of an EPROM including the voltage limiting circuit of FIG. 1; FIG. 3 is a circuit diagram of a voltage limiting circuit developed by the inventors of the present invention prior to the present invention. ■IVG...High voltage generation circuit, OSC...Oscillation circuit, U X D CR...Unit circuit, CB...8 bootstrap ports, Ql, Q6~QiO, Q24゜Q26・
・・P channel 2/channel MOSFET, Q2~Q5, Q1
1~Q13. Q20-Q22. Q25. Q27.
Q28Q30. Q31...N channel MOS
FET, Gl...Nandday 1 circuit.

Claims (1)

[Claims] 1. A booster circuit for generating a relatively high internal power supply voltage using an externally supplied power supply voltage, and a diode-connected booster circuit provided between the output terminal of this booster circuit and a reference voltage. 1. A semiconductor integrated circuit device comprising: a voltage limiting circuit including a P-channel MOSFET. 2. The semiconductor integrated circuit device is an EPROM device,
2. A semiconductor integrated circuit device according to claim 1, wherein said booster circuit is for generating a high power supply voltage used for writing or erasing a memory cell of said EPROM device.