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JPS6224950B2 - - Google Patents

Info

Publication number
JPS6224950B2
JPS6224950B2 JP18477981A JP18477981A JPS6224950B2 JP S6224950 B2 JPS6224950 B2 JP S6224950B2 JP 18477981 A JP18477981 A JP 18477981A JP 18477981 A JP18477981 A JP 18477981A JP S6224950 B2 JPS6224950 B2 JP S6224950B2
Authority
JP
Japan
Prior art keywords
metal wiring
wiring
protection element
current path
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP18477981A
Other languages
Japanese (ja)
Other versions
JPS5886756A (en
Inventor
Kenji Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP18477981A priority Critical patent/JPS5886756A/en
Publication of JPS5886756A publication Critical patent/JPS5886756A/en
Publication of JPS6224950B2 publication Critical patent/JPS6224950B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は、半導体装置に係り、特に集積回路
(IC)の静電破壊防止策に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and particularly to measures to prevent electrostatic damage in integrated circuits (ICs).

静電気によるICの破壊とは、ICの周囲のも
の、例えばICのチツプ実装工程中の治具、搬送
用キヤリア、検査治具及び人体等に帯電した静電
気がICと接近又は接触したICの端子間を通して
放電し、内部素子を破壊に至らしめる現象であ
る。IC、LSI(大規模集積回路)の発展には目を
見張るものがありトランジスタの発明以来わずか
30年の間に、民生用、産業用のあらゆる分野に急
速に普及しつづけて来た。この普及の大きな理由
の1つにIC化が電子機器、システムに実装され
る部品点数あるいは接続端子数の削減等をもたら
し、機器、システムの信頼性を大幅に向上させる
事に寄与した事が挙げられる。一方IC化により
機器、システムの信頼性はICの信頼性に大きく
依存する様になり、ICの信頼性向上への要求は
ますます厳しいものになつてきつつある。ICの
故障メカニズムには、例えば湿気の侵入による劣
化、ワイヤ接続部での断線、あるいは拡散プロセ
スでの欠陥に基づくリーク電流の増大等の色々の
問題があるが、ICメーカーの努力により多くの
ものは実用上ほとんど問題の無いレベルにまで解
決されて来ている。
Destruction of an IC due to static electricity means that static electricity charged on things around the IC, such as jigs during the IC chip mounting process, carriers for transportation, inspection jigs, or the human body, may approach or come in contact with the IC between the terminals of the IC. This is a phenomenon that causes a discharge to occur through the battery, leading to destruction of internal elements. The development of ICs and LSIs (Large-Scale Integrated Circuits) has been remarkable, with only a few advances since the invention of the transistor.
Over the past 30 years, it has continued to rapidly spread across all consumer and industrial fields. One of the major reasons for this widespread use is that the introduction of ICs has reduced the number of components and connection terminals installed in electronic devices and systems, contributing to a significant improvement in the reliability of devices and systems. It will be done. On the other hand, with the introduction of ICs, the reliability of devices and systems has come to greatly depend on the reliability of the ICs, and the demands for improving the reliability of ICs are becoming increasingly severe. There are various failure mechanisms for ICs, such as deterioration due to moisture intrusion, disconnection at wire connections, and increased leakage current due to defects in the diffusion process, but thanks to the efforts of IC manufacturers, many problems can be solved. has been solved to a level where there are almost no practical problems.

その中の大きな問題の1つに静電気による破壊
がある。静電気による破壊がクローズアツプされ
て来た背景には2つの事が起因している。1つは
LSIの高集積化が進んで来た事である。必然的に
高密度化が要求され、LSIのパターンは極めて微
細化されて来た。この傾向は静電気による破壊と
いう見地からみれば、必ずしも好ましい事ではな
い。もう1つはICの使用環境の多様化がある。
あらゆる分野へICが使われはじめた事、とりわ
け携帯用電子機器への導入が促進された事と身の
まわりに石油化学製品が増大した事により、静電
気とICがかかわりあう機会が著しく増大した事
である。
One of the major problems is damage caused by static electricity. There are two reasons why damage caused by static electricity has become a focus of attention. One is
This is because LSIs have become more highly integrated. Inevitably, higher density is required, and LSI patterns have become extremely fine. This tendency is not necessarily desirable from the standpoint of damage caused by static electricity. Another reason is the diversification of the environments in which ICs are used.
As ICs have begun to be used in all fields, especially in portable electronic devices, and petrochemical products have increased in our daily lives, the opportunities for static electricity to interact with ICs have increased significantly. It is.

この静電気によるICの破壊を防止する為に、
特公昭43―455に示されるようなダイオードや、
MOSFETやパンチスルー素子等を用いた各種の
保護素子が考えられており静電気に対してかなり
強いICが得られている。しかし、ICの集積度や
性能を良くする為に前記の様に入出力配線の微細
化をしてくると、保護素子そのものは、静電気の
エネルギーに対して十分強い構造であつても入力
配線そのものが、静電気のエネルギーで溶解し入
力端子がオープンになるという欠点を有する様に
なつてきた。
In order to prevent the IC from being destroyed by this static electricity,
Diodes as shown in Special Publication No. 43-455,
Various protection elements using MOSFETs, punch-through elements, etc. have been considered, and ICs that are quite resistant to static electricity have been obtained. However, as the input/output wiring becomes finer as described above in order to improve the degree of integration and performance of ICs, even if the protection element itself has a structure that is sufficiently strong against electrostatic energy, the input wiring itself However, it has come to have the disadvantage that it melts due to static electricity energy and the input terminal becomes open.

本発明の目的は、装置の集積度や性能をそこな
わないで静電気による破壊が起りにくく、品質の
良いICを提供することにある。
An object of the present invention is to provide a high-quality IC that is less likely to be damaged by static electricity without impairing the degree of integration or performance of the device.

本発明は、入出力端子用ボンデイングパツドと
入出力用素子を結ぶ金属配線のうち、該ボンデイ
ングパツドと静電破壊保護素子間の配線幅が、残
りの入出力配線幅より太いことを特徴としてい
る。
The present invention is characterized in that among the metal wiring connecting the input/output terminal bonding pad and the input/output element, the wiring width between the bonding pad and the electrostatic discharge protection element is thicker than the remaining input/output wiring width. It is said that

以下、本発明について図面を参照しながら詳細
に説明する。
Hereinafter, the present invention will be explained in detail with reference to the drawings.

第1図は従来より一般的に使用されている静電
破壊保護素子を用いた装置の平面図で、入力配線
は入出力端子用ボンデイングパツド1からAl等
の金属配線3,4を経て内部回路領域8に接続さ
れている。又入力配線はその途中から静電破壊保
護素子2に入力し、保護素子2は配線6を経て、
装置の電源供給パツド5に接続されている。保護
素子2としては、ダイオードやMOSFETやパン
チスルー素子等の周知の各種のものを用いること
ができる。図面で7はチツプのエツヂを示す。本
構造に於て、入力端子に放電した電荷は、パツド
1に入り、配線3を経由して、保護素子2に吸収
され最終的に配線6、パツド5を経て装置の電源
に吸収される。このとき装置の内部領域8に放電
された電荷の一部が流れるがこの量は非常に少な
く装置の破壊には到らない。しかるに、第1図で
は、装置の性能等を考慮して入力配線3,4は非
常に細く設計してあり、しかも同じ幅である。こ
の為本装置は、保護素子2そのものは、静電気に
対して強い構造にもかかわらず、電荷の放電経路
である配線3が電荷が流れる時に発生するジユー
ル熱によつて溶解し断線することが、時々生じ、
装置の入力がオープン状態になることがあつた。
一般に保護素子2がない時には、内部回路8内の
入力素子がシヨートする故障が多かつたが、保護
素子2を入れた為に、オープン不良が新しく問題
となつた。
Figure 1 is a plan view of a device using an electrostatic discharge protection element that has been commonly used. It is connected to the circuit area 8. In addition, the input wiring is input to the electrostatic damage protection element 2 from the middle, and the protection element 2 passes through the wiring 6,
It is connected to the power supply pad 5 of the device. As the protection element 2, various known elements such as a diode, MOSFET, punch-through element, etc. can be used. In the drawing, 7 indicates the edge of the chip. In this structure, the charge discharged to the input terminal enters the pad 1, passes through the wiring 3, is absorbed by the protection element 2, and is finally absorbed by the power supply of the device through the wiring 6 and the pad 5. At this time, a part of the discharged charge flows into the internal region 8 of the device, but this amount is very small and does not destroy the device. However, in FIG. 1, the input wirings 3 and 4 are designed to be very thin considering the performance of the device, and have the same width. Therefore, in this device, although the protective element 2 itself has a structure that is strong against static electricity, the wiring 3, which is the discharge path of the electric charge, can be melted and disconnected by the Joule heat generated when the electric charge flows. Occasionally,
There were times when the input of the device became open.
Generally, when there was no protection element 2, there were many failures such as shorting of input elements in the internal circuit 8, but since the protection element 2 was included, open failures became a new problem.

第2図は、本発明の好ましい実施例を示す平面
図であり、第1図と異なる点は、入力配線のうち
入力パツド1′から保護素子2′に到る配線3′
と、保護素子2′から電源パツド5′に到る配線
6′が、内部回路領域8′に到る入力配線4′より
幅が太くなつている点である。本発明実施例の構
造において、配線3′,6′の幅は電荷放電によつ
て生ずるジユール熱に十分耐えられるように12μ
m以上がとつてあり、本装置は、静電気によるオ
ープン不良がなくなつた。
FIG. 2 is a plan view showing a preferred embodiment of the present invention. The difference from FIG. 1 is that the wiring 3' from the input pad 1' to the protection element 2' is
Another point is that the wiring 6' extending from the protection element 2' to the power supply pad 5' is wider than the input wiring 4' extending to the internal circuit area 8'. In the structure of the embodiment of the present invention, the width of the wirings 3' and 6' is 12 μm so as to be able to sufficiently withstand the Joule heat generated by charge discharge.
m or more, and this device has no open defects caused by static electricity.

本発明実施例の重要な点は、装置の高密度化、
高性能化に対して最近要求されている配線パター
ンのフアイン化をそこなわない様に、保護素子を
ボンデイングパツド1′にすぐそばに置き、入力
配線が保護素子2′に入力した後は、要求される
細い配線幅にしてある点である。
The important points of the embodiments of the present invention are the high density of the device,
In order not to damage the finer wiring pattern that is recently required for higher performance, the protective element is placed close to the bonding pad 1', and after the input wiring is input to the protective element 2', The point is that the required narrow wiring width has been achieved.

以上、本発明について、実施例を用いて説明し
たように本発明の構成を用いれば、装置の集積
度、性能をそこなわないで、静電気に対して高い
品質を有する半導体装置が得られる。
As described above using the embodiments of the present invention, if the configuration of the present invention is used, a semiconductor device having high quality against static electricity can be obtained without impairing the degree of integration or performance of the device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の静電破壊保護素子を有する装
置の平面図、第2図は、本発明の好ましい実施例
を示す平面図である。 なお図において、1……入出力端子用ボンデイ
ングパツド、2……静電破壊保護素子、3,4,
6……内部配線、5……電源端子用ボンデイング
パツド、7……チツプエツヂ、8……内部回路領
域、である。
FIG. 1 is a plan view of a device having a conventional electrostatic discharge protection element, and FIG. 2 is a plan view showing a preferred embodiment of the present invention. In the figure, 1...bonding pad for input/output terminals, 2...electrostatic damage protection element, 3, 4,
6... Internal wiring, 5... Bonding pad for power supply terminal, 7... Chip edge, 8... Internal circuit area.

Claims (1)

【特許請求の範囲】 1 複数の入出力端子用ボンデイングパツドと、
該入出力端子用ボンデイングパツドに第1の金属
配線を介して接続された回路領域と、該回路素子
領域に与える電源電位を外部から受ける電源電極
と、前記第1の金属配線の所定のものに第2の金
属配線を介して接続された前記回路領域を静電破
壊から防止する保護素子と、該保護素子と前記電
源電極との間の電流通路とを含み、前記第1の金
属配線および前記第2の金属配線のうち前記入出
力端子用ボンデイングパツドと前記保護素子との
間の電流経路となる部分の配線巾を他の部分より
太くしかつ前記保護素子と前記電源電極との間の
電流通路の電流容量を大きくしたことを特徴とす
る半導体装置。 2 前記第1および第2の金属配線のうち前記電
流経路となる部分は12μm以上の配線巾を有する
ことを特徴とする特許請求の範囲第1項記載の半
導体装置。 3 前記保護素子と前記電源電極との間の電流通
路は第3の金属配線であり、該第3の金属配線は
前記第1の金属配線のうち前記電流経路となる部
分以外の部分より太くなつていることを特徴とす
る特許請求の範囲第1項記載の半導体装置。 4 前記第3の金属配線と前記第1および第2の
金属配線のうち前記電流経路となる部分とは12μ
m以上の配線巾を有することを特徴とする特許請
求の範囲第3項記載の半導体装置。
[Claims] 1. Bonding pads for a plurality of input/output terminals;
A circuit area connected to the input/output terminal bonding pad via a first metal wiring, a power supply electrode that receives a power supply potential applied to the circuit element area from the outside, and a predetermined one of the first metal wiring. a protection element that prevents the circuit area connected to the circuit area via a second metal wiring from being damaged by electrostatic discharge, and a current path between the protection element and the power supply electrode, the first metal wiring and The wiring width of a portion of the second metal wiring that serves as a current path between the input/output terminal bonding pad and the protection element is made wider than other portions, and between the protection element and the power supply electrode. A semiconductor device characterized in that the current capacity of the current path is increased. 2. The semiconductor device according to claim 1, wherein a portion of the first and second metal wiring that becomes the current path has a wiring width of 12 μm or more. 3. The current path between the protection element and the power supply electrode is a third metal wiring, and the third metal wiring is thicker than a portion of the first metal wiring other than the portion that becomes the current path. A semiconductor device according to claim 1, characterized in that: 4. The distance between the third metal wiring and the portion of the first and second metal wiring that becomes the current path is 12μ.
4. The semiconductor device according to claim 3, having a wiring width of m or more.
JP18477981A 1981-11-18 1981-11-18 Semiconductor device Granted JPS5886756A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18477981A JPS5886756A (en) 1981-11-18 1981-11-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18477981A JPS5886756A (en) 1981-11-18 1981-11-18 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5886756A JPS5886756A (en) 1983-05-24
JPS6224950B2 true JPS6224950B2 (en) 1987-05-30

Family

ID=16159152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18477981A Granted JPS5886756A (en) 1981-11-18 1981-11-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5886756A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01210048A (en) * 1988-02-18 1989-08-23 Matsushita Electric Ind Co Ltd Dust collecting electrode

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0373564A (en) * 1989-08-14 1991-03-28 Nec Corp Semiconductor device
JP4904619B2 (en) * 2000-11-29 2012-03-28 富士通セミコンダクター株式会社 Semiconductor device
US6727533B2 (en) 2000-11-29 2004-04-27 Fujitsu Limited Semiconductor apparatus having a large-size bus connection
JP2010135391A (en) * 2008-12-02 2010-06-17 Seiko Epson Corp Semiconductor device and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01210048A (en) * 1988-02-18 1989-08-23 Matsushita Electric Ind Co Ltd Dust collecting electrode

Also Published As

Publication number Publication date
JPS5886756A (en) 1983-05-24

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