JPS62249250A - Memory device - Google Patents

Abstract

PURPOSE:To surely judge whether the data stored in an in-use system storage part and a standby system storage part are equal or not, by providing an arithmetic storage means at the in-use system storage part, and the standby system storage part, respectively. CONSTITUTION:By supplying an instruction to read out the data from a central processor, an in-use system storage part 300 reads out the data stored in a data storage part 320, and sends it to a CRC circuit 310, and a read error check circuit 350. Similarly, a standby system storage part 400 also sends a read data to a CRC circuit 410, and a read error check circuit 450. And the CRC circuits 310 and 410 perform a prescribed arithmetic calculation on those data, and store arithmetic results, and the read error check circuits 350 and 450 perform read error check operations. In the case, a control part 200, after completing the transfer of the data, compares the arithmetic results stored in the CRC circuits 310 and 410, and informs coincidence/no coincidence to the central processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a storage device, and more particularly to a storage device with a duplex configuration.

[Conventional technology]

2. Description of the Related Art In systems equipped with a central processing unit and a storage device, the storage devices have been duplicated in order to improve the reliability of the system. In other words, Ki+! 1
The device consists of an active storage unit and a backup storage unit, and when writing data from the central processing unit, the same data is written to both the active storage unit and the backup storage unit, and the data is written to the central processing unit. When transferring data, the data is read from both the active storage section and the backup storage section, a read error check is performed, and the following processing is performed depending on the result of the read error check. If there is no abnormality in the data read from the active storage unit, the data read from the active storage unit is transferred to the central processing unit, and if there is an abnormality in the data read from the active storage unit, the data is transferred to the active storage unit and again. Data is read from the backup storage and a read error check is performed, and if there is no abnormality in the data read from the active storage, the data read from the active storage is transferred to the central processing unit and read from the active storage. If there is an abnormality in the read data and there is no abnormality in the data read from the backup storage, the data read from the backup storage is transferred to the central processing unit.

[Problem that the invention seeks to solve]

As described above, system reliability can be improved by configuring the storage devices in a duplex manner, but there are the following problems. That is, in the conventional example described above, when data is transferred to the central processing unit, a read error check is only performed for each data read from the active storage section and the backup storage section, so There was a problem in that it was not possible to determine whether or not the same data was stored in the backup storage unit.

The present invention solves the above-mentioned problems, and its purpose is to make it possible to reliably determine whether or not the same data is stored in the active storage section and the backup storage section. .

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a storage device that is connected to a central processing unit and operates according to instructions from the central processing unit. a first data storage section that performs a predetermined operation on data read out from the first data storage section and stores the operation result;
an active system storage section comprising an arithmetic storage means; a second data storage section in which the same data as the first data storage section is stored; performs the same calculation as the first calculation storage means,
a spare system storage unit comprising a second calculation storage means for storing calculation results; and a spare system storage unit that reads data stored in the first data storage unit according to a read command from the central processing unit, and stores the calculation result in the central processing unit. At the same time, the data stored in the first and second data storage units are transferred to the first and second data storage units, respectively. The data is transferred to the second arithmetic storage means, and upon completion of reading the data, the first. The calculation results stored in the second calculation storage means are compared, and in the case of a match, the central processing unit and a control unit that notifies the central processing unit that the data stored in the active storage unit and the standby storage unit are not the same if the comparison does not match.

[For production]

The storage contents of the first arithmetic storage means provided in the active storage section and the storage contents of the second arithmetic storage means provided in the backup storage section match only when the series read from the re-storage section Since the data stored in the active storage unit and the backup storage unit are the same, it is only possible to determine whether the data stored in the active storage unit and the backup storage unit are the same. can be determined with certainty.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a semiconductor memory device 100 includes a control section 200, a CRC (Co, rre
ction code) circuit 310. Data storage section 32
0. Register 330. An active storage section 300 including an AND gate 340 and a read error check circuit 350, and a CRC circuit 410. Data storage unit 420. register 4
30. It is composed of a spare storage section 400 including an AND gate 440 and a read error check circuit 450.

Note that the CRC circuits 310 and 410 each perform an operation on the data read out from the data storage units 320 and 420 in a predetermined manner (for example, sequentially adding the read data, taking exclusive OR of the read data, etc.). and stores the calculation results. Also, the register 330 in the active storage unit 300 and the register 4 in the backup storage unit 400
It is assumed that "1" and "0" are respectively set in 30 at the time of initial setting.

The control unit 200 is connected to a signal line 2 from a central processing unit (not shown).
When a data read command is applied via 01, the active storage unit 300 and the backup storage unit 400 are simultaneously selected,
A data read instruction is applied to the active storage unit 300 and the backup storage unit 400 via signal lines 305 and 405, respectively. When a data read instruction is applied, the active storage unit 300 reads the data stored in the data storage unit 320, and transmits the read data to the CRC circuit 310 through the signal line 301. IJ - error check circuit 3
50 and the AND gate 340, the spare storage unit 40
0 reads data stored in the data storage section 420, and sends the read data to the CRC circuit 410.0 via the signal line 401. Added to read error check circuit 450 and AND gate 440. In this case, registers 330, 43
0 has the OS set to ``1''1'' as described above, and the AND gates 340 and 440 are in the on and off states, respectively, so the data in the active storage unit 300 Only the data read from the storage section 320 is passed through the AND gate 340 . It will be applied to the control unit 200 via the signal line 302.

When data is added via the signal lines 301 and 401, the CRC circuits 310 and 410 perform predetermined calculations on the data and store the calculation results, and the read error check circuits 350 and 450 perform a read error check. If a read error is detected, the signal line 303°403
The controller 200 is notified of this via the .

Note that the calculations performed by the CRC circuit 310 and the CRC circuit 410
is the same as the calculation performed by .

If the read error check circuit 350 in the active storage unit 300 does not detect a read error, the control unit 200 checks the data storage unit 320 via the AND gate 340.
The data added from the CRC circuit 3 is transferred to the central processing unit via the signal line 202, and when the data transfer is completed,
10. The calculation result stored in 410 is transferred to the signal line 304.
．． 404 and compare the two. Then, in the case of a comparison match, the control unit 200 notifies the central processing unit of the tongue whose data stored in the active storage unit 300 and the backup storage unit 400 match via the signal line 201, If the comparison does not match, the central processing unit is notified via the signal line 201 that the data stored in the active storage unit 300 and the backup storage unit 400 do not match.

Furthermore, when the central processing terminal receives a notification of comparison discrepancy,
For example, if a read error is detected by the read error check circuit 350 of the active storage unit 300, retries are performed up to a predetermined number of times, and the read error is still resolved. If not, the control unit 200 sets the register 330 to 0° and the register 4
30 is set to “1”, and the backup storage unit 40 is set to “1”.
The data read from the data storage section 420 in 0 is applied to the control section 200 via the game 1-440 and the signal &91402, and this data is used. Further, although the above-described embodiments have been explained using a semiconductor memory device as an example, it goes without saying that the present invention can also be applied to a memory device such as a core memory.

〔Effect of the invention〕

As described above, the present invention provides a first CRC circuit 310 that performs a predetermined operation on data read out from a first data storage section and stores the operation result in the active storage section.
a second arithmetic storage means which performs the same arithmetic operation as the first arithmetic storage means on the data read from the second data storage part in the spare system storage part and stores the result of the calculation; 1. The calculation results stored in the second calculation storage means match if the data read from the second data storage unit are the same.
That is, the first. Since the data stored in the second data storage section is the same, it is possible to reliably determine whether or not the same data is stored in the active storage section and the backup storage section. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention. In the figure, 100...semiconductor storage device, 200...
- Control unit, 300... Active storage unit, 400... Backup storage unit, 310.410... CRC circuit, 320
,420...Data storage section, 330.430...Register, 340,440...And gate, 350
．． 450...Read error check circuit, 201,2
02°301~306.401~406...Signal line.

Claims (1)

[Scope of Claims] In a storage device connected to a central processing unit and operated according to instructions from the central processing unit, a first data storage unit storing data and reading from the first data storage unit an active storage unit comprising a first calculation storage unit that performs a predetermined calculation on the data and stores the calculation result; and a second storage unit that stores the same data as the first data storage unit. a data storage unit; and a second calculation storage unit that performs the same calculation as the first calculation storage unit on the data read from the second data storage unit and stores the calculation result. a system storage unit, and reads data stored in the first data storage unit according to a read command from the central processing unit and transfers it to the central processing unit, and also transfers the data to the first and second data storage units. The stored data is transferred to the first and second arithmetic storage means, and upon completion of data reading, the arithmetic results stored in the first and second arithmetic storage means are compared, and it is determined whether the comparison matches. If the data stored in the active storage unit and the backup storage unit match, the central processing unit is notified that the data stored in the active storage unit and the backup storage unit match, and if the comparison does not match, the data stored in the active storage unit and the backup storage unit are notified. A storage device comprising: a control unit that notifies the central processing unit that data stored in the data are not the same.