JPS62247619A - Inverter delay circuit - Google Patents

Abstract

PURPOSE:To obtain a fixed duty ratio by controlling the position and the num ber of connection forms so that the coincidence is secured between the rise and fall delay times in case either rise or fall has larger delay time than the other owing to the connection form of inverters. CONSTITUTION:For an example of inverters of plural stages, the array of these inverters is not always direct and therefore it is impossible to neglect the effect given to the delay signals at connection areas of folded parts, etc. In other words, the effect is given only to the rise or the fall of an input signal at the connection part in case this connection part is set at the following even or odd stage counted from the first stage of inverters. In this connection, the coincidence is secured between the connection areas set at the following even and odd stages counted from the inverter of the first stage. Thus the equal effect is given to both rise and fall and therefore both rise and fall have an equal delay. Here it is desirable to prepare an even number of stages for all inverters.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a delay circuit comprising a plurality of stages of inverters connected in series, and particularly to an inverter suitable for canceling the occurrence of phase modulation in a signal to be delayed. This is related to the array ζ.

[Conventional technology]

Conventionally, in delay circuits made up of multiple stages of inverters connected in series, no consideration has been given to the effect on the signal to be delayed at points where the connection state or form of connection is different from that of the next stage. Note that related circuits of this type include, for example, Japanese Patent Laid-Open No. 56-120209.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology is a delay circuit having multiple stages of inverters, and does not take into consideration the influence on the delayed waveform at a location having a different connection state or connection form from the next stage.
There is a possibility that the influence at the connection point appears only on either the falling edge or the rising edge of the signal, resulting in a problem that the duty ratio changes.

An object of the present invention is to delay the rising edge and falling edge of a signal to be delayed equally.

[Means for solving problems]

The above purpose is to have an even number of points in a multi-stage inverter arrangement that have a connection state different from the next stage or a different connection form from the next stage, and to This is achieved by providing the same number of connection points as the number of connection points in odd-numbered stages counting from the first inverter.

[Effect]

An inverter has the function of inverting and delaying an input signal, but the delay time differs depending on the rise and fall of the input signal. Therefore, the number of inverters becomes a problem. Furthermore, the present invention is a delay using multiple stages of inverters, and in order to reduce the area on the circuit, the inverter arrangement is not necessarily straight, and there are places where the connection state and connection form are different from the next stage, for example. The influence on the delayed signal at bending parts cannot be ignored. If the above connection point exists only at the rear of even-numbered stages or after the odd-numbered stages counting from the first stage of the inverter, the input signal will fall or Only on either side of the rise,
The effect of the connection appears and causes phase modulation of the signal.

In other words, when counting from the first stage inverter, the above-mentioned connection points that exist in the after even-numbered stages and after the odd-numbered stages are equal,
It has an equal effect on the rising and falling edges of the input signal. This causes equal delays in the rise and fall of the input signal, eliminates changes in duty ratio, and prevents phase modulation from occurring. Furthermore, according to the explanation of this effect, the number of connection points must always be an even number. Considering the total number of inverters that the input signal passes through, in the case of an even number of stages, a delayed signal with a waveform equivalent to the input signal waveform is obtained, and the rising and falling edges are delayed equally, but in the case of an even number of stages, In this case, the delayed signal appears inverted with respect to the input signal, and the amount of delay differs depending on whether it rises or falls by one inverter stage. The total number of inverters is
Originally, it would be ideal to have an even number of stages, but
It can also be used with an odd number of stages.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows important parts of the inverter series connection circuit.

This is an example in which a key point is bent by 180 degrees. There are four bending points, a signal is input from the input terminal 1, and a delayed ratio signal can be taken out from the output terminal 3. 4
, 5, 6.7 are bent portions.

FIG. 2 is a schematic drawing of the inverter arrangement shown in FIG. 1 stretched out in a straight line, focusing only on the number of inverters.

The following can be understood from Figure 2. That is,
The first row includes an even number of inverters, and the bent portion 4 is located after the even numbered row. An odd number of inverters belong to the second row, and the bent portion 5 is present after the odd numbered row. Third
An odd number of inverters also belong to the rows, and a folded portion 6 exists after the even numbered rows. The fourth row also includes an odd number of inverters, and the bent portion 7 is present after the odd numbered row. The fifth column of the final stage also includes an odd number of inverters, and as a result, the total number of inverters is an even number.

The required conditions of the present invention are satisfied with the bending portions being provided at two locations after the even-numbered inverter stages and at two locations after the odd-numbered stages.

Next, the operation of this embodiment shown in FIG. 1 will be explained with reference to the time chart shown in FIG.

The time chart of FIG. 6 shows the input terminals 1 and 1 of the delay circuit shown in FIG. The change in potential level of each terminal 8.9, 10, 11.12 is shown. First, at time tx, when the potential level of input terminal 1 changes from low potential level vL to high potential level vH, at terminal 8, since it has just passed through an odd number of inverters, the signal is inverted and changes from vH after delay time TDA. Fall down to vL. Further, at time t2, the potential level of input terminal 1 changes from vH to vL, and at terminal 8 rises from vL to vH after TDi. However, TDA.

TDM is the delay time due to the total number of inverters up to terminal 8, and Toi-'roA = Δt is the difference in delay time between the rise and fall that appears only when passing through an odd number of inverter stages. Next, inverter 1 stage and bending section 4
At the terminal 9 through the terminal 8, the signal is inverted from the state at the terminal 8, and at time t1 rises from vL to VH after TDA, and falls from vH to vL after TD≦at time t2. However, Toa + 'rni is the sum of the delay amount due to all the inverters up to the terminal 9 and the delay amount due to the bending portion 4.

Further, TDg'rl)self=ΔTD4 is the difference in the amount of delay between the rise and fall caused by the bending portion.

ΔTD4, which is the problem in this case, is caused by an increase in the time constant due to an increase in the capacitance of the circuit due to bending, but there is a difference in delay time between rising and falling edges, and ΔTD4 occurs.
It appears as TD4.

FIG. 4 shows, as an example, a layout diagram of an IC when the present invention is applied to a delay circuit using a C-MOS inverter. 20 represents AA, 21 represents a diffusion layer, 22 represents polysilicon, and 23 represents a contact. VDD is a power supply line, P-MOS is in contact with VDD, and N-MOS is in contact with GND. 122 is a gate, and contacts connected to the P-MOS and N-MOS are connected to the gate of the next stage through an Al line 20.

FIG. 4 is a layout diagram of the above-mentioned folded part. Due to the folded part, the Al line 20 is connected to the inverter in the second row and the next stage, making it longer than the others and occupying a large field. I understand that.

This leads to an increase in the parasitic capacitance at the bent portion.

Returning to Figure 6 again. At the terminal 9, the duty ratio of the signal changes due to the above reason. At terminal 10, terminal 9
The delayed signal FALL passes through even-numbered stages of inverters.
TIME recovers and the rising and falling slopes return to their original values, but the difference in duty ratio remains the same. T.D.
I d and TDI g are the amount of delay at each rising and falling edge up to the terminal 10.

The terminal 11 exists via the first stage of inverter and the bending part 5, and this time, as a result of the signal which is not inverted with respect to the input signal passing through the first stage of inverter and the bending part 5, at time tl, Tolj After that, it falls from VH to vL,
At time t2, after TDI l, the voltage rises from VL to vH. TDIτ - TDII = Δt, and in this case, the difference in the amount of delay between the rise and fall at the bending part is:
They do not appear on the time chart and cancel each other out. This is because the delayed signal passes through the bent portions with different connection states twice, and one is bent after the even-numbered inverter.
The other is the result of folding after the odd-numbered row. Therefore, at terminal 11, the duty ratios become equal. FAL
The difference between the delay of LTIME and the delay time of Δ is eliminated by using an even number of inverters. Its operation is shown in the time chart at terminal 12. TDl'z and'
rDt is the delay time due to all inverters up to terminal 12 and bending, and TDI 2 = 'l Di 2. Here, the duty ratios become equal and the effects of the present invention can be obtained. The same operation as described above is repeated before and after the subsequent bending section 6.7, and the output terminal 3 shows an even number of bends and the number of inverters from the first stage before the bending is an even number and an odd number. By arranging the inverters so that the number of locations is the same, the delayed signal can be taken out without causing a change in the duty ratio.

Regarding the arrangement shown in FIG. 5 as another example,
It is clear that the invention can be applied in exactly the same way and that exactly the same effects can be obtained.

Note that the effects of the present invention are not limited to the first embodiment. For example, in the layout diagram of FIG.
Although it is connected to the next stage inverter by O, the same effect can be obtained even if the connection shape uses polysilicon, a diffusion layer, or the like.

A similar effect can be obtained with a t&N-MOS inverter.

〔Effect of the invention〕

According to the present invention, when a delay circuit comprising a plurality of stages of inverters connected in series has a different connection state and connection form from the next stage, it is possible to eliminate changes in the duty ratio before and after the delay circuit, thereby eliminating phase modulation in the delayed signal. This does not occur with output delay signals.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an inverter arrangement format according to an embodiment of the present invention, FIG. 2 is a diagram schematically showing the number of inverters up to the folded part of the ear 1, and FIG. The time chart diagram, Figure 4, showing the operating waveforms of the circuit is the layout diagram of the folded part in Figure 1, 8f! FIG. 5 is a diagram showing an inverter arrangement format according to another embodiment of the present invention. 1...Input terminal of delay circuit 2...Inverter 3...Output terminal 11 of delay circuit

Claims (1)

[Claims] 1. An inverter delay consisting of multiple stages of inverters connected in series, where the first connection point takes a normal form and the second connection place takes a special form. In the circuit, the total number of the second connection points is an even number, and the second connection point exists between an even-numbered stage inverter counting from the first stage inverter and the next stage inverter. An inverter delay circuit characterized in that the inverter delay circuit is distributed so that the number of inverters and the number existing between an odd-numbered inverter and the next inverter counting from the first inverter are equal. .