JPS62247618A - Inverter delay circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an inverter delay circuit, and in particular, the present invention relates to an inverter delay circuit in which the duty ratio of a delayed signal obtained at its output stage remains unchanged compared to that of a signal before delay. The present invention relates to such an inverter delay circuit.

[Conventional technology]

In a conventional inverter delay circuit, in a series connection circuit of inverters used as a delay circuit, the last stage inverter changes the duty ratio due to changes in rise and fall times due to an output buffer circuit connected to the output terminal of the inverter. However, this was not considered. Note that related delay circuits of this type include, for example, Japanese Patent Application Laid-Open No. 55-44248;
JP-A-56-120209 is mentioned.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology deals with the delay of signals such as FM signals and PWM signals in which the data ratio of the signals is a problem.
No consideration was given to preserving the duty ratio.
Due to the influence of the impedance of the circuit next to the last stage inverter, the rise delay time Ti of the last stage inverter
LH and falling delay time iHL are different from the rising delay time ILH and falling delay time TtKL of other inverters, and the duty ratio at the last stage is equivalent to the difference in delay time (T, 1L-1+!J). There was a problem with change.

An object of the present invention is to cancel the change in duty ratio by shifting the change in duty ratio corresponding to the delay time difference between rise and fall (TIL-TILII) in the inverter in the last stage in advance in the inverter in the previous stage,
It is an object of the present invention to provide a delay circuit capable of obtaining a delayed signal with no change in duty ratio at an output stage.

[Means for solving problems]

The above purpose utilizes the fact that the output signals of even and odd stages of inverters connected in series have opposite phases to each other, and the output of the last stage input is changed by connecting an output buffer circuit to the output terminal. At the end, at least the rise delay time of the even-numbered inverter is set to the same TI as above.
By connecting in parallel with the next stage an output buffer circuit having an impedance such that LHs and falling delay time are the same T and ttL as above, the delay time difference (Tlut-TIIL) which is in reverse phase with the last stage is Created at even-numbered stages, delay time difference at last stage (T+#LTHur)
By adding 1, this is achieved by canceling the difference in delay time between rise and fall.

[Effect]

In general, in an inverter connected in two stages, the signal input to the input terminal A of the first stage inverter is the output P4B of the first stage inverter, and assuming that the rise is delayed by, for example, TtLH1 and the fall is delayed by, for example, Tz ML, the delay time difference (Tv
It becomes an anti-phase signal with a changed duty ratio corresponding to tu-TtLi). Furthermore, the signal is delayed by H and L at the rising edge and by T211L at the falling edge at the output end of the next stage, but since the signal is reversed, the signal that rose at point A will fall at point B. So, at point A and point 0, (TxLx+T
The signal is delayed by txr, ) and has no change in duty ratio.

As a result, the rise delay time, e.g. T11ll, and the fall delay time, e.g. The duty ratio fluctuation due to the difference from T@HL is caused by the output stage of the inverter in the second stage counting from the last stage, and the rise delay time of that inverter is the same as the previous one.TI LM s
The falling delay time is also T1! By adding a circuit having an impedance for IL, that is, the same circuit as the output buffer, two stages of inverters having the same rise and fall delay times are connected, and the duty ratio is preserved.

Furthermore, even if the circuit connected to the output terminal of the second stage inverter counting from the last stage is connected to the output terminal of the even-numbered stages after the second stage, the data ratio is preserved until the last stage, so the last stage It becomes possible to compensate for fluctuations in the data ratio. As mentioned above, the circuit with the same characteristics as the output buffer circuit connected to the last stage inverter is worshiped as the output terminal of the even-numbered stage inverter counting from the last stage inverter. It is possible to eliminate changes in duty ratio caused by the inverter.

〔Example〕

An embodiment of the present invention is shown in FIG. 1 below. Figure 2 and 2nd
This will be explained using Figure A.

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an input/output waveform diagram of an inverter connected in two stages, and FIG. 2A is a circuit diagram of an inverter connected in two stages.

In the figure, N represents an integer. In FIG. 1, a plurality of N inverters are connected in series, and an output buffer circuit 10 is connected to the output terminal of an inverter l at the last stage.
In an inverter delay circuit configured to take out a signal via the inverter 1, the output buffer circuit 10 of the inverter 1 is caused by connecting the output buffer circuit 10 to the inverter 1 to the output terminal of the second stage inverter 2 counting from the last stage inverter 1. A circuit configuration in which a delay time matching circuit 11 having the same circuit configuration as the load, that is, the output buffer 10, is connected such that the rise delay times T, ti and the fall delay time TIHL are equal to the rise delay time and fall delay time of the inverter 2. It is shown.

Furthermore, it is also conceivable that the circuit 11 is connected not to the output stage of the inverter 2 but to the output end of an even-numbered stage inverter counting from the last stage inverter 1.

The above is the basic circuit configuration that is not inventive.

Next, Figure 2 shows the output waveform at each point when inverters 4 and 5 are connected in series as shown in Figure 2A, and the inverters are connected in two stages like this. FIG. 3 is a diagram for explaining that variations in duty ratio are canceled out. The signal input to point A in Figure 2A is B
The signal at point A is reversed, and the rising delay time of inverter 4, e.g., T4 LM s, is delayed by the falling delay time, e.g., T411L.
The signal is shifted by ILzr). Furthermore, at point 0, the signal at point B becomes an inverted signal (in phase with point A),
The rise delay time of the inverter 5 is delayed by, for example, T5LH*fall delay time, for example, TaML, and the duty ratio becomes a signal deviated from the signal at point B by (T5LH-T!IIL).

Here, the difference in duty ratio between point B and point 0 is the first term and the second term.
The reason why the terms are exchanged is that the signal is reversed by the inverter 4, and a signal that rises at point A becomes a signal that falls at point B (reverse phase). The rise delay time and fall delay time of inverter 4 and inverter 5 are the same (TaLu = Ta
Lx* liu :T,! IL), the signal at point 0 will be delayed by (T4HL+T4LH) from the signal at point A, and the duty ratio change will be 0 (T4HL-14LH+TaL).
n-TstrL=O), and the duty ratio becomes a preserved signal.

An embodiment of the present invention shown in FIG. 1 will be described based on the duty ratio preservation explained above.

Since the output buffer 10 is connected to the output terminal of the inverter 1 at the last stage, the load on the inverter 1 changes from that of the other inverters, and the rise delay time becomes, for example, TI LH*the fall time, for example, T+EL. Inverter rise delay time Tt LHe Fall delay time T*
It will be different from HL. Therefore, the duty ratio at the output stage changes by an amount corresponding to the delay time difference (TzHz 1Lii). Therefore, by connecting the circuit 11 as a load with the rise and fall delay times of the inverter 2 to TI LH and T111L, respectively, to the output terminal of the inverter 2 in the second stage counting from the output stage, the circuit 11 as explained in FIG. Two stages of inverters with equal rise and fall delay times are connected, making it possible to create a delay circuit with no change in duty ratio at the output stage.

Also, even if the circuit 11 is connected to the output stage of an even-numbered inverter instead of the second stage counting from the last stage inverter 1,
Since the delay time difference between the even-numbered stages is preserved, a delay circuit with no change in duty ratio at the output stage is possible.

A specific example is shown in FIG. In this case, the output buffer 10 in FIG. 1 is composed of a capacitor 12.15, an inverter 20, and a resistor 13.14, and the average value of the amplitudes of the inverters (1 to N) connected in series is set as the threshold level VTB. This is a self-biased inverter amplifier circuit that shapes the signal into a rectangular wave. This circuit has a resistor 1 for a signal capacitively coupled with a capacitor 12.
3.14 and a capacitor 15 to provide a self-bias to the inverter 20 by applying feedback.

This relationship is shown in FIG. In FIG. 4, characteristic 41 shows the input/output characteristics of the inverter, and characteristic 42 shows that the output voltage and input voltage become equal by applying feedback, and the operating point is at the intersection of characteristics 41 and 42. It becomes an inverting amplifier with an amplification factor according to the slope of characteristic 41. Since the input impedance of the self-biased inverter amplifier described above is generally low, the delay time of the inverter 1 is longer than that of a normal inverter. For this reason, the circuit 11 is the same as the output buffer 10, that is, the capacitors 12, 15 .
Inverter 20. A self-biased inverter configured with resistors 13 and 14 is used, and the rise and fall delay time difference of inverter 2 is created in advance, and this is applied to inverter 1.
In addition to the rise and fall delay times of , they are casselled from each other. This enables a delay circuit with no change in duty ratio at the output stage.

FIG. 5 shows another concrete example. In the embodiment shown in FIG. 3, if the load seen from inverter 1 is connected to the output terminal of inverter 2, inverter 1 will be added to the cargo area seen from inverter 2, and the change in delay time due to output buffer 10 will be Although it is not the head, strictly speaking, it is inverter 2.
and the delay time of inverter 1 are no longer the same. Therefore, in the non-embodiment, inverter 1 is connected to the output stage of inverter 1.
By adding 6, the loads of inverter 1 and inverter 2 are matched and the delay times are made the same. This makes it possible to create a delay circuit with no change in duty ratio compared to the embodiment shown in Figure @3.

FIG. 6 shows yet another specific embodiment. This example is the third
It is a circuit diagram when the circuit 11 of the embodiment shown in the figure is connected not to the second stage counting from the last stage but to the output stage of another even-numbered stage inverter. This is done by connecting the delay matching circuit 11 to the output terminal of the even-numbered inverter 6 (in Figure 6, the 6th stage is selected as an example), and adjusting the rise delay time and fall delay time of the inverter 6 to This is to match the rise delay time and fall delay time. In this case, an even number of inverters (
Since there are four stages (in FIG. 6), the delay time difference due to inverter 6 is preserved and transmitted to inverter 1. For this reason,
It is possible to obtain the same effect as in FIG.

FIG. 7 shows yet another specific embodiment. This example is the 6th
In the example shown in the figure in which the delay time adjustment circuit 11 is connected to the output end of the even-numbered stage inverter, the inverter rows after the even-numbered stage appear to be added to the cargo area seen from the even-numbered stage inverter. Therefore, the rise delay time and fall delay time of inverter 1 and the even-numbered inverter are different,
Strictly speaking, the difference in delay time cannot be canceled. Therefore, the inverter of the next stage that can be seen from the inverter of the even numbered stage is connected to the inverter of the last stage as in the case of FIG. 5, and the rise and fall delay times of the inverter of the even numbered stage are , the falling delay time is the same. Here, all of the inverters visible from the even-numbered stages may be connected to inverter 1 at the last stage, but the ones that affect the rise and fall delay times of inverter 1 are the ones that are next to inverter 1. Since this is the input impedance of each stage, there is not much effect even if there are multiple stages. From the above, the embodiment shown in FIG. 7 allows a delay circuit with fewer changes in duty ratio at the output stage.

FIG. 8 shows yet another specific embodiment. This is done by capacitively coupling the output buffer 10 shown in FIG.
Resistor 13 that applies feedback to the inverter voltage and the inverter voltage.
14 and a capacitor 15, the circuit configuration is such that bias is applied through a resistor 18, and the circuit 11 for matching the delay time has the same configuration as the output buffer circuit 10.

The output buffer 10 of FIG. 8 also performs the same function as the output buffer 10 of the embodiment of FIG. In the output buffer circuit IO of FIG. 8, if the threshold levels VTH of inverters 17 and 20 are not the same, the bias value of inverter 20 will deviate from the threshold level VTH of inverter 17, causing a change in duty ratio. For this reason, the inverters 17 and 20 must be designed as a pair.

Furthermore, the embodiments shown in FIGS. 5 to 7 can be applied to the output buffer 10 shown in FIG. 8 as well as in the case of the output buffer 10 shown in FIG. 3.

〔Effect of the invention〕

According to the invention, the rise delay time and fall delay time of the last stage inverter connected to the input side of the output buffer are determined in advance, and the rise delay time and fall delay time of the even-numbered stage inverters counted from the last stage inverter are calculated in advance. By making it equal to , the delay time difference can be canceled at the last stage inverter, so it is possible to configure a delay circuit in which the duty ratio does not change at the output stage.

[Brief explanation of drawings]

3 is a circuit diagram of a specific embodiment of the present invention, FIG. 4 is an input/output characteristic diagram of the self-biased inverter of FIG. 3, and FIG. 5 is a circuit of another embodiment of the present invention. Figure 6 is a circuit diagram of still another embodiment of the present invention, Figure 7 is a circuit diagram of still another embodiment of the present invention, and Figure 8 is a circuit diagram of still another embodiment of the invention. FIG. 1-7.1? , 20. N...Inverter 12, 1
5... Capacitor 13.14.18... Resistor 1
0... Output buffer circuit 11... Output buffer delay time adjustment dummy circuit Agent Patent attorney Masaru Ogawa 11 Mouth (α) 5 3 Mouth deception〈 Daigyukuni

Claims (1)

[Claims] 1. In an inverter delay circuit consisting of an even number of inverters connected in series and an output buffer connected to the output terminal of the inverter at the last stage, an even number counting from the inverter at the last stage is provided. An inverter delay circuit characterized in that a delay time adjustment circuit having the same characteristics as the output buffer is connected to the output end of the inverter in the second stage. 2. The inverter delay circuit according to claim 1, characterized in that the output buffer comprises an inverter having a self-biasing function and connected to the output terminal of the last-stage inverter via a capacitor. Inverter delay circuit.