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JPS6224522U - - Google Patents

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Publication number
JPS6224522U
JPS6224522U JP11566485U JP11566485U JPS6224522U JP S6224522 U JPS6224522 U JP S6224522U JP 11566485 U JP11566485 U JP 11566485U JP 11566485 U JP11566485 U JP 11566485U JP S6224522 U JPS6224522 U JP S6224522U
Authority
JP
Japan
Prior art keywords
variable delay
input
impedance
output
characteristic impedance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11566485U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11566485U priority Critical patent/JPS6224522U/ja
Publication of JPS6224522U publication Critical patent/JPS6224522U/ja
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例の回路構成図、第２
図は本考案の他の実施例の回路構成図である。 １……入力バツフア回路、２……集中定数型可
変遅延線、３……出力バツフア回路。 Figure 1 is a circuit configuration diagram of one embodiment of the present invention, Figure 2 is a circuit diagram of an embodiment of the present invention.
The figure is a circuit configuration diagram of another embodiment of the present invention. 1... Input buffer circuit, 2... Lumped constant variable delay line, 3... Output buffer circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 可変遅延機能を有する集中定数型可変遅延線の
入力端子に特性インピーダンスＺ０の入力インピ
ーダンスを有する入力バツフア回路を設けるとと
もに、出力端子に特性インピーダンスＺ０出力イ
ンピーダンスを有する出力バツフア回路を設け、
これら入出力バツフア回路を介して前記集中定数
型可変遅延線を特性インピーダンスＺ０の同軸線
路間に挿入したことを特徴とする可変遅延回路。 An input buffer circuit having an input impedance of characteristic impedance Z 0 is provided at the input terminal of a lumped constant type variable delay line having a variable delay function, and an output buffer circuit having an output impedance of characteristic impedance Z 0 is provided at the output terminal,
A variable delay circuit characterized in that the lumped constant type variable delay line is inserted between coaxial lines having a characteristic impedance Z0 via these input/output buffer circuits.
JP11566485U 1985-07-26 1985-07-26 Pending JPS6224522U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11566485U JPS6224522U (en) 1985-07-26 1985-07-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11566485U JPS6224522U (en) 1985-07-26 1985-07-26

Publications (1)

Publication Number Publication Date
JPS6224522U true JPS6224522U (en) 1987-02-14

Family

ID=30999528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11566485U Pending JPS6224522U (en) 1985-07-26 1985-07-26

Country Status (1)

Country Link
JP (1) JPS6224522U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63302617A (en) * 1987-06-02 1988-12-09 Nec Ic Microcomput Syst Ltd Delay circuit
JPH0446953U (en) * 1990-08-24 1992-04-21

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63302617A (en) * 1987-06-02 1988-12-09 Nec Ic Microcomput Syst Ltd Delay circuit
JPH0446953U (en) * 1990-08-24 1992-04-21

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