JPS62241448A - Data transmission method - Google Patents

Abstract

PURPOSE:To surely attain group synchronization by performing the group synchronization not by only a group synchronizing signal, but the value of a counter in combination. CONSTITUTION:The frame format of a transmit signal is provided with a frame synchronizing signal field a1, a group synchronizing signal field a2, a main data field a3, and a control data frame a4 and when data is transmitted, n=8 frames from the 1st frame F1 To the 8th frame F8 are grouped in one. In the field a2, the group synchronizing signal V which has logic '1' is arranged in only the frame F7 and group synchronizing signals V with logic '10' are arranged in the remaining frames F1-F6 and F8. This frame signal is received and the group synchronizing signal of the group synchronizing signal field is detected to count the number of times of reception of the group synchronizing signal field by a counter, which is initialized in synchronism with the detection of the group synchronizing signal with logic '1'. Then it is decided that the generation period of the logic '1' of the group synchronizing signal is reached and when this group synchronizing signal is detected, a signal indicating that frame groups are synchronized is sent out.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transmission system suitable for key telephone equipment ltK, and more particularly, to a data transmission system that can easily and accurately synchronize a group of frames. Regarding.

[Conventional technology]

In the button telephone device, the main data obtained by converting the audio signal iA/D is transmitted, and the activation request signal from the terminal,
It is required to transmit control data consisting of a signal indicating that the central office line is in use. Generally, control data is not placed centrally in a single frame button, but distributed over multiple frames. By doing so, the number of frames in which main data cannot be arranged can be reduced to zero. When control data is distributed and arranged in a plurality of frames, it is necessary to synchronize each frame and also to synchronize a group of frames including the control data. FIG. 6 shows the conventional group synchronization method, in which the start bit or frame synchronization signal field S
The group consists of a frame format consisting of a main data (audio or image data) field B, a control data field D, and a stop signal or no-signal field.

A group synchronization signal with a special code that can be distinguished from others is placed in the data field of the first frame of this group.

[Problem that the invention seeks to solve]

If the main data field of the first frame of the group is used for the group synchronization signal as described above, it becomes impossible to place the main data in this frame, and the original analog signal (
For example, it becomes difficult to reproduce analog signals with good fidelity (audio signals). Therefore, a field dedicated to the group synchronization signal is provided during formatting, and a logic "BI", for example, is entered into the group synchronization signal field of a specific frame selected from the group, and a logic "0" is written into the group synchronization signal field of the remaining frames.
It is possible to synchronize the group by reading a logical ``1'' using this method.However, if noise equivalent to 1 degree of logic occurs in this method, the group will be synchronized. becomes impossible.

Therefore, it is an object of the present invention to provide a data transmission system that can easily and reliably synchronize groups.

[Means for solving problems]

To solve the above problems and achieve the above objectives <7)
This BJII transmits main data in a frame of a predetermined format, and also stores control data in all or selected frames of a group of n frames (a number of 2 or more). In the data transmission method, the format is provided with at least a frame synchronization signal field a1, a group synchronization signal field a2, a main data field a3, and a control data field a4, and the format is provided with at least a frame synchronization signal field a1, a group synchronization signal field a2, a main data field a3, and a control data field a4. A group synchronization signal with a first content is placed in the group synchronization signal field of one or more frames that have been selected, and the first content is placed in the group synchronization signal field of all remaining frames that are not selected in the frame group. transmitting a frame signal in which a group synchronization signal having a second content different from the contents of the e group synchronization signal is arranged; receiving the frame signal and detecting a group synchronization signal in the group synchronization signal field; counting the number of times the field is received by a counter, and initializing the counter in synchronization with the detection of the group synchronization signal having the first content; after the counter is initialized, counting the number of times the field is received; determining whether or not the occurrence period of the first content of the first content has been reached based on the counter; and determining that the occurrence period of the first content of the group shikishiki has arrived after the counter is initialized; and when the group synchronization signal having the first content is detected, transmitting a signal indicating that the frame group is synchronized! This relates to the characteristic data transmission method.

[For production]

In the above invention, a group synchronization signal is detected from a group synchronization signal field provided in each frame, and this content indicates Il! which indicates group synchronization. Even if the contents of l are present, a signal indicating group synchronization (for example, a notification signal) will not be generated by this alone.The period in which the first content of the next group synchronization signal is generated has arrived after the counter is initialized. is determined by a counter, and a signal indicating valid group synchronization is generated only when the first content is actually detected.Therefore, group synchronization 'lk can be reliably achieved.

〔Example〕

Next, a key telephone device according to an embodiment of the present invention will be explained.

[Device overview]

For button telephone devices, the main device shown in Figure 1 (1)
Data must be exchanged between the terminal device (2) and the terminal device (2). Therefore, the main device (11) and the terminal device (2)
A receiving side transmission line (4) is provided between the receiving circuit (3) and a transmitting side transmission line (6) is provided between the transmitting circuit (5) and the main device (II). A device (11) has an exchange function and a transmitting/receiving circuit, and transmits data to a terminal device (11) using a frame format according to the present invention.
3), and also receives data sent from the transmitting circuit (51).

[Frame format]

As shown in Figure @3, the frame format of the transmission signal includes, for example, a field al for a start bit ST consisting of 2 bits, that is, a frame synchronization signal field, and a field a2 for a group synchronization signal 2 consisting of 1 bit according to the present invention. and 1, for example, a field a3 for main data (audio data) B consisting of 8 bits, and 1 field a4 for control data D, which indicates the use of a central office line, for example.
and a field a11 indicating that there is no signal i. When transmitting data in this frame format, the first frame (F1) to the eighth frame (F1) to
n = 8 frames with 8 frames F as one group t
,, control data D and group synchronization signal ■ in the group c! include. Data for each sampling period of A/D conversion is arranged in the main data field Fas of each frame, and the start bit field al provided at the beginning of the frame
K Fi, vI A start bit (frame synchronization signal) 8T, which is necessary for transmitting data in a four-step manner, is placed in the control data field a4. Control data D6 is arranged using frames F1 to F6.

No control data is arranged in the remaining m7 and eighth frames F7 and Fs.

In the group synchronization signal field a21c related to the present invention, as shown in FIG.
In the sixth frame F, ~F6 and wLs frame F8, a group synchronization signal with a second content consisting of logic @O'' is arranged. As is clear from the relationship with the distribution of synchronization signals, logic °1 is arranged as a group synchronization signal in the frame F next to the last frame F6 in which control data is stored. The group synchronization signal is a notification signal R, Q indicating that the reception of control data of the group to which it belongs has been completed.
can be used to generate

The last non-signal field a of the unit frame is a part provided so that the start bit ST can be reliably detected. In this example, field a11 is set to have no signal, but stop information may be placed here and start-stop data transmission may be performed using this.

[Configuration of receiving circuit]

In Figure 82, which shows a part of the receiving circuit (3) in Figure 1,
The frame separation circuit (7) connected to the data input transmission line (4) starts from the input frame in the format shown in FIG. The first content of the group synchronization signal VD, the main data B1 of field as, and the control data D of field a4 are separately detected.

The control unit (81 is a part that has a CPU and performs various controls, and the line (9) is used to send the clock signal CK, and the line (a) is used to send the group synchronization signal detection pulse VTV frame separation circuit (to the output). In addition, the clock signal CK
In order to generate the group synchronization signal detection pulse VT in synchronization with frame reception, the start bit ST output line αυ of the frame separation circuit (7) is connected to the control unit (83K).

The main data output line a2 of the frame separation circuit (7) is connected to the main data buffer memory 03 consisting of a shift register, and the control data output line (141) is connected to the control data buffer memory a9 consisting of a shift register. Batza memory 03Q518IC is the control unit (8
) are connected, frame synchronization and group synchronization are established, and then main data B and control data D are output as valid data.

In order to detect the synchronous period according to the present invention, a NAND gate 1 (161), an AND gate (iL), a synchronous n-ary counter θ&, a columnar input control signal (VE) generation circuit α1,
D flip 70 knob ■ and OR gate Qυ are provided.
ing. One input terminal of the NAND gate αe is connected to the logic 10 group synchronization signal output line derived from the frame separation circuit (7), and the other input terminal is connected to the binary output of the counter side in decimal notation. (111)
The output terminal of the carry output terminal CRVci is connected to the load terminal of the counter αυ. One input terminal of the AND gate αη is connected to the output terminal of the synchronous signal detection pulse VT of the control unit (8) through the line (2), and the other input terminal is connected to the VE generation circuit α■. , the output terminal is connected to the clock enable terminal ElC of the counter αa.
The clock terminal CK of 81 is connected to the clock signal output terminal of the control section (8) via the line (c). VE
The generation circuit α includes a pulse line (2
3), Clock line (2), counter carry output terminal CR.

The reset signal line (2) derived from the control unit (8)
9 is pregnant with connection. The reset signal line (C) is connected to the clear terminal CL of the counter (181) and is connected to the reset terminal R of the D7 lip 70 (A) via the OR gate/21. Note that the response signal (ACK) line (2) of the control section (8) is also connected via the reset terminal RKuOR gate Qυ of the D flip 70. Data input terminal Ilj counter (carry output terminal CR of 181) of D flip-flop (A)
K connection, and the clock input terminal CK receives the group synchronization signal (VD
) is connected to the detection pulse line (A), and the Q output terminal is connected to the notification signal RQ input terminal of the control unit (8) via line (5).

〔motion〕

Next, the operation of the circuit shown in FIG. 2 will be explained with reference to FIGS. 3 to 5. Now, if the transmission signal ND shown in FIG. Based on 1lK5
Tarock signal CK in figure [F] is generated [,.

The group synchronization signal V, main data B, and control data D are read at the timing determined by this clock signal CK.

) in FIG. 5 shows the generation timing of the synchronization signal detection pulse (VT pulse), which is generated in synchronization with the group synchronization signal field of each frame. In this example, Figure 4 (8
), only in the original 7th frame F7, logic "1" with the contents of ll, 1 is placed in the group synchronization signal field V, so during normal operation, t! There is only one effective synchronous period Hals (VD pulse) in one group of ~tLI as shown in Fig. 5 (Q
obtained as shown in .

When the power of the device is turned on, a reset signal is generated on the line (c), the counter α81 is initialized so that its value becomes zero, and the output of the VE creation circuit α is shown in FIG.
Since the level becomes high (H) as shown in Figure 5), V
It becomes possible for the T pulse to be input to the clock enable terminal E of the counter Q8) via the AND gate (17)'%-. ■T /< of the counter (181 is in Figure 5)
It responds to the clock signal CK shown in FIG. 5 [F] only during the pulse generation period. Since the vT pulse is set to have a clock period of one clock period, only one clock pulse inputs the counter α8)K during one VT pulse period. (2) T pulses are generated in synchronization with the group synchronization signal field as shown at t2, ts, ts, and L12, and the counter side is incremented in response.

■T pulses are input sequentially at one frame interval, and when the binary output value of the counter αe reaches (1113), the signal VDE of the carry output terminal CR becomes high level at <ts as shown in FIG. This is given to the VE creation circuit (1!I,
When this output is at a low level a little later than ts, as shown in FIG. 0, the AND gate αη blocks the input of the VT pulse. Therefore, even if a vT pulse occurs, the counter α& is not incremented and the carry output terminal CR is kept at a high level. A VD pulse is available on the line for at least eight frames to be transmitted after a high level carry output occurs at 2 sts during the initial power-up operation. Incidentally, since FIG. 5 shows a normal operating state, 1. which is one frame time after t5 and a little before tll. A vD pulse is generated.

When a VD pulse is generated from t7 to t9, this becomes the clock input of the D flip-flop ■, and the D7 flip-flop (A) reads the high level of the data input terminal, and this Q output is the 511th (G) high level notification signal. Become HQ. This notification signal notifies the control unit (8) that the RQd group has been synchronized and that the reception of control data has been completed.

Since the VD pulse is input to the NAND gate (161),
At time t7, both inputs of the NAND gate a61 become high level, and its output changes to low level. As a result, the counter αF3 is loaded to zero in synchronization with the clock at time 18, the carry output terminal CR becomes low level, and the output of the vE generation circuit a9 becomes high level.

When the control unit (8) receives the notification signal RQ, it generates a response signal ACK in response to it at the time too.The D flip-flop is reset in response to the response signal ACK.
At tlo, the communication signal RCJ returns to low level.

When the VT pulse of the 8th frame F8 from tll to t13 is generated, the counter is incremented by one step by +12 in response to this r(.After that, the next group of VT pulses enters the counter Q81, so the counter is output. The cuff is incremented to [111].

At the end of this method, the counter αQ counts at 7, and unless the carry output terminal CR is at a high level, V
Even if a high level pulse occurs on the D line @, the notification signal RQ
does not occur. In other words, if the carry output terminal CR is at a low level, even if a VD pulse is input from the VD line to the D flip 70 g (a), the D flip 70 g
is not set.

This means that even if noise similar to a valid VD pulse occurs when the count output value of the counter α barrel is 0 to 6 in decimal notation,
D frig 701 does not respond to this and the notification signal RQ
'? means it will not occur.

During normal operation, when a valid VD pulse is generated from t7 to t9 in FIG. 5, the counter is initialized to zero, and vE in FIG. 5 returns to a high level, so that the counter α8
Start counting the VT pulses shown in Figure 1, wJ5, a3), and +1
It is re-initialized when 8 vT pulses are generated, with 2 being the first pulse. As a result, one notification signal RQ is generated in one group, making it possible to receive data in a synchronized manner.

By the way, the VD pulse of FIG. 5 (0) is generated in the seventh frame I puff. That is, the VD pulse is generated after the reception of the control data D and D6 included in frames F and F6 is completed. Therefore, the response signal R corresponding to the VD pulse
Q, functions as a notification signal indicating completion of reading of control data. When the control unit (8) receives the notification signal RQ at t7, the control unit (8) outputs the control data of this group written in the control data buffer memory (151) shown in FIG. 2 as valid data. It also instructs the main data memory αJ to output the main data already written in i!t-1 and the main data of this group written from this 4 as valid data. Since reception at t1 to tts in Figure 5 is found to be effective, W!, data transmission from the terminal device (21 in Figure 1 to the main f2ft (11) is also performed. At time T from 17 to t13 in the figure, the next group of transmission frames is formed, and 113
start sending. It should be noted that if frames F7 and FB are provided in which no control data is arranged, there will be a loss in that the processing of the control data on the receiving side cannot be completed within the period of the group Jf4-r.

The details of the transmitter circuit (51 are not shown, but are shown in FIG.
In response to the generation of the notification signal RQ shown in FIGS.
The group frame format shown in the figure) creates the same transmission frame, and synchronizes it with the received frame.
It is configured so that it is sent from the main device to the main device.

[Modified example]

The present invention is not limited to the above-described embodiments, but may be modified, for example, as follows.

It can be applied not only to transmission and reception between the 11 and the terminal equipment!+21, but also to data transmission between audio/video transmission/reception circuits or between CPUs.

(It may be determined that the logic "0" is placed in one selected frame of the bl synchronization signal, and the logic "0" is placed in all the remaining frames.Also, the contents of ml (for example, ")"
') may be placed in a plurality of consecutive frames within the same group [7, all remaining frames KI of the same group] The contents of L2 (for example @O'') may be placed.

The tc+ control data may be placed in all of the group frames F1 to Fs. In this case, a synchronization signal with the contents of M1,1 is placed in the first frame F1 of the next group.

(dlV]) pulse can be used for signals other than the notification signal RQ, and can be used only for the synchronization period signal.

〔Effect of the invention〕

As is clear from the above, according to one aspect of the present invention, the synchronization period is not established using only the synchronization period signal, but the synchronization period is determined in combination with the value of the counter, so that the synchronization period can be reliably obtained.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the principle of a button telephone device according to an embodiment of the present invention, Figure 2 is a block diagram showing a part of the receiving circuit of the terminal installed in Figure @1, and Figure 3 is a block diagram showing the principle of a button telephone device according to an embodiment of the present invention. *Figure 4 shows the group frame format used in the methods shown in Figures 1 and 2, and the values of the synchronization signal and control data. FIG. 5 is a diagram showing the state of each part in FIG. 2, and FIG. 6 is a diagram showing a conventional group frame format. ■...Synchronization signal, B...Main data, D...Control data, (7)...Frame separation circuit, (8)...
Control unit, α &... Counter % (A)...7 17
0 tsubu.

Claims (2)

[Claims] (1) The main data is stored in a frame of a predetermined format and transmitted, and the control data is transmitted in n pieces (
In a data transmission method in which data is transmitted by being accommodated in all or a selected plurality of frames in a frame group consisting of a number of 2 or more, the format includes at least a frame synchronization signal field (a_1) and a group synchronization signal field (a_2). )
, a main data field (a_3), and a control data field (a_4), and a group synchronization signal with a first content is provided in the group synchronization signal field of one or more frames selected from the frame group. is arranged, and a second content different from the first content is placed in the group synchronization signal field of all remaining unselected frames in the frame group.
transmitting a frame signal in which a group synchronization signal having the contents of is arranged; receiving the frame signal and detecting a group synchronization signal in the group synchronization signal field; and counting the number of times the group synchronization signal field is received by a counter. and initializing the counter in synchronization with the detection of the group synchronization signal of the first content, and after the counter is initialized, the period of occurrence of the first content of the group synchronization signal is reached. determining whether or not the first content of the group synchronization signal has reached the generation period of the first content of the group synchronization signal after the counter is initialized; A data transmission system characterized by transmitting a signal indicating that the frame group is synchronized when a synchronization signal is detected. (2) The data transmission method according to claim 1, wherein the group synchronization signal having the first content is arranged in a frame next to the last frame in which the control data is stored. .