JPS62240930A - Manufacture of liquid crystal display panel - Google Patents
Manufacture of liquid crystal display panelInfo
- Publication number
- JPS62240930A JPS62240930A JP61085315A JP8531586A JPS62240930A JP S62240930 A JPS62240930 A JP S62240930A JP 61085315 A JP61085315 A JP 61085315A JP 8531586 A JP8531586 A JP 8531586A JP S62240930 A JPS62240930 A JP S62240930A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- pattern
- common electrode
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 25
- 125000006850 spacer group Chemical group 0.000 claims abstract description 16
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 15
- 238000007789 sealing Methods 0.000 claims abstract description 6
- 239000011347 resin Substances 0.000 claims abstract 2
- 229920005989 resin Polymers 0.000 claims abstract 2
- 239000010408 film Substances 0.000 claims description 65
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 3
- 230000007261 regionalization Effects 0.000 claims 1
- 239000007772 electrode material Substances 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 11
- 239000011521 glass Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000002834 transmittance Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003892 spreading Methods 0.000 description 3
- 239000011324 bead Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 235000012364 Peperomia pellucida Nutrition 0.000 description 1
- 240000007711 Peperomia pellucida Species 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000011149 active material Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 235000012054 meals Nutrition 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は液晶表示パネル(以下、LCDパネルと略称す
る。)、特にTFT等を用い之アクティブマ) IJフ
ックス式の大型LCD表示パネルの製造法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a liquid crystal display panel (hereinafter abbreviated as "LCD panel"), particularly to a method for manufacturing a large IJ-Fuchs type LCD display panel using active materials such as TFT. It is something.
従来の技術
TPT等を用いたアクティブマトリックス方式LCDパ
ネルは、第3図、第4図に示すように、主面上に透明な
画素電極1、同画素電極1を制御するTPT等の制御素
子2、さらに制御素子群を選択連動するための走査信号
線パターン3、及び画像信号線パターン4を有するガラ
ス等からなる透明主基板5と、ガラス等の透明基板の主
面全域に透明導電性膜、所謂ITOli16を被着して
なる対向共通電極用透明基板7をガラスピーズ等からな
るスペーサ8を介して2〜10Itm(LCDパネル構
成により異なる)の間隔で近接配置し、両基板6.7の
間隙部9に液晶1oを注入封止することによって得てい
る。なお、第4図中において、11.12はそれぞれ走
査信号線パターン3及び画像信号線パターン4の外部引
き出し用電極端子部、13は液晶封止部、また14は対
向共通電極用透明基板7におけるITOTeO2基板6
との接続用電極である。As shown in FIGS. 3 and 4, an active matrix type LCD panel using conventional technology TPT or the like has a transparent pixel electrode 1 on the main surface and a control element 2 such as TPT that controls the pixel electrode 1. Furthermore, a transparent main substrate 5 made of glass or the like has a scanning signal line pattern 3 for selectively interlocking the control element group and an image signal line pattern 4, and a transparent conductive film is formed on the entire main surface of the transparent substrate such as glass. Transparent substrates 7 for common electrodes coated with so-called ITOli 16 are arranged close to each other at intervals of 2 to 10 Itm (varies depending on the LCD panel configuration) via spacers 8 made of glass beads, etc., and the gap between both substrates 6.7 is This is obtained by injecting and sealing the liquid crystal 1o into the portion 9. In FIG. 4, 11 and 12 are external lead-out electrode terminal portions of the scanning signal line pattern 3 and image signal line pattern 4, respectively, 13 is a liquid crystal sealing portion, and 14 is a portion of the transparent substrate 7 for the common electrode. ITOTeO2 substrate 6
This is an electrode for connection with.
発明が解決しようとする問題点
L c D パネルに用いる透明な対向共通電極は、一
般的には前述のように透明基板γ上に透明導電性電極薄
膜としてITOTeO2用するが、このITOTeO2
透過性を考慮した場合薄く形成することが好ましく、通
常100人〜1000人程度の膜厚で形成してあり、そ
のシート抵抗は数10〜数100Ω/口程度である。ま
た、対向共通7u極であるITOTeO2部回路との接
続電極部分は、LCDパネルの構成上、そのパネルのコ
ーナ部分等の隅部に設けられることが多い。(第4図)
LCDパネルのサイズが小さい場合には、上記のような
方法で対向共通電極を構成しても、ITO膜6内での拡
がり抵抗の影響は実用上差し障りはないが、LCDパネ
ルのサイズが大型化するに従って、■TO膜6内におけ
る拡がり抵抗が画像品質に悪影響を及ぼす要因となる。Problems to be Solved by the Invention L c D The transparent counter common electrode used in the panel is generally made of ITOTeO2 as a transparent conductive electrode thin film on the transparent substrate γ as described above.
In consideration of permeability, it is preferable to form the film thinly, and it is usually formed with a film thickness of about 100 to 1000 ohms, and its sheet resistance is about several 10 to several 100 Ω/hole. Moreover, the connection electrode portion with the ITOTeO 2-part circuit, which is the opposing common 7u pole, is often provided at a corner such as a corner portion of the panel due to the structure of the LCD panel. (Fig. 4) If the size of the LCD panel is small, even if the opposing common electrode is configured in the manner described above, the influence of the spreading resistance within the ITO film 6 will not cause any practical problems. As the size of the TO film 6 increases, the spreading resistance within the TO film 6 becomes a factor that adversely affects image quality.
即ち、外部回路接続電極部の近傍と、隅部から最も離れ
た部位では膜抵抗が異なり、上記ITO膜6を対向共通
電極とした場合同膜面内の電位に差が生じ、LCDパネ
ル内の各単位画素部の表示特性に差異ができ、均一な画
素像を有するLCDパネルの提供に支障をきたすことに
なる。That is, the membrane resistance is different in the vicinity of the external circuit connection electrode part and the part farthest from the corner, and when the ITO film 6 is used as a common electrode, a difference occurs in the potential within the film surface, and the This causes differences in the display characteristics of each unit pixel portion, which poses a problem in providing an LCD panel with uniform pixel images.
この問題を解決するための手段として、ITOTeO2
−ト抵抗を下げることが考えられる。しかし、シート抵
抗を下げるためにはITOTeO2厚を厚くするか、も
しくはITOTeO2成、即ち膜質を変える等の方策を
講じる必要があり、何れの場合にも通常はITOTeO
2透過率を下げるため、透明導電性膜としての一方の機
能を損なうことになる。As a means to solve this problem, ITOTeO2
- It is possible to lower the resistance. However, in order to lower the sheet resistance, it is necessary to take measures such as increasing the ITOTeO2 thickness or changing the ITOTeO2 formation, that is, the film quality.
2. Since the transmittance is lowered, one of the functions as a transparent conductive film is impaired.
さらに、LCDパネルの大型化に伴うもうひとつの問題
は、液晶を注入する部位の間隙精度の保持である。即ち
、主基板6と対向共通電極用の透明基板7間の間隙寸法
の調整を、ガラスピーズ等のスペーサ8を間隙部に散布
し、同スペーサ径により基板5,7間の間隙を保持調整
する方式が一般に使用されている。この場合の要諦は基
板全面に対する均一なスペーサの散布であるが、基板寸
法が大型化すると散布の均一性を保持することが難しく
、間隙寸法に不均一が生じるという問題がある。Furthermore, another problem associated with the increase in size of LCD panels is maintaining the gap accuracy at the portion where liquid crystal is injected. That is, to adjust the size of the gap between the main substrate 6 and the transparent substrate 7 for the opposing common electrode, spacers 8 such as glass beads are scattered in the gap, and the gap between the substrates 5 and 7 is maintained and adjusted using the same spacer diameter. method is commonly used. The key in this case is to uniformly distribute the spacers over the entire surface of the substrate, but as the substrate size increases, it is difficult to maintain uniformity in the distribution, resulting in non-uniformity in the gap size.
問題点を解決するための手段
この問題点を解決するために本発明は、光の透過領域に
位置する対向共通電極のITO膜の膜厚は薄く形成し、
非透過領域部のITOg層は厚く形成して低抵抗化を図
った言わば2層構造の製造法により対向共通電極を形成
することで、ITO膜内の面抵抗の低下を図ると共に、
非透過領域部のITO膜層を厚く形成するプロセスでの
マスク材料を間隙寸法保持用のスペーサ材として流用す
ることにより、基板の大型化に対しても均一な間隙寸法
の保持を図っている。なお、この選択的に形成する低抵
抗ITO層並びにスペーサ用マスク材料の平面形状は、
LCDパネルの主基板S上に形成した走査信号線パター
ン3もしくは画像信号線パターン4の形状と同一形状で
形成する。Means for Solving the Problem In order to solve this problem, the present invention provides a method in which the ITO film of the opposing common electrode located in the light transmitting region is formed to be thin.
The ITOg layer in the non-transparent region is formed thickly to reduce the resistance.By forming the opposing common electrode using a manufacturing method with a so-called two-layer structure, the sheet resistance within the ITO film is reduced.
By using the mask material used in the process of forming a thick ITO film layer in the non-transparent region as a spacer material for maintaining the gap size, it is possible to maintain a uniform gap size even when the substrate size is increased. The planar shape of the selectively formed low resistance ITO layer and spacer mask material is as follows:
It is formed in the same shape as the scanning signal line pattern 3 or the image signal line pattern 4 formed on the main substrate S of the LCD panel.
作用
本製造法により製造した透明な対向共通電極用ITO膜
は画素表示領域、即ち透光部は透過率を重視した薄層I
TO膜が、非透光部には導電性を重視した厚い膜厚のI
TO膜を形成した構造となるため、この対向共通電極全
体の面抵抗を下げ得ると共に透光領域の透過率を低下せ
しめない、換言すれば損失の少ない透過型LCDパネル
を提供することができると共に、間隙保持用スペーサは
パターン形成法により所定の寸法形状で基板全域に形成
するため、パネル全面において均一な間隙寸法を保持す
ることができる。The transparent ITO film for the counter common electrode manufactured by this manufacturing method has a thin layer I with emphasis on transmittance in the pixel display area, that is, the light-transmitting part.
The TO film has a thick I film with emphasis on conductivity in the non-light-transmitting areas.
Since it has a structure in which a TO film is formed, it is possible to lower the sheet resistance of the entire opposing common electrode and not to reduce the transmittance of the light-transmitting region, in other words, it is possible to provide a transmissive LCD panel with low loss. Since the gap maintaining spacer is formed over the entire substrate in a predetermined size and shape by a pattern forming method, it is possible to maintain a uniform gap size over the entire panel surface.
実施例
第1図は本発明の製造法により構成したLCDパネルの
完成時の断面構造を示す部分断面拡大図である。また、
第2図A〜Cは本発明のスペーサ機能を持った対向共通
電極の製造法を示す断面拡大略図である。なお、図面は
作図の都合及び説明の便宜上、寸法は任意に拡大しであ
る。Embodiment FIG. 1 is an enlarged partial cross-sectional view showing the completed cross-sectional structure of an LCD panel constructed by the manufacturing method of the present invention. Also,
FIGS. 2A to 2C are enlarged cross-sectional diagrams showing a method of manufacturing a common electrode having a spacer function according to the present invention. Note that the dimensions of the drawings are arbitrarily enlarged for convenience of drawing and explanation.
以下、図面により詳述する。なお、第1図、第2図で従
来例と同一箇所には同一番号を付しである。まず、第2
図人のように対向共通電極用透明基板7の主面15全面
に透明な対向共通電極材としてITO膜60を数100
0Å以上の膜厚で被着する。次に、このITO膜6膜上
0上真食刻処理用ホトレジストを数μm〜’+ottm
の膜厚で形成する。この時のホトレジストの形成膜厚の
設定は後述するが、その形成法は膜厚が2〜37tm以
下の場合には、液状ホトレジストを用いたスピンコード
法で、膜厚が厚い場合にはそれぞれの膜厚に対応したフ
ィルム状ホトレジストを使用するが、形成法はこれに限
定されるものではなく、所定の膜厚形成ができるもので
あればよい。The details will be explained below with reference to the drawings. Note that in FIGS. 1 and 2, the same parts as in the conventional example are given the same numbers. First, the second
As shown in the figure, hundreds of ITO films 60 are coated as a transparent counter common electrode material on the entire main surface 15 of the transparent substrate 7 for the counter common electrode.
Deposit with a film thickness of 0 Å or more. Next, on this ITO film 6 film, a photoresist for true etching treatment is applied to a thickness of several μm to '+ottm.
Formed with a film thickness of The setting of the film thickness of the photoresist at this time will be described later, but the formation method is the spin code method using liquid photoresist when the film thickness is 2 to 37 tm or less, and the spin code method using liquid photoresist when the film thickness is thick. Although a film-like photoresist corresponding to the film thickness is used, the forming method is not limited to this, and any method that can form a film with a predetermined thickness may be used.
次に、第4図で説明した主基板6上に機能素子2、制御
配線等のパターン形成時に使用したホトマスク、具体的
にはここではストライブ状のパターン形状を有する走査
信号線パターン3形成用ホトマスクを用いて、上記ホト
レジスト膜のパターンピッチを実施すると、第2図Bの
ような断面形状を持ち、かつパターン巾Wm及びパター
ンピッチPmが、走亘信号線パターン3のパターン巾W
p及びパターンピッチPpと等しいストライブ状のホト
レジストパターン16がITO膜6o上に形成される(
第2図B、Cの断面は第3図の人−人′ 部に対応する
部位の拡大略図である。)。Next, a photomask used to form patterns for the functional elements 2, control wiring, etc. on the main substrate 6 as described in FIG. When the pattern pitch of the photoresist film is determined using a photomask, it has a cross-sectional shape as shown in FIG. 2B, and the pattern width Wm and pattern pitch Pm are the pattern width W of the running signal line pattern 3
A striped photoresist pattern 16 equal to p and pattern pitch Pp is formed on the ITO film 6o (
The cross-sections in FIGS. 2B and 2C are enlarged schematic views of portions corresponding to the man-to-man' section in FIG. ).
なお、このストライブ状のホトレジストパターン16の
形成は、主基板5上に画像信号線パターン4を形成する
ためのホトマスクを用いてパターン形成してもよい。Note that the striped photoresist pattern 16 may be formed using a photomask for forming the image signal line pattern 4 on the main substrate 5.
このホトレジストパターン16をマスクとして第2図C
のように、透光領域即ち画素領域部17となる部位のI
TO膜60の膜厚を選択的に減少せしめ、同部位ITO
膜を1000Å以下の膜厚の薄膜層ITO膜層61とし
た後、マスクとして用いたホトレジストパターン16を
熱処理あるいは電子線照射処理等の処理により、残存す
る膜厚の厚いITO膜6膜層2層上化残置させる。Using this photoresist pattern 16 as a mask, FIG.
As shown in FIG.
The thickness of the TO film 60 is selectively reduced, and the ITO
After forming the film into a thin ITO film layer 61 with a thickness of 1000 Å or less, the photoresist pattern 16 used as a mask is subjected to heat treatment or electron beam irradiation treatment to form the remaining thick ITO film 6 and two layers. Leave the top up.
なお、ITO膜eo上に形成するホトレジストの形成厚
さは次のように設定する。例えば、LCDパネルの液晶
注入部の間隙(セルギヤ・7プ)9が6μm1画素領域
部17の薄膜層ITO膜61の膜厚は600人、他の残
存厚膜層ITO膜62の膜厚が1μであれば、残存硬化
させた後のホトレジストの膜厚が約51tとなるように
、硬化時の収縮を見込んで5 lt+αの膜厚を被着時
に設定する。Note that the thickness of the photoresist formed on the ITO film eo is set as follows. For example, the gap (cell gear 7) 9 in the liquid crystal injection part of the LCD panel is 6 μm, the thickness of the thin ITO film 61 in the pixel area 17 is 600, and the thickness of the remaining thick ITO film 62 is 1 μm. If so, a film thickness of 5 lt+α is set at the time of deposition, taking into account shrinkage during curing, so that the film thickness of the photoresist after residual curing is approximately 51 t.
以上のようにして製造した膜厚の異なるITO膜61.
62及び硬化ホトレジスト16からなるスペーサを形成
した共通電極用透明基板7を、第1図に示すように機能
素子2その他をその主面に形成した透明主基板5上に主
面相互を対向させ、かつ透明主基板6の走査信号線パタ
ーン3と共通電極用透明基板7の厚膜層ITO膜62の
相対位置が合致するように載置圧接し、両基板6.7間
を接着固定すれば、両基板5,7間には厚膜層ITO[
62及びホトレジストパターン16からなるスペーサが
構成する間隙部9が形成され、この間隙部9に液晶10
を注入封止することによりLCDパネルが得られる。ITO films 61 with different film thicknesses manufactured as described above.
A common electrode transparent substrate 7 on which a spacer made of 62 and a hardened photoresist 16 is formed is placed so that its main surfaces face each other on a transparent main substrate 5 on which functional elements 2 and others are formed on its main surface, as shown in FIG. And if the scanning signal line pattern 3 of the transparent main substrate 6 and the thick film layer ITO film 62 of the common electrode transparent substrate 7 are placed and pressed so that their relative positions match, and the two substrates 6 and 7 are fixed with adhesive, A thick film layer of ITO [
62 and a spacer made of a photoresist pattern 16, a gap 9 is formed, and a liquid crystal 10 is formed in this gap 9.
An LCD panel is obtained by injection sealing.
発明の効果
従来の薄膜層ITO膜のみの透明対向共通電極では、そ
の薄膜層ITO膜のシート抵抗の関係上、基板が大型化
するに従って電極抵抗が増大し友が、本発明の製造法に
よる透明対向共通電極基板を用いたLCDパネルでは、
第1図に示すように光源(図示せず)からの光18を制
御する画素領域17の透明対向共通電極のITO膜6膜
上1く、回部での透過光の吸収による損失を低くするこ
とができると共に、制御素子部、走査信号線パターン3
等が形成する非透光領域19に対向する部位のITO膜
6膜上2厚を厚く形成することにより低抵抗化層としで
あるため、画素領域17の開孔率及び透過率を損なうこ
とが無く、同基板の面抵抗を下げることができ、拡がり
抵抗の増大電位分布の不均一性に伴う画像品質の低下を
抑制する効果がある。Effects of the Invention In the conventional transparent counter common electrode made only of a thin ITO film, the electrode resistance increases as the substrate becomes larger due to the sheet resistance of the thin ITO film. In an LCD panel using a facing common electrode substrate,
As shown in FIG. 1, the ITO film 6 of the transparent counter common electrode of the pixel area 17 that controls the light 18 from the light source (not shown) is placed on the ITO film 6 to reduce the loss due to absorption of transmitted light in the circuit. control element section, scanning signal line pattern 3
By forming a thick layer on the ITO film 6 at the portion facing the non-light-transmitting region 19 formed by the above-described materials, a low-resistance layer is formed, so that the aperture ratio and transmittance of the pixel region 17 are not impaired. Therefore, the sheet resistance of the substrate can be lowered, and there is an effect of suppressing the deterioration of image quality due to the increase in spreading resistance and the non-uniformity of the potential distribution.
さらに、LCDパネルの大型化に伴う間隙(セルギャッ
プ)の均一性の保持を、2層構造のITO膜層形成プロ
セスに用いたホトレジストパターンを硬化させてスペー
サとしているため、パネル全面に亘って均一なスペーサ
が配置できるため、間隙の均一性の保持向上に対する効
果も大きい。Furthermore, in order to maintain the uniformity of the cell gap as LCD panels increase in size, the photoresist pattern used in the two-layer ITO film formation process is hardened and used as a spacer, resulting in a uniform cell gap across the entire panel. Since spacers can be arranged, the effect of maintaining and improving the uniformity of the gap is also large.
第1図は本発明の製造法によるLCDパネル完成時の断
面拡大略図、第2図に、Cは本発明による対向共通電極
用透明基板の製造法をしめず断面拡大略図、第3図は従
来例によるLCDパネルの断面拡大略図、第4図はLC
Dパネルの主基板のモ面形状例を示す平面略図である。
1・・・・・・画素電極、2・・・・・・TFT等の制
御素子、3・・・・・・走査信号線パターン、4・・・
・・・画像信号線パターン、6・・・・・・透明主基板
、θ、60・・・・・・透明導電性膜(ITO膜)、6
1・・・・・・薄膜層ITO膜、62・・・・・残存厚
膜層ITO膜、7・・・・・・対向共通電極用透明基板
、8・・・・・・スペーサ、9・・・・・・間隙部、1
o・・・・・・液晶、11・・・・・・定食信号パター
ン引出し′電極端子部、12・・・・・・画像信号パタ
ーン引出し電極端子部、13・・・・・・液晶封止部、
14・・・・・・対向共通電極の外部接続用端子部、1
5・・・・・・対向共通電極用透明基板7の主面、16
・・・・・・ホトレジストパターン、17・・・・・・
透光領域即ち画素領域部、18・・・・・・光源からの
照射光、19・・・・・・非透光領域。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名/−
−自承噺り諏
J−一え全信号パターン
5−遊明主基弘
bノー、〕1拶も@ I TOR
62−邦存肩屓層ITO履
7一−−灯狙円1交V藺碑偽抜
’y−rW1飄部(じルキキップ)
7一対祝寿す眉囲透男匙双
6ノ一オ屓ITO店肩
62= i5PrMICITO8
第3図
第4図
A #FIG. 1 is an enlarged schematic cross-sectional view of a completed LCD panel according to the manufacturing method of the present invention, FIG. An enlarged schematic cross-sectional view of an LCD panel according to an example, FIG.
FIG. 7 is a schematic plan view showing an example of the cross-sectional shape of the main board of the D panel. 1... Pixel electrode, 2... Control element such as TFT, 3... Scanning signal line pattern, 4...
...Image signal line pattern, 6...Transparent main substrate, θ, 60...Transparent conductive film (ITO film), 6
DESCRIPTION OF SYMBOLS 1... Thin film layer ITO film, 62... Residual thick film layer ITO film, 7... Transparent substrate for opposing common electrode, 8... Spacer, 9... ...Gap part, 1
o...Liquid crystal, 11...Set meal signal pattern drawer' electrode terminal part, 12...Image signal pattern drawer electrode terminal part, 13...Liquid crystal sealing Department,
14...Terminal part for external connection of opposing common electrode, 1
5... Main surface of transparent substrate 7 for opposing common electrode, 16
...Photoresist pattern, 17...
Light-transmitting area, ie, pixel area, 18... Light emitted from the light source, 19... Non-light-transmitting area. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
- Self-confessed plagiarism J - One all signal pattern 5 - Yumeishu Motohiro b no, ] 1 greeting @ I TOR 62 - Kokusai shoulder layer ITO shoes 71 - Touaien 1kou V stamp False extraction'y-rW1 Jiruki Kip 7 pairs of congratulatory eyebrows transparent men's spoons 6 no.
Claims (3)
縞状にパターンニングした数1000Å以上の膜厚の厚
膜層とからなる2層の導電性透明電極膜を形成すると共
に、この膜厚導電性透明電極膜パターン層上に、そのパ
ターン形成用ホトレジスト(感光性樹脂)パターンを残
置せしめて間隙保持用スペーサとし、この導電性透明電
極膜基板を対向共通電極用透明基板とすると共に主基板
との間に液晶を注入封止することを特徴とした液晶表示
パネルの製造法。(1) A thin film layer with a thickness of 1000 Å or less on a transparent substrate,
A two-layer conductive transparent electrode film consisting of a thick film layer with a film thickness of several thousand angstroms or more is formed in a striped pattern, and a photoresist for pattern formation is formed on this conductive transparent electrode film pattern layer. (Photosensitive resin) pattern is left as a spacer for maintaining a gap, and this conductive transparent electrode film substrate is used as a transparent substrate for an opposing common electrode, and liquid crystal is injected and sealed between it and the main substrate. Manufacturing method for liquid crystal display panels.
導電性透明電極膜及び同膜上の残置ホトレジストパター
ンの寸法形状を、主基板上の制御配線パターンと同一寸
法形状で形成し、この共通電極用透明基板のパターンを
主基板上の制御配線パターンに対向合致させて載置し、
前記パターンが形成する両基板間の間隙部に液晶を注入
封止することを特徴とした特許請求の範囲第1項に記載
の液晶表示パネルの製造法。(2) Thickness of the striped pattern provided on the common electrode transparent substrate The conductive transparent electrode film and the remaining photoresist pattern on the same film are formed to have the same dimensions and shape as the control wiring pattern on the main board. Place the common electrode transparent substrate pattern so that it matches the control wiring pattern on the main substrate,
2. The method of manufacturing a liquid crystal display panel according to claim 1, further comprising injecting and sealing liquid crystal into the gap between the two substrates formed by the pattern.
上に導電性透明電極膜を、この導電性透明電極膜上にホ
トレジストを被着し、このホトレジストを主基板上に形
成する制御配線パターン形成用ホトマスクによりホトレ
ジストパターンを形成し、同ホトレジストパターンをマ
スクとして選択的に導電性透明電極膜の膜厚を1000
Å以下に減少せしめ、しかる後に前記ホトレジストパタ
ーンを残存導電性透明電極膜上で硬化残置せしめたこと
を特徴とした特許請求の範囲第1項に記載の液晶表示パ
ネルの製造法。(3) A control wiring pattern in which a conductive transparent electrode film with a thickness of several thousand angstroms or more is deposited over the entire main surface of the common electrode transparent substrate, a photoresist is deposited on the conductive transparent electrode film, and the photoresist is formed on the main substrate. A photoresist pattern is formed using a forming photomask, and using the photoresist pattern as a mask, the thickness of the conductive transparent electrode film is selectively increased to 1000 mm.
2. The method of manufacturing a liquid crystal display panel according to claim 1, wherein the photoresist pattern is reduced to less than .ANG., and then the photoresist pattern is left to harden on the remaining conductive transparent electrode film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61085315A JPS62240930A (en) | 1986-04-14 | 1986-04-14 | Manufacture of liquid crystal display panel |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61085315A JPS62240930A (en) | 1986-04-14 | 1986-04-14 | Manufacture of liquid crystal display panel |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62240930A true JPS62240930A (en) | 1987-10-21 |
Family
ID=13855171
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61085315A Pending JPS62240930A (en) | 1986-04-14 | 1986-04-14 | Manufacture of liquid crystal display panel |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62240930A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5643471A (en) * | 1994-11-09 | 1997-07-01 | Sharp Kabushiki Kaisha | Liquid crystal device and method for producing the same |
KR100264165B1 (en) * | 1992-07-22 | 2000-08-16 | 구본준 | Lcd device |
JP2002182222A (en) * | 2000-12-19 | 2002-06-26 | Matsushita Electric Ind Co Ltd | Method for manufacturing liquid crystal panel |
KR20030043248A (en) * | 2001-11-27 | 2003-06-02 | 소프트픽셀(주) | Manufacturing method for spacer of ferroelectric liquid crystal display |
US20220087034A1 (en) * | 2020-09-17 | 2022-03-17 | Azotek Co., Ltd. | Method of manufacturing circuit board structure |
-
1986
- 1986-04-14 JP JP61085315A patent/JPS62240930A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100264165B1 (en) * | 1992-07-22 | 2000-08-16 | 구본준 | Lcd device |
US5643471A (en) * | 1994-11-09 | 1997-07-01 | Sharp Kabushiki Kaisha | Liquid crystal device and method for producing the same |
JP2002182222A (en) * | 2000-12-19 | 2002-06-26 | Matsushita Electric Ind Co Ltd | Method for manufacturing liquid crystal panel |
KR20030043248A (en) * | 2001-11-27 | 2003-06-02 | 소프트픽셀(주) | Manufacturing method for spacer of ferroelectric liquid crystal display |
US20220087034A1 (en) * | 2020-09-17 | 2022-03-17 | Azotek Co., Ltd. | Method of manufacturing circuit board structure |
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