JPS62234297A - Program voltage supplying circuit - Google Patents

Abstract

PURPOSE:To impress a program voltage without fail by connecting the output and word line of an address decoder through a depletion type electric field effect transistor IGFET and interrupting the electric current path from a power source for writing to the power source for reading. CONSTITUTION:When address input signals A1, A2 and A3 are all a logic 1, through P channel type IGFET M1, M2 and M5 and N channel type IGFET M3, M4 and M6, the electric potential of an output point 2 comes to be the logic zero, the electric potential of an output point 2 comes to be a logic 1 and a word line WL is charged through a depletion type IGFET M8. In the writing condition, a writing signal inversion PG comes to be the logic zero, the electric potential of the word line WL rises and an FET M8 is turned off. By the electric potential, IGFET M10 and M11 are turned on, and the word line WL is charged by a power source voltage VPP for writing. Consequently, the electric current path from the voltage VPP to a power source voltage VCC for reading is interrupted and the word line WL comes to be the voltage VPP without fail.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program voltage supply circuit, and more particularly to a circuit that performs data programming by supplying a program voltage to a word line of a nonvolatile semiconductor memory element.

Semiconductor storage devices using conventional non-volatile semiconductor memory elements and programmable read-only memories (PR,
The insulated gate field effect transistor (hereinafter referred to as IGFET) is composed of an N-channel (N-ch) or a B-channel (P-ch) type insulated gate field effect transistor (IGFET) or a single-channel IGFET.

However, recently, in order to save power, the circuits for reading and writing nonvolatile semiconductor memory elements have been replaced with complementary IGFgT (
Attempts have been made to configure the system using CMO8). on the other hand,
Data writing IIK The circuit for supplying the program voltage applies the progera 4@ voltage to the word line to write data to the element. However, since this word line is connected to the output of the address decoder, the programming voltage is divided toward the address decoder, making it difficult to apply a high voltage.

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit that can supply a regular program voltage to a word line connected to a memory element.

In the present invention, the output of an address decoder and a word line are connected through a debrainyon type insulated gate field effect transistor, and the gate is controlled by the potential of this word line.
The present invention is characterized in that a circuit is provided for applying a program voltage to the word line when a selection signal from an address decoder is supplied to the word line.

Next, the present invention will be explained in detail using the drawings.

FIG. 1 shows a program voltage supply circuit connected to a three-person decoder circuit according to an embodiment of the present invention.

In the figure, P-ch type IGFgT Ml, M2. and N-ch type IGFET M3. Consists of M4 etc.

Two address input signals AI, A2 are applied 2
The output point 1 of the human-powered NAND circuit is the address input signal A1
And A2 is the argument! Only when the I Cm output power supply voltage Vcc corresponds to +5V), the logic becomes O (corresponding to the ground power supply), and when the address human input signals AI and A2 are in other logic states, the output points 1ri all become logic 1. This output point 1 is assumed to be human power, and P
-ch type IGFET M5. N-ch type IGFET M
Of the complementary logic circuits consisting of two IGF'ETs, etc., one IGFET M6 has its source grounded, and the source of the other IGFgTMs is connected to the address input signal A.
3.

Both drains are connected in common, and this is used as the output of the complementary logic circuit. Further, an IGFET M7 is provided, which has the output (output point 2) of this complementary logic circuit as its drain, address No. 4.1 A3 having the opposite logic to the address signal A3 as its gate, and its source as the ground power supply.

Next, a deblation type IGF'ET M8 is provided between the output point 2 of the complementary logic circuit and the word line WL,
This is gate-controlled by write signal PG. Furthermore, a P-ch type IGF which takes the word line WL as an input and is connected between the power supply VpI (for loading, which becomes a high voltage during writing) and the ground.
ET M9. Another complementary inverting logic circuit including an N-ch type IGFET MIQ is provided. Take the output of this circuit (output point 3) as input.

P-ch type IGFET Mll whose source is the write power supply VpI) and whose drain is connected to the word line WL
has been established. Note that the load capacitance 1tCt is a capacitance added to the word line WL. First, two address input signals AI,
Either of A2 is logic O and the potential of output point l is logic 1
If , IGFET M5 is off, IGFET M
6 is in the on state, the potential at the output point 2 becomes logic O regardless of the input state of the address input signal A3. In the read state, the ri conditioning signal PG is at the potential of the read power supply voltage Vcc, and the write phase power supply voltage Vpptd is the read power supply voltage V.
Set to the same potential as cc. For this reason, depletion u
In the M8rt read state, it is always on and the word line WL
The potential at the output point 2 becomes the ground potential, which is the same potential as the output point 2.

The time required for the potential of the word line WL to discharge from logic 1 to logic 0 is determined by IGFET M6. It is determined by the conductance gm of M8 and the load capacitance C1.

word! ! When the WL potential is determined to be logical, IGF'E
TM9 is turned on, IGFgT MIO is turned off, the potential of output point 3 becomes logic 1, and IGPI13T Ml
1 is turned off, and the current ri from the storage power supply voltage VPp to the word line WL is cut off.

In the write state, rlr, IGFET M11i write voltage +25V is applied, and the write signal PG becomes logic O, but since IGiT M8 is a depletion type, if the 1st position of output point 2 is logic 0, IGFET M8ri turns on state. Therefore, the potential of the word line Wl becomes the same as the output point 2, which is the ground α level.

Two address input signals A! , A2 are both logic 1, the potential ri of output point 1 is logic 0, IGFgT
M5 is on, IGF'ET M6 is off.

Depending on the input state of address input signal A30, word line WL
The potential of is determined. If address input signal A3 is logic 1, IGFET M7td off Vc! vinegar.

The potential of the output point 2 becomes logic 1, which is the same potential as the potential of the address input signal A3, that is, the potential of the power supply Vcc.

Since the write signal PG is logic 1 in the bladder-out state, I
GFBT M8 turns on and the word line Wl.

becomes logic 1, which is the same potential as output point 2. Word line WL
By determining the potential at logic 1, IGFgTMs is turned off, IGFET MIO is turned on, and IGFET Mll is turned on.

The time required to change the potential on word line VvL from logic O to logic 1 is determined by IGFET M5. It is determined by the conductance gm of M8 and the load capacitance C1.

In addition, in the write state, when the write signal PG becomes logic 0, +5■ and gate VcO■ are applied to the source of IGFET Ms. current path r to
The word line WL becomes the potential of the write power supply voltage Vpp. Note that the threshold voltage vT of the IGFET Ms is +5V at the source under the above conditions.

It needs to be less than -5V, a value necessary to satisfy the condition that IGFgTMs is turned off when gate ico v is applied.

To explain in detail, IGFET M5 is turned on,
When the potential of output point 2 becomes power supply voltage +5■.

7-)"iW L (i') 1[1dIGFET
It is charged through Ms and rises to a potential where IGFgT Ms turns off. The word at this time? The potential of fMWL becomes the absolute value of the threshold voltage of IGFET M8. This turns on IGFgT MIO and outputs point 3.
The potential of the word line WL decreases, the IGPFiT Mll is turned on, the potential of the word line WL is charged from the write power supply voltage VpI) and rises, and since the IGFBT Ms is off, the potential of the word line WL is charged from the write power supply voltage VpI). It is cut off, and finally becomes the potential (+25V) of the power supply voltage Vf)I) for rt4F.

Next, when output point 1 is logic O and address input signal A3 is logic 0, IGFET M7 is turned on and output point 2 becomes logic 0, so the potential of word line WL becomes logic 0.

As mentioned above, the charging and discharging time during reading is
FET M5. Ms gm, IGFET M6.

It is determined by the size of gm of Ms. In the present invention, IGF
This is because ET Ms is of the depletion type and the gate voltage is the voltage of the read power supply voltage Vcc.

The gmri of IGFgT Ms is large. Therefore, the charging/discharging time is short and high-speed operation is possible.

Furthermore, during writing, the current path from the writing power supply voltage vpp to the reading power supply voltage Vcc can be cut off by the riIGFET Ms, so the circuits necessary for reading and the circuits necessary for writing can be easily separated. can. This makes it possible to configure a circuit that requires a high-speed read operation using an IGFgT with a minimum channel length that does not require a high withstand voltage.

In the decoder circuit presented in the embodiment, since the output of output point 1 is separated into two parts according to the address input signal A3*A3, the address input signal A1. A2 2N
The AND circuit can be reduced to half the number of word line outputs.

Due to this, the IGF required to configure the decoder circuit
It becomes possible to reduce the number of ETs.

In this embodiment, the address input signal A3e is divided into two by 3, but the larger the number of divisions, such as 4 or 8, the smaller the number of IGFETs required to configure it compared to the conventional one. .

Note that in this embodiment, the read operation can be made faster by using a deblation type IGFET.

Since the current path from the word line output ri write voltage to the read voltage in the write operation is cut off, no voltage drop occurs and the stored voltage is sufficient.

The present invention has the above-mentioned advantages, and is particularly effective in designing large-capacity memories.

[Brief explanation of drawings]

FIG. 1 shows a program voltage supply circuit according to an embodiment of the present invention. In the top view, 1Ml, M2, M5, M9, Ml
1...-0・P-ch type IGFET, M3. M4.
M6. M7゜M 10---N-c h type IGFBT
%M8=...-n-ch depletion type IGFFjT
,A, ,A, ,A3. A3: Address input signal, PG: Write signal. WL...Word Thi, Vcc...
Read voltage ms voltage. Vl)ri...Writing power supply voltage, 1, 2.3.
...Output point, C1...Load capacity. ,〈τゝ1,tX Agent Patent Attorney Susumu Hara Procedural Amendment Worker

Claims (1)

[Claims] The output of the address decoder circuit is connected to a word line via a depletion type insulated gate field effect transistor, the gate is controlled by a signal on the word line, and a program voltage is applied to the word line when the word line is selected. A program voltage supply circuit comprising a circuit for applying .