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JPS6222529B2 - - Google Patents

Info

Publication number
JPS6222529B2
JPS6222529B2 JP57118938A JP11893882A JPS6222529B2 JP S6222529 B2 JPS6222529 B2 JP S6222529B2 JP 57118938 A JP57118938 A JP 57118938A JP 11893882 A JP11893882 A JP 11893882A JP S6222529 B2 JPS6222529 B2 JP S6222529B2
Authority
JP
Japan
Prior art keywords
photoresist
circuit pattern
probe card
pattern
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57118938A
Other languages
Japanese (ja)
Other versions
JPS599934A (en
Inventor
Masao Ookubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Electronic Materials Corp
Original Assignee
Japan Electronic Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Electronic Materials Corp filed Critical Japan Electronic Materials Corp
Priority to JP11893882A priority Critical patent/JPS599934A/en
Publication of JPS599934A publication Critical patent/JPS599934A/en
Publication of JPS6222529B2 publication Critical patent/JPS6222529B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Measuring Leads Or Probes (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】 本発明は半導体ウエフアーのテストに用いるプ
ローブカードの製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a probe card used for testing semiconductor wafers.

中心部に顕微鏡による観察のための穴を有する
絶縁基板にその穴を取り囲んで放射状に探針を配
設した従来形式のプローブカードは、その製造に
当たつて、上記の穴から、その下に置かれたテス
トすべき半導体ウエフアーの端子、または端子の
配列位置を画いた図形を観察しながら、探針の先
端がウエフアーの端子の配列位置に一致するよ
う、各探針の位置調整を行う必要がある。この作
業は、特に最近、ウエフアーの端子数が増大する
におよんで、ますます長時間を要する複雑な作業
となりつつあるだけでなく、このような方法で製
造されたプローブカードは、取扱い上の僅かな不
注意により探針の位置が変わり、探針位置の再調
整を要するなどの欠点や、また、ウエフアーの端
子がバンプ型の場合には、探針が滑りをおこすな
どの欠点がある。
Conventional probe cards have an insulating substrate with a hole in the center for microscopic observation and probes are arranged radially surrounding the hole. It is necessary to adjust the position of each probe so that the tip of the probe matches the arrangement position of the terminals on the wafer while observing the terminals of the placed semiconductor wafer to be tested or the diagram depicting the arrangement position of the terminals. There is. Not only is this process becoming more and more time-consuming and complex, especially as the number of terminals on wafers increases, but probe cards manufactured in this way are also subject to slight handling problems. There are also disadvantages such as the position of the probe changing due to carelessness and requiring readjustment of the probe position, and also disadvantages such as the probe tip slipping when the wafer terminal is of a bump type.

本発明は、以上のような欠点を取り除き、ウエ
フアーの端子数や、端子配列パターンの複雑性に
関係なく一定の作業工程で、ウエフアー端子への
接触片間の相対的位置関係がずれることのない、
しかも、端子がバンプ型であつても接触子に滑り
を生じない、プローブカードの製造方法を提供す
ることを目的としている。
The present invention eliminates the above-mentioned drawbacks and prevents the relative positional relationship between the contact pieces to the wafer terminals from shifting during a certain work process regardless of the number of terminals on the wafer or the complexity of the terminal arrangement pattern. ,
Moreover, it is an object of the present invention to provide a method for manufacturing a probe card in which the contacts do not slip even when the terminals are of a bump type.

以上の目的のために本発明は、弾性を有する絶
縁体上に、ウエフアーの端子とそれにつながるリ
ード部分のパターンを金属のフオトエツチング法
により形成する工程と、面上に上記パターンが形
成された絶縁体をプリント配線基板上に固着し、
上記のパターンとプリント配線との間に所定の電
気接続を行う工程から成り立つている。
For the above purpose, the present invention includes a step of forming a pattern of a wafer terminal and a lead portion connected thereto on an elastic insulator by a metal photoetching method, and an insulator having the pattern formed on the surface thereof. Fix the body onto the printed wiring board,
It consists of a process of making a predetermined electrical connection between the above pattern and printed wiring.

以下に本発明の実施例を図面に基づいて説明す
る。
Embodiments of the present invention will be described below based on the drawings.

まず、第1図に示すように、厚さ0.2mmの銅板
1にフオトレジストとして例えばコダツク社製マ
イクロレジスト752を塗り、それにテストすべ
き半導体ウエフアーの端子パターン3と、それら
を外部回路に接続するためのリード部のパターン
4とから成る回路パターンを、その部分が感光す
るように写真焼付けした後、例えばコダツク社の
マイクロレジスト・デイベロツパーで現像して回
路パターン以外の部分の不用レジストを除去す
る。
First, as shown in Figure 1, a 0.2 mm thick copper plate 1 is coated with a photoresist, such as Microresist 752 manufactured by Kodatsu, and the terminal patterns 3 of the semiconductor wafer to be tested are connected to the external circuit. After the circuit pattern consisting of the pattern 4 of the lead portion for the circuit is photoprinted so that that portion is exposed to light, it is developed using, for example, a Kodak Microresist Developer to remove unnecessary resist from portions other than the circuit pattern.

第2図はこの段階における銅板上のフオトレジ
ストの付着状態を、第1図のラインLに沿つた断
面について示している。次に銅板1の裏側より、
端子パターン部に相当する部分に、第3図に示す
ように弾性板5として厚さ2mmのゴムと、厚さ1
mmのプラスチツクの補強板6を貼付した後、銅板
1にエツチングをほどこし(第4図)、さらに、
銅表面に残留するフオトレジストをコダツク社の
マイクロレジスト除去液を用いて除去すると、第
5図に示すように、弾性板5の表面に銅の端子パ
ターンが形成される。これを斜め上方より望む斜
視図を第6図に示す。第6図において、回路パタ
ーンは銅板1のエツチングにより形成されている
わけであるが、ここでは記号1を用いず、回路パ
ターン各部に第1図の端子パターンおよびリード
部のパターンに相当して記号3(端子)および記
号4(リード)を用いている。これを第7図に示
すように、あらかじめ用意されたプリント配線基
板7の上に接着固定し、各リード部4と、プリン
ト配線基板7の所定の配線8との間に電気的接続
を行つて、本発明の製造方法によるプローブカー
ドが得られる。第8図は、第7図のラインMに沿
つた、プローブカード7の断面を示す。
FIG. 2 shows the state of adhesion of the photoresist on the copper plate at this stage in a cross section taken along line L in FIG. Next, from the back side of copper plate 1,
As shown in FIG. 3, a rubber with a thickness of 2 mm and a rubber with a thickness of 1
After pasting the plastic reinforcing plate 6 of mm in diameter, etching is applied to the copper plate 1 (Fig. 4), and further,
When the photoresist remaining on the copper surface is removed using a microresist removal solution manufactured by Kodak, a copper terminal pattern is formed on the surface of the elastic plate 5, as shown in FIG. A perspective view of this from diagonally above is shown in FIG. In Fig. 6, the circuit pattern is formed by etching the copper plate 1, but the symbol 1 is not used here, and symbols are used for each part of the circuit pattern corresponding to the terminal pattern and lead pattern in Fig. 1. 3 (terminal) and symbol 4 (lead) are used. As shown in FIG. 7, this is adhesively fixed onto a printed wiring board 7 prepared in advance, and electrical connections are made between each lead part 4 and a predetermined wiring 8 of the printed wiring board 7. , a probe card is obtained by the manufacturing method of the present invention. FIG. 8 shows a cross section of the probe card 7 along line M in FIG.

以上のように、本発明によれば、テストすべき
ウエフアーの端子への接触が、端子の数や配列パ
ターンの複雑性に関係なく、一定のフオトエツチ
ングの工程で得られ、接触子相互間にずれを生ず
ることもない。しかも、上記接触子は、弾性板に
より裏打ち保持されているので、その弾性によ
り、ウエハー端子へ圧接されるので接触点におけ
る接触電気抵抗の増加が防止しされる。また、本
発明に基づく方法で製造されたプローブカードを
用いれば、ウエフアーのテストに当たつての、接
触子とウエフアー端子との間の位置整合に際して
も、ウエフアーとプローブカードの2次元的位置
関係を一度決定しておけばよく、従来のプローブ
カードの場合のように、顕微鏡により探針とウエ
フアー端子間の接触を、各探針毎に監視、調整す
る必要がない。
As described above, according to the present invention, contact with the terminals of the wafer to be tested can be obtained through a constant photoetching process regardless of the number of terminals or the complexity of the arrangement pattern, and No deviation occurs. Furthermore, since the contactor is backed and held by an elastic plate, its elasticity allows it to be pressed into contact with the wafer terminal, thereby preventing an increase in contact electrical resistance at the contact point. Furthermore, by using the probe card manufactured by the method based on the present invention, the two-dimensional positional relationship between the wafer and the probe card can be adjusted even when aligning the positions between the contacts and the wafer terminals during wafer testing. need only be determined once, and there is no need to monitor and adjust the contact between the probe and wafer terminal for each probe using a microscope, as is the case with conventional probe cards.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例においてフオトエツチン
グすべきパターンを示す。第2図、第3図はフオ
トエツチング実施の準備過程を説明するための図
である。第4図はフオトエツチングにより弾性板
上に形成されたパターンの断面図である。第5図
および第6図は残留フオトレジストが除去され、
弾性板上に形成された銅のパターンの、それぞれ
断面図および斜視図である。第7図および第8図
はそれぞれ本実施例により製造されたプローブカ
ードの平面図および断面図である。 1…銅板、2…フオトレジスト、3…端子パタ
ーン、4…リードパターン、5…弾性板、6…補
強板、7…プリント配線基板、8…プリント配
線。
FIG. 1 shows the pattern to be photoetched in an embodiment of the invention. FIGS. 2 and 3 are diagrams for explaining the preparation process for performing photoetching. FIG. 4 is a cross-sectional view of a pattern formed on an elastic plate by photoetching. Figures 5 and 6 show that the residual photoresist has been removed;
FIG. 3 is a cross-sectional view and a perspective view, respectively, of a copper pattern formed on an elastic plate. FIGS. 7 and 8 are a plan view and a sectional view, respectively, of a probe card manufactured according to this example. DESCRIPTION OF SYMBOLS 1...Copper plate, 2...Photoresist, 3...Terminal pattern, 4...Lead pattern, 5...Elastic plate, 6...Reinforcement plate, 7...Printed wiring board, 8...Printed wiring.

Claims (1)

【特許請求の範囲】[Claims] 1 金属板の片面にフオトレジストを塗布し、テ
ストすべき半導体ウエフアーの端子パターンとそ
れら端子パターンにつながつてリード部を成すパ
ターンとから成る回路パターンを上記フオトレジ
ストに写真焼付した後、上記回路パターン以外の
部分のフオトレジストを除去し、上記金属板の、
フオトレジストを塗布しなかつた側の面に弾性を
有する絶縁板を貼付してから、上記金属板に上記
回路パターンを有する側よりエツチングをほどこ
して上記回路パターンを示す金属部分を上記絶縁
板上に残留形成させた後、金属部分表面上に残る
フオトレジストを除去し、上記絶縁板をプリント
配線基板上に固着し、上記回路パターンのリード
部を上記プリント配線基板の所定の配線に電気接
続することによつてプローブカードを形成させ
る、プローブカードの製造方法。
1. Apply photoresist to one side of a metal plate, photoprint a circuit pattern consisting of terminal patterns of the semiconductor wafer to be tested and patterns connected to these terminal patterns to form lead parts on the photoresist, and then print the circuit pattern on the photoresist. Remove the photoresist from other parts of the metal plate,
After attaching an elastic insulating plate to the side on which the photoresist is not applied, etching is applied to the metal plate from the side having the circuit pattern to place the metal part showing the circuit pattern on the insulating plate. After forming the remaining photoresist, removing the photoresist remaining on the surface of the metal part, fixing the insulating plate on the printed wiring board, and electrically connecting the lead part of the circuit pattern to the predetermined wiring of the printed wiring board. A method for manufacturing a probe card, the method comprising: forming a probe card by forming a probe card.
JP11893882A 1982-07-07 1982-07-07 Manufacture of probe card Granted JPS599934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11893882A JPS599934A (en) 1982-07-07 1982-07-07 Manufacture of probe card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11893882A JPS599934A (en) 1982-07-07 1982-07-07 Manufacture of probe card

Publications (2)

Publication Number Publication Date
JPS599934A JPS599934A (en) 1984-01-19
JPS6222529B2 true JPS6222529B2 (en) 1987-05-19

Family

ID=14748941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11893882A Granted JPS599934A (en) 1982-07-07 1982-07-07 Manufacture of probe card

Country Status (1)

Country Link
JP (1) JPS599934A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62233774A (en) * 1986-04-03 1987-10-14 Matsushita Electric Ind Co Ltd Inspecting method for circuit board
JPH0820465B2 (en) * 1990-06-29 1996-03-04 シャープ株式会社 Electrical inspection method for semiconductor device
KR100196195B1 (en) * 1991-11-18 1999-06-15 이노우에 쥰이치 Probe card
WO1995034000A1 (en) * 1994-06-03 1995-12-14 Hitachi, Ltd. Connecting device and its manufacture
JP4841298B2 (en) * 2006-04-14 2011-12-21 株式会社日本マイクロニクス Probe sheet manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5132181A (en) * 1974-09-11 1976-03-18 Matsushita Electric Ind Co Ltd Handotaisoshisokuteiyopuroobubarinoseizohoho
JPS51121267A (en) * 1975-04-17 1976-10-23 Seiko Epson Corp Semiconductor wafer measuring device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5132181A (en) * 1974-09-11 1976-03-18 Matsushita Electric Ind Co Ltd Handotaisoshisokuteiyopuroobubarinoseizohoho
JPS51121267A (en) * 1975-04-17 1976-10-23 Seiko Epson Corp Semiconductor wafer measuring device

Also Published As

Publication number Publication date
JPS599934A (en) 1984-01-19

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