JPS62222696A - Multilayer wiring board manufacturing method - Google Patents
Multilayer wiring board manufacturing methodInfo
- Publication number
- JPS62222696A JPS62222696A JP6497086A JP6497086A JPS62222696A JP S62222696 A JPS62222696 A JP S62222696A JP 6497086 A JP6497086 A JP 6497086A JP 6497086 A JP6497086 A JP 6497086A JP S62222696 A JPS62222696 A JP S62222696A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- base metal
- multilayer wiring
- metal layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000010953 base metal Substances 0.000 claims description 31
- 238000007747 plating Methods 0.000 claims description 31
- 239000004020 conductor Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 12
- 238000007772 electroless plating Methods 0.000 claims description 11
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 229910052804 chromium Inorganic materials 0.000 claims description 8
- 239000011651 chromium Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 4
- 229910052759 nickel Inorganic materials 0.000 claims 2
- 239000002344 surface layer Substances 0.000 claims 2
- 238000010030 laminating Methods 0.000 claims 1
- 239000010409 thin film Substances 0.000 description 10
- 238000005498 polishing Methods 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 5
- 239000009719 polyimide resin Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- WCUXLLCKKVVCTQ-UHFFFAOYSA-M Potassium chloride Chemical compound [Cl-].[K+] WCUXLLCKKVVCTQ-UHFFFAOYSA-M 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- YAGKRVSRTSUGEY-UHFFFAOYSA-N ferricyanide Chemical compound [Fe+3].N#[C-].N#[C-].N#[C-].N#[C-].N#[C-].N#[C-] YAGKRVSRTSUGEY-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000001103 potassium chloride Substances 0.000 description 1
- 235000011164 potassium chloride Nutrition 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高集積ＬＳＩなどを実装する多層配線基板の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a multilayer wiring board on which highly integrated LSIs and the like are mounted.
従来の多層配線基板の製造方法においては、たとえば第
３図（ａ）に示す如く、基板１の上面全面に亘ってめっ
きの電極とな如うる下地金属層２を形成し、その上面に
第３図（ｂ）に示す如く、所望の導体配線パターンの形
状に溝加工されたレジスト３を形成する。In the conventional method for manufacturing a multilayer wiring board, for example, as shown in FIG. As shown in Figure (b), a resist 3 is formed with grooves formed in the shape of a desired conductor wiring pattern.
しかるのち、第３図（Ｃ）に示す如く、露出した前記下
地金属層２を電極として電気めつき４を行ない、前記レ
ジスト３の溝を選択的に導体充填する。Thereafter, as shown in FIG. 3C, electroplating 4 is performed using the exposed base metal layer 2 as an electrode to selectively fill the grooves of the resist 3 with a conductor.
このとき、スルーホール（図示せず）も同様に形成する
。At this time, through holes (not shown) are also formed in the same way.
ついで、第３図（ｄ）に示す如く、レジスト３を除去し
て導体配線５を形成し、第３図（ｅＪに示す如く、導体
配線５に対接する以外の前記下地金属層２を除去し、第
３図（ｆ）に示す如く、基板１の上面全面に前記導体配
線５を包むように絶縁層６を形成したのち、第３図（ｇ
）に示す如く研磨などによシ前記導体配線５の上面を露
出するとともに該絶縁層６の表面を平面研磨し、以下、
前記の工程を繰返して多層配線基板を製造する方法が実
施されている。Next, as shown in FIG. 3(d), the resist 3 is removed to form a conductor wiring 5, and as shown in FIG. As shown in FIG. 3(f), an insulating layer 6 is formed on the entire upper surface of the substrate 1 so as to surround the conductor wiring 5, and then, as shown in FIG.
), the upper surface of the conductor wiring 5 is exposed by polishing or the like, and the surface of the insulating layer 6 is polished to a flat surface.
A method of manufacturing a multilayer wiring board by repeating the above steps has been implemented.
〔例、プロシーディンクス・オブ・ザ・サーチイーフォ
ース・イー・シー・シーくエレクトロニック・コンポー
ネント・コンファレンス＞（Ｐｒｏｃｅｅ−ｄｉｎｇｓ
ｏｆ ｔｈｅ ３４ｔｈ ＥＣＣ＜Ｅｌｅｃｔ
ｒｏｎｉｃ ＣｏｍｐｏｎｅｎｔＣｏｎｆｅｒｅｎｃｅ
＞ ） Ｐ ８２〜８７ Ｉ８４参照〕〔発明が解決し
ようとする問題点〕
前記の従来技術では、選択めっきをし、レジストを除去
し、下地金属層を除去したのち、全面に絶縁層を形成し
、表面研磨をすることによって導体金属を露出させると
ともに該絶縁層の表面を平面加工する工程が必要となる
。[Example: Proceedings of the Search Force Electronic Components Conference]
of the 34th ECC＜Elect
ronic ComponentConference
> ) See pages 82 to 87 I84] [Problems to be solved by the invention] In the above-mentioned conventional technology, after selective plating is performed, the resist is removed, and the base metal layer is removed, an insulating layer is formed on the entire surface. , it is necessary to expose the conductive metal by surface polishing and to planarize the surface of the insulating layer.
そのため、工程数が多くなシ、がっ基板のそシなどによ
って表面を平面加工が困難であシ、かっ平面研磨された
表面にばらつきが発生すると、それが配線抵抗のばらつ
きに反映するなどの問題がある。Therefore, it is difficult to process the surface to make it flat due to the large number of process steps, the warpage of the board, etc., and if variations occur in the polished surface, this will be reflected in the variations in wiring resistance. There's a problem.
本発明は、前記従来技術の問題を解決し、大幅に工程数
を減少するとともに表面研磨を不要にして製造の容易化
を可能とする多層配線基板の製造方法を提供することに
ある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a multilayer wiring board that solves the problems of the prior art, greatly reduces the number of steps, and eliminates the need for surface polishing to facilitate manufacturing.
Ｃ問題点を解決するための手段〕
前記の目的は、導体配線を形成する場合、該導体配線を
形成する面に所望の配線パターン形状と略同形状にター
ニングされた下地金属層を形成する工程と、絶縁層を全
面に形成する工程と、前記絶縁層を前記所望の配線パタ
ーン形状に溝加工して前記下地金属層を露出させる工程
と、前記露出された下地金属層をめっき下地層として前
記溝加工された絶縁層をめっきレジストとして無電解め
っきして導体配線を形成する工程にて形成することによ
シ達成される。Means for Solving Problem C] The above object is a process of forming a base metal layer turned into substantially the same shape as the desired wiring pattern shape on the surface on which the conductor wiring is to be formed. forming an insulating layer on the entire surface; forming grooves in the insulating layer into the desired wiring pattern shape to expose the base metal layer; and using the exposed base metal layer as a plating base layer. This is achieved by forming conductor wiring by electroless plating using a grooved insulating layer as a plating resist.
導体配線を無電解めっきで形成する場合、めつきの下地
金属層は導通がとれている必要がないので、めっきに先
き立ってパターニングすることが可能である。When the conductor wiring is formed by electroless plating, the base metal layer for plating does not need to be electrically conductive, so it is possible to pattern it prior to plating.
しだがって、めっきを行なったのちにめっきレジストを
除去し、めっきの下地金属を除去する工程が不要となる
ので、溝加工された絶縁層にめっきレジストとしての機
能を兼ねさせることができ、これによってめっきを行な
うことができる。Therefore, it is not necessary to remove the plating resist after plating and remove the underlying metal for plating, so the grooved insulating layer can also function as a plating resist. This allows plating to be performed.
また、めっきの厚さを前記絶縁層の厚さと一致させるこ
とによシ表面研磨工程が不要となる。Further, by making the thickness of the plating match the thickness of the insulating layer, a surface polishing step is not necessary.
さらに、前記めっきの下地金属層は無電解めっき液に対
して活性であれば、その種類を問わず、すでに形成され
ているめっき層でもよい。Further, the base metal layer for plating may be an already formed plating layer, regardless of its type, as long as it is active against an electroless plating solution.
ただし、ある種の金属をめっきの下地金属層とした場合
には、め１つき液に浸したとき、該めっきの下地金属層
からめつきレジストである絶縁層が剥離することがある
。そのさいには、前記めっき下地金属層を２種以上の金
属層状構造とし、めっきの下地金属層として使用する一
方の金属は内層に、前記剥離を発生させないための他方
の金属を最表面層すなわち絶縁膜に接する層に形成する
。However, when a certain type of metal is used as the base metal layer for plating, the insulating layer, which is a plating resist, may peel off from the base metal layer for plating when immersed in a plating solution. In that case, the plating base metal layer has a layered structure of two or more metals, one metal used as the plating base metal layer is an inner layer, and the other metal is the outermost layer to prevent peeling. Formed in a layer in contact with the insulating film.
なお、前記他方の金属は無電解めっき液に対して不活性
であってもよい。Note that the other metal may be inert to the electroless plating solution.
ついで、絶縁層を形成し、該絶縁層を溝加工して前記下
地金属層を露出させたのち、前記溝加工された絶縁層を
めっきレジストとして無電解めっきを行なうことによシ
、前記めっきの下地金属層から前記絶縁層を剥離するこ
となく導体配線を形成することができる。Next, an insulating layer is formed, grooves are formed in the insulating layer to expose the base metal layer, and electroless plating is performed using the grooved insulating layer as a plating resist. Conductive wiring can be formed without peeling off the insulating layer from the base metal layer.
以下、本発明の一実施例である第１図（ａ）〜（ｅ）に
よシ説明する。Hereinafter, an embodiment of the present invention will be explained with reference to FIGS. 1(a) to 1(e).
実施例１
第１図（ａ）に示す如く、基板１上に銅薄膜からなる下
地金属層２を形成したのち、第１図（ｂ）に示す如く、
ドライエツチングなどで前記下地金属層２を所望の導体
配線パターンと略同形状にし、溝加工されたポリイミド
系樹脂よシなる絶縁層６−□を形成する。Example 1 After forming a base metal layer 2 made of a thin copper film on a substrate 1 as shown in FIG. 1(a), as shown in FIG. 1(b),
The base metal layer 2 is made into substantially the same shape as the desired conductor wiring pattern by dry etching, etc., and an insulating layer 6-□ made of polyimide resin with grooves is formed.
ついで、第１図（Ｃ）に示す如く、前記下地金属層２上
に前記溝加工されたポリイミド系樹脂よりなる絶縁層６
−１をめっきレジストして選択的に無電解銅めっきを行
なって銅めつき層１０を形成し、導体配線５を形成する
。Next, as shown in FIG. 1(C), the grooved insulating layer 6 made of polyimide resin is formed on the base metal layer 2.
-1 as a plating resist and selectively performs electroless copper plating to form a copper plating layer 10 and conductor wiring 5.
しかるのち、第１図（ｄ）に示す如く、スルーホールを
形成するため、前記導体配線５と略同形状すなわち所望
のスルーホールパターン形状よシも広くパターニングさ
れたクローム薄膜７−２を形成し、ドライエツチングな
どで所望のスルーホールパターン１１を形成する。Thereafter, as shown in FIG. 1(d), in order to form through holes, a chrome thin film 7-2 is formed which is patterned to have approximately the same shape as the conductor wiring 5, that is, to have a desired through hole pattern shape. , a desired through-hole pattern 11 is formed by dry etching or the like.
ついで第１図（ｅ）に示す如く、前記絶縁層６−２をレ
ジストとして前記クロム薄膜７−２を前記エツチング液
で選択的にエツチングして前記下地金属２を露出させ、
露出した前記下地金属２上に前記絶縁層６−２をめっき
レジストとしてスルーホール１１部に無電解めっきを行
ない、接続部ルを形成した。Then, as shown in FIG. 1(e), using the insulating layer 6-2 as a resist, the chromium thin film 7-2 is selectively etched with the etching solution to expose the base metal 2,
Electroless plating was performed on the exposed base metal 2 using the insulating layer 6-2 as a plating resist on the through hole 11 portion to form a connection portion.
以下、上記の工程を繰返すことによシ多層配線基板を製
造することができる。Thereafter, a multilayer wiring board can be manufactured by repeating the above steps.
実施例２
つぎに本発明の他の一実施例である第２図（ａ）〜（ｆ
）によシ説明する。Embodiment 2 Next, FIGS. 2(a) to 2(f) which are another embodiment of the present invention are shown.
) to explain.
第２図（ａ）に示す如く、基板１上にクロム薄膜７−１
銅薄膜８およびクロム薄膜９の順に全面蓋着して下地金
属２を形成する。As shown in FIG. 2(a), a chromium thin film 7-1 is formed on the substrate 1.
The copper thin film 8 and the chromium thin film 9 are covered in this order to form the base metal 2.
ついで、第２図（ｂ）に示す如く、ドライエツチングな
どで下地金属２を所望の導体配線ノくターンと略同形状
にし、溝加工されたポリイミド系樹脂よシなる絶縁層６
−□を形成する。Next, as shown in FIG. 2(b), the base metal 2 is made into a shape approximately the same as the desired conductor wiring turn by dry etching, etc., and a grooved insulating layer 6 made of polyimide resin is formed.
- form □.
しかるのち、第２図（Ｃ）に示す如く、前記溝加工され
たポリイミド系樹脂よりなる絶縁層６−□をレジストし
て前記下地金属層２の最表面層のクロム薄膜７−□をフ
ェリシアン化カリ／水酸化カリ溶液で選択的にエツチン
グする。Thereafter, as shown in FIG. 2(C), the grooved insulating layer 6-□ made of polyimide resin is resisted, and the chromium thin film 7-□ on the outermost surface of the base metal layer 2 is coated with ferricyanide. Selective etching with potassium chloride/potassium hydroxide solution.
ついで、第２図（ｄ）に示す如く、内層である前記銅薄
膜８上に前記溝加工されたポリイミド系樹脂よシなる絶
縁層６−０をめつきレジストとして選択的に無電解めっ
きを行なって銅めっき層１０を形成し、導体配線５を形
成する。Next, as shown in FIG. 2(d), electroless plating is selectively performed on the copper thin film 8, which is the inner layer, using the grooved insulating layer 6-0 made of polyimide resin as a plating resist. Then, a copper plating layer 10 is formed, and a conductor wiring 5 is formed.
以下は前記実施例１と同様な方法によシ第２図（ｅ）お
よび第２図（ｆ）に示す如くスルーホールを形成したの
ち、前記の工程を繰返すことによシ多層配線基板を製造
することができる。In the following, a multilayer wiring board was manufactured by forming through holes as shown in FIG. 2(e) and FIG. 2(f) in the same manner as in Example 1, and then repeating the above steps. can do.
したがって本発明による多層配線基板の製造方法によれ
ば従来に比較して大幅に工程数を減少することができ、
かつ表面研磨を不要とすることができるので、容易に多
層配線基板を製造することができる。Therefore, according to the method for manufacturing a multilayer wiring board according to the present invention, the number of steps can be significantly reduced compared to the conventional method.
Moreover, since surface polishing can be made unnecessary, a multilayer wiring board can be manufactured easily.
以上述べたる如く、本発明によれば、従来に比較して大
幅に工程数を減少することができ、かつ表面研磨を不要
とすることができるので、容易に多層配線基板を製造す
ることができる。As described above, according to the present invention, the number of steps can be significantly reduced compared to the conventional method, and surface polishing can be made unnecessary, making it possible to easily manufacture a multilayer wiring board. .
第１図（ａ）〜（ｅ）は本発明の一実施例である多層配
線基板の製造工程図、第２図（ａ）〜（ｆ）は本発明の
他の一実施例である多層配線基板の製造工程図、第３図
（ａ）〜（ｇ）は従来の多層配線基板の製造工程図であ
る。
１・・・基板、２・・・下地金属、５・・・導体配線、
６−４゜６−２・・・絶縁層、７−□、７−２・・・ク
ロム薄膜、８・・・銅薄膜、９・・・クロム薄膜、１ｏ
・・・銅めっき層、１１・・・溝、ル・・・接続部。
代理人 弁理士 秋 本 正 実
γ−２クロム簿甲匍、 ｔｏ 鋸めり、４４． １
１ ４． ７２ 牛か瘤乞音戸。
第 ２ 図
第 ３ 区
ｂ−１把稀肩
手続省口正書（自発）
昭和６２年２月５１６日Figures 1 (a) to (e) are manufacturing process diagrams of a multilayer wiring board that is an embodiment of the present invention, and Figures 2 (a) to (f) are multilayer wiring diagrams that are another embodiment of the present invention. 3(a) to 3(g) are manufacturing process diagrams of a conventional multilayer wiring board. 1... Board, 2... Base metal, 5... Conductor wiring,
6-4゜6-2...Insulating layer, 7-□, 7-2...Chromium thin film, 8...Copper thin film, 9...Chromium thin film, 1o
...Copper plating layer, 11...Groove, Ru...Connection part. Agent Patent Attorney Tadashi Akimoto Real γ-2 Chrome Book Armor, to saw mill, 44. 1
1 4. 72 Cow or lump beg Ondo. Figure 2, Figure 3, Section b-1, Ministry of Foreign Affairs official document (spontaneous), February 516, 1988.
Claims (1)
線基板の導体配線を形成する多層配線基板の製造方法に
おいて、前記導体配線を形成する面に所望の配線パター
ン形状と略同形状にパターニングされた下地金属層を形
成する工程と、少なくとも前記下地金属層以外に絶縁層
を形成する工程と、前記絶縁層をめつきレジストとして
前記下地金属層上に無電解めつきを行なつて前記導体配
線を形成する工程とからなることを特徴とする多層配線
基板の製造方法。 ２、基板上に導体層と絶縁層とを交互に積層して多層配
線基板の導体配線を形成する多層配線基板の製造方法に
おいて、前記導体配線を形成する面に所望の配線パター
ン形状と略同形状にパターニングされた少なくとも２種
からなる下地金属層を形成する工程と、少なくとも前記
下地金属層上以外に絶縁層を形成する工程と、前記下地
金属層をエッチングして無電解めつきの下地層となり得
る金属が露出するまでエツチングする工程と、前記絶縁
層をめつきレジストとして前記の露出した金属層上に無
電解めつきを行なつて前記導体配線を形成する工程とか
らなることを特徴とする多層配線基板の製造方法。 ３、前記絶縁層は有機系絶縁層で形成されていることを
特徴とする特許請求の範囲第１項または第２項記載の多
層配線基板の製造方法。 ４、前記無電解めつきは無電解銅めつきであることを特
徴とする特許請求の範囲第１項または第２項記載の多層
配線基板の製造方法。 ５、前記下地金属層はその最表面層がクロム・ニッケル
のうちいずれか一種で形成されていることを特徴とする
特許請求の範囲第１項または第２項記載の多層配線基板
の製造方法。 ６、前記下地金属層はその最表面層がクロム・ニツケル
のうちいずれか一種で形成され、かつ前記無電解めつき
は無電解銅めつきであることを特徴とする特許請求の範
囲第１項または第２項記載の多層配線基板の製造方法。[Scope of Claims] 1. A method for manufacturing a multilayer wiring board in which a conductor layer and an insulating layer are alternately laminated on a substrate to form conductor wiring of a multilayer wiring board, in which a desired surface is formed on the surface on which the conductor wiring is to be formed. A step of forming a base metal layer patterned in substantially the same shape as the wiring pattern shape, a step of forming at least an insulating layer other than the base metal layer, and a step of forming a base metal layer on the base metal layer using the insulating layer as a plating resist. A method for manufacturing a multilayer wiring board, comprising the step of forming the conductor wiring by electrolytic plating. 2. In a method for manufacturing a multilayer wiring board in which conductor wiring of a multilayer wiring board is formed by alternately laminating conductor layers and insulating layers on a substrate, the surface on which the conductor wiring is to be formed has a shape that is approximately the same as the desired wiring pattern shape. a step of forming a base metal layer consisting of at least two types patterned into a shape; a step of forming an insulating layer at least on a portion other than the base metal layer; and a step of etching the base metal layer to become a base layer for electroless plating. and a step of performing electroless plating on the exposed metal layer using the insulating layer as a plating resist to form the conductor wiring. A method for manufacturing a multilayer wiring board. 3. The method of manufacturing a multilayer wiring board according to claim 1 or 2, wherein the insulating layer is formed of an organic insulating layer. 4. The method for manufacturing a multilayer wiring board according to claim 1 or 2, wherein the electroless plating is electroless copper plating. 5. The method for manufacturing a multilayer wiring board according to claim 1 or 2, wherein the outermost surface layer of the base metal layer is formed of one of chromium and nickel. 6. Claim 1, wherein the outermost surface layer of the base metal layer is formed of one of chromium and nickel, and the electroless plating is electroless copper plating. Alternatively, the method for manufacturing a multilayer wiring board according to item 2.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6497086A JPS62222696A (en) | 1986-03-25 | 1986-03-25 | Multilayer wiring board manufacturing method |
| US07/281,879 US4963512A (en) | 1986-03-25 | 1988-12-08 | Method for forming conductor layers and method for fabricating multilayer substrates |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6497086A JPS62222696A (en) | 1986-03-25 | 1986-03-25 | Multilayer wiring board manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62222696A true JPS62222696A (en) | 1987-09-30 |
| JPH0587038B2 JPH0587038B2 (en) | 1993-12-15 |
Family
ID=13273412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6497086A Granted JPS62222696A (en) | 1986-03-25 | 1986-03-25 | Multilayer wiring board manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62222696A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011076386A (en) * | 2009-09-30 | 2011-04-14 | Hosiden Corp | Capacitance type touch panel and method for producing the same |
-
1986
- 1986-03-25 JP JP6497086A patent/JPS62222696A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011076386A (en) * | 2009-09-30 | 2011-04-14 | Hosiden Corp | Capacitance type touch panel and method for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0587038B2 (en) | 1993-12-15 |
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