JPS6222177A - Digital signal processor - Google Patents

Abstract

PURPOSE:To speed up a processing by providing the same number of accumulating registers as the number of stages of pipe lines. CONSTITUTION:The same or more number of accumulating registers A<2> and B<3> as that of stages of pipe lines are provided, and an arithmetic and logic operation circuit 1 executes partially an operation in parallel separating it into N-number of times according to the N-number of states of the pipe lines. The result of the operation is stored in order at the N-number of the accumulating registers A<2> and B<3>. Lastly, a final output is generated with adding the content of each of accumulating registers A<2> and A<3>. Thus, so that a sum of products operation is executed by every supplying of multiplication result, a filter operation can be executed efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an arithmetic device that performs a product-sum operation in a digital signal processing device.

(Prior Art) Digital signal processing equipment that performs digital signal processing such as digital filters and FFT (Fast Fourier Transform) employs a special configuration in order to efficiently realize product-sum operations that frequently appear in digital signal processing algorithms. 9-ru. The conventional structure is, for example, Transactions of the Institute of Electronics and Communication Engineers (D), Vol.
J6G-C, No. 12, published December 1983, Hirohisa Karube et al., "High-speed Digital Signal Processing LSI, 4 pages 943-
950, which will be explained with reference to FIG.

In Fig. 3, 10.20 is the input register of the multiplier, 30 is the register that stores the multiplication result, and 40 is the accumulation register that stores the output of the arithmetic and logic circuit.In conventional digital signal processing devices, there is usually only one. have.

50 is a parallel multiplier, and 60 is an arithmetic and logic operation circuit that performs an operation between the multiplication result and the accumulation register.

A method for realizing the digital filter shown in FIG. 2 in an apparatus having such a configuration will be described.

The calculation formula for the filter shown in FIG. 2 is given by formula (1).

When formula (1) is realized by a digital signal processing device.

Transform equation (1) into the following equation.

yn←0(2) yn←yn+αtXn-+(3) (Do this for i values 0 to 5) By assigning the accumulation register 40 as yn in FIG. By performing the addition between the
) can be executed in one instruction cycle, and the final y is obtained by repeating equation (3) six times. can be found.

In conventional digital signal processing devices, the number of logic stages in the arithmetic and logic circuit is small because the fixed-point format is used as the data format.For this reason, the time required to execute one instruction cycle when performing a multiply-accumulate operation is It was determined by the multiplication time of parallel multipliers.

(Problems to be Solved by the Invention) However, in the device having the above configuration, when a floating point format is adopted for data formation in order to expand the dynamic range of the signal, the number of logic stages of the arithmetic and logic operation circuit increases significantly. The factor that determines the time for one instruction cycle changes from the conventional multiplier to the arithmetic logic circuit. For this reason, the time for one instruction cycle increases compared to the fixed-point format, which results in deterioration of the performance of the digital signal processing device.

In order to prevent this performance deterioration, it is conceivable to use a pipeline system consisting of multiple stages of the arithmetic and logic operation circuit, but in this case, in order to obtain the result of equation (3), the number of processing steps equal to the number of pipeline stages is required. In addition, if only one accumulation register is provided as in the conventional configuration, (
3) A process that requires the immediately previous execution result, such as an expression, has the disadvantage that the immediately previous result is used, which reduces the efficiency of pipelining.

The present invention aims to improve the above-mentioned drawbacks of the prior art.

(Means for Solving the Problems) A feature of the present invention for achieving the above object is that, in a digital signal processing device that performs an M-sum operation, an N-stage (N22) Vibration type arithmetic logic operation circuit; and at least N accumulation registers for accumulating outputs of the circuit, and each time a value is given from the outside, the arithmetic and logic operation circuit sequentially performs an operation between the value and the output value of each of the registers,
The digital signal processing device includes means for providing the sum of the outputs of the respective registers as the final result.

(Function) In the above configuration, the arithmetic logic operation circuit partially divides the operation into N times according to the number of stages N of the pipeline, executes each operation in parallel, and the result of the operation is divided into N times for accumulation. Stored sequentially in registers.

Therefore, each time the arithmetic and logic operation circuit receives an input value from the outside, it performs an operation on the human input value and the immediately preceding contents of each accumulation register, and stores the result in each accumulation register. Finally, the contents of each accumulation register are added and the result is the final output.

As described above, by providing accumulation registers equal to the number of pipeline stages, it is possible to achieve the effect of pipelining and improve processing speed.

(Example) FIG. 1 shows an embodiment of an arithmetic device according to the present invention.

In FIG. 1, 1 is an arithmetic logic operation circuit (A r ith
It has a two-stage pipeline configuration with a pipeline register 9 inserted in the middle.

Reference numeral 2.3 is an accumulation register for storing the output of ALt), and these are hereinafter referred to as accumulation register A and accumulation register B, respectively. 4 is an input register serving as six inputs of the ALU. Reference numeral 5 denotes a selector for selecting the input to the manual register, and either the multiplier output or the accumulation register output is selected depending on the instruction. 6 is a selector for selecting the output of the accumulation register.

7 is the output bus of the ALU and is connected to the power of the accumulation register 2.3.

8 is an output bus of the accumulation register and is connected to the ALU B input and the input of the selector 5.

The operation of this apparatus will be described below using the digital filter shown in FIG. 2 as an example.

The digital filter in FIG. 2 is calculated using the following equation.

Here, equation (1) is transformed to obtain the following equation.

That is, yn is divided into two groups, yn' with an even number of delays and yn'' with an odd number of delays, and is expressed as the sum of both.

The calculation formula when formula (3) is executed in this device is shown below.

3/ n ”-'I n' + yn-(4-9) (4
) calculation process will be explained using FIG.

It is assumed that an accumulation register A+ is used for accumulating yn'' and an accumulation register B is used for accumulating yn, and each register is cleared to 0.

The input register receives the multiplication result α from the multiplier. xn.

αI Xn −1+ ”” + α5Xn−6,
Even and odd delays are alternately supplied for each instruction cycle.

α in the input register in the first step. xn is set and the formula (4-3) becomes executable, so in the second step the selector 6 selects the accumulation register A side (yn') and performs the addition (3/3) of the accumulation register and the input register. n'+α
oxn).

In the third step, y' specified in the second step.

+α. Since the value of Xn is obtained, it is stored in the accumulation register A.
Store in.

Also, in the second step, α, Addition with input register (yn”+α1Xn
-1).

In the fourth step, yn“+αl specified in the third step
Since the value of x, , is obtained, it is stored in the accumulation register B. Also, in the third step, new Xn゛ and α2
x, -, are accumulation registers A, respectively.

Since it is obtained in the input register, equation (4-4) can be executed, the selector 6 selects the accumulation register A, and the ALU performs addition between the accumulation register A and the manual register.

In this way, by dividing equation (1) into equation (3), Yn
By alternating the accumulation of `` and y.'', the ALU
The product-sum operation can be performed every time a multiplication result is supplied.

As shown in FIG. 4, the final value of yn' is determined in the accumulation register A in the seventh step, and the value Yn'' is determined in the accumulation register B in the eighth step.

Therefore, in the eighth step, the selector 6 selects the accumulation register A, and the selector 5 selects the accumulation register side.
Set Yno in the input register.

Next, in the ninth step, input register and accumulation register B
Finally, yn can be obtained by performing addition between .

By having a means to transfer the value of the cumulative H4 register to the input register in this way, it is possible to accumulate between the cumulative registers, and as a result, even when formula (1) is divided, The final group is obtained by summing each term.

Above, we have talked about a two-stage ALU, but
In general, in the case of an ALU that uses a j-stage pipeline system, the sum of products is divided into j partial sums of products, as shown in equation (5), and the accumulation of each term is calculated in advance by a cumulative sum of j or more parts. Assign to register.

Even in this case, the multiplication result is α. xn, αI Xn-t −
If '-' is supplied, a product-sum operation can be executed each time a multiplication result is supplied, and the final y, , can be obtained by summing each partial sum.

In this way, by providing accumulation registers equal to or greater than the number of pipeline stages of ALLI and having a means for calculating the sum of the accumulation registers, even when ALLI is a pipeline system, the product-sum operation can be performed using the multiplication result. The filter calculation can be performed every time the filter calculation is performed, and the filter calculation can be performed efficiently.

(Effects of the Invention) As described in detail above, according to the present invention, the following effects can be obtained.

(1) Even when the arithmetic and logic circuit is of a pipeline type, the product-sum operation can be executed every time a multiplication result is supplied.

For example, when executing an N-tap transversal filter with a two-stage pipeline^LU, if there is only one conventional accumulation register, pipelining does not have the effect of waiting for the calculation result, and the number of steps is reduced to 2N steps. In contrast, the method according to the present invention requires only N+3 execution steps because the product-sum operation can be executed for each cycle. As a result, the effect of the present invention becomes more significant as the number of taps increases.

(2) Even when the arithmetic logic circuit is pipelined, filter operations can be executed efficiently;
Even when arithmetic and logic circuits handle floating-point format data, the instruction cycle time is approximately the same as or less than the time required for one instruction cycle in the conventional fixed-point format, and digital signal processing equipment performance can be improved both in terms of speed and dynamic range.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the arithmetic device according to the present invention, FIG. 2 is a diagram showing a digital filter, FIG. 3 is a block diagram showing a conventional digital signal processing device, and FIG. 4 is a block diagram showing an embodiment of the arithmetic device according to the present invention. FIG. 3 is an explanatory diagram for explaining the operation of one embodiment of the arithmetic device. 1 is a two-stage pipeline arithmetic logic circuit, 2-lobe accumulation register A, 3 is accumulation register B, 4 is input register of 1, 5 and 6 are selectors, 7.8 is bus,
10, 20, 30 are registers, 40 is an accumulation register, 50 is a parallel multiplier, and 60 is a non-pipelined arithmetic logic circuit. ,,v 夾 lol! ! +=zg*fern,bayy'1ahpt
uFigure 1

Claims (2)

[Claims] (1) A digital signal processing device that performs a product-sum operation, comprising an N-stage (N≧2) pipelined arithmetic and logic circuit, and at least N accumulation registers that accumulate the outputs of the circuit. , the arithmetic and logic operation circuit is characterized in that each time a value is given from the outside, the arithmetic and logic operation circuit sequentially performs an operation between the value and the output value of each of the registers, and means is provided for providing the sum of the outputs of each of the registers as the final result. A digital signal processing device. (2) The digital signal processing device according to claim 1, wherein the means for providing the sum of the respective registers is the arithmetic and logic operation circuit.