JPS62219558A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit '3A device, and in particular improves the electrical reliability of a conductive layer having a high melting point metal film or its silicide film. It is related to the technology to

[Conventional technology]

The first conductive layer such as the gate electrode of MISFET is M
A technology for forming high melting point metals such as O, W, Ta, and Ti or their silicide films was published by Nikkei McGraw-Hill in 1983.
It is described in "Nikkei Electronics Special Issue R Micro Devices" published on August 22, 2008, p. 119.

[Problem that the invention seeks to solve]

The inventor of the present invention discovered the following problems as a result of experiments and studies on the conductive layer having the high melting point metal film or its silicide film.

The conductive layer is damaged by ion implantation when forming the source and drain regions of the MISFET, and a damaged layer is formed on the upper surface of the conductive layer. When a polycrystalline silicon film and an aluminum film are connected to this damaged conductive layer, an abnormal reaction occurs at the contact area between the high melting point metal film or silicide film and the aluminum film, and this abnormality occurs. The reaction significantly increases the contact resistance between the high melting point metal film or silinide film and the polycrystalline silicon film.

Additionally, damage and contamination occur due to plasma etching during sidewall spacer formation.

Therefore, in a two-layer film in which the high-melting point metal film or silicide film is provided on a polycrystalline silicon film, abnormal oxidation occurs when the two-layer film is oxidized, and the high-melting point metal film or silicide film is There is also the problem of peeling off from the crystalline silicon film.

An object of the present invention is to improve the electrical reliability of a conductive layer on a semiconductor substrate.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

That is, a protective film is provided on both sides of the high melting point metal film or the silicide film of the high melting point metal during ion implantation or etching.

[Effect]

According to the above means, the electrical reliability of the electrically conductive layer is improved because the electrically conductive layer is not damaged or contaminated.

[Example ■]

First, the configuration of the MTSFET in this example will be explained.

Figure 1 is a plan view of the MISFET, Figure 2 is A- in Figure 1.
3 is a sectional view taken along section line A, FIG. 3 is a sectional view taken along section line B--B in FIG. 1, and FIG. 4 is a sectional view taken along section line C--C in FIG. 1. Note that in order to make it easier to see the configuration of the MISFET, Figure 1 shows the field insulating film and gate 1.
~Electrode'' Insulating films other than those on the two sides are not shown.

In FIGS. 1 to 4, ■ is a semiconductor substrate made of p-type single crystal silicon, 2 is a P-well region, 3 is an N-well region, 4 is a field insulating film made of silicon oxide film, and 5 is a P-type This is a channel stopper area. Two N-channel MISFETs are shown in P-well region 2, and one P-channel MTSFET is shown in N-well region 3. The N-channel MISFET includes a gate insulating film 6 made of a silicon oxide film surrounded by a field insulating film 4;
n-type semiconductor regions 7A and r which are source and drain regions
It consists of an r-type semiconductor region 7B, a polycrystalline silicon film 8A doped with an n-type impurity such as phosphorus, and a gate electrode 8 made of a tungsten silicide film 8B deposited thereon.

The P-channel MTSFET has an insulating film 6. It is composed of a p-type semiconductor region 18 which is a source and drain region, and a gate electrode 8 having a structure similar to that of an N-channel MTSFET. Note that the tungsten silicide [8B of the electron t, ia] may be a high melting point metal such as MOlW, Ta, or Ti, or a silicide film thereof. Further, the gate electrode 8 may be formed using only the high melting point metal film or the high melting point metal silicide.
may be configured.

=4-9 is an insulating film made of a silicon oxide film or a silicon nitride film, and has a thickness of about 300 to 500 layers. The insulating film 9 is deposited on the upper surface of the tungsten silicide film 8 and extends in the same pattern as the tungsten silicide film 8B. The insulating film 9 serves as a damage prevention film during ion implantation to form the n″″ type semiconductor region 7B, which is part of the source and drain regions of the N-channel MISFET, and also serves as a damage prevention film during ion implantation to form the n″″ type semiconductor region 7B, which is a part of the source and drain regions of the N-channel MISFET. The n-type impurity in 8A, such as phosphorus, diffuses into the external atmosphere (out-of-us-1on).
This is to prevent this from happening.

In this way, the insulating film 9 made of a silicon oxide film or a silicon nitride film is provided on the upper surface of the tungsten silicide film 8B, and the insulation film 9 (A) for forming the n4 type semiconductor region 7B is formed.
The tungsten silicide film 8B is prevented from being damaged by the ion implantation in step s). That is, in the conductive layer 17A made of an aluminum layer and the conductive layer 14 made of a polycrystalline silicon film connected to the tungsten silicide film 8B of the same goo 1 to electrode 8, an abnormal reaction between the tungsten silicide film 8B and the aluminum layer 17A is caused. By preventing the tungsten silicide film 8B
This prevents an increase in contact resistance or poor conduction of the polycrystalline silicon film 14.

Etching stoppers 10 made of a polycrystalline silicon film or an amorphous silicon film are further provided on both sides of the insulating film 9. The etching stopper 10 is attached to the insulating film 9 and extends in the same pattern as the insulating film 9, that is, the same pattern as the tungsten silicide film 8B. The etching stopper 10 serves as an end point detection film during reactive ion etching that forms the sidewall spacer 11.

The side wall spacer 11 is formed by, for example, plasma CVD.
or a silicon oxide film formed by CVD, including a polycrystalline silicon film 8A, a tungsten silicide film 8B, and an insulating film 9.
, is attached to the side surface of the etching stopper 10 and extends in the same direction as the gate electrode 8.

The conductive layer 14 is made of a second layer of polycrystalline silicon film,
N of one of the N-channel MISFETs shown
Gating of channel MISFET [i8 is connected to the upper surface of i8, that is, the upper surface of tungsten silicide film 8B, through a connection hole 13 formed by selectively removing an insulating film 12 made of a silicon oxide film. The conductive M14 contains n such as phosphorus.
Type impurities are introduced. The conductive layer 14 connects the resistive element 14A formed integrally with the conductive layer 14 to the N-channel MISFE.
It is connected to the gate electrode 8 of T. The end of the conductive layer 14 opposite to the side connected to the gate electrode 8 is connected to the power supply potential V.
CC is connected to the 5V terminal, for example. A conductive layer 17A made of an aluminum film is connected to the goo 1-electrode 8 to which the conductive layer 14 is connected through the connection hole 16. The conductive layer 17A is another N-channel MIS different from Mataki.
The conductive layer 17A is connected to the rl" type semiconductor region 7B, which is a part of the drain region of the FET, through a connection hole 16. Furthermore, the conductive layer 17A is connected to the P"" type semiconductor region 18, which is a part of the drain region of the P-channel MISFET, through a connection hole. The conductive layers 17B, 17G, and 17D made of an aluminum layer are connected through predetermined connection holes 16 to the wedge-shaped semiconductor region 7B, which is part of the source and drain regions of the N-channel MISFET. Further, the conductive layer 17E made of an aluminum layer is connected to the tungsten silicide film 8B of the gate electrode 8 which is integrally formed by the P-channel MISFET and the N-channel MISFET.
on the top surface.

The connection is made through the connection hole 16. P channel MISF
A conductive layer 17F made of an aluminum layer is connected to a P'''' type semiconductor region 18, which is a source region of the ET, through a connection hole 16.

Reference numeral 12 denotes an insulating film, which is made of, for example, a silicon oxide film produced by plasma CVD. Reference numeral 15 denotes an insulating film, which is composed of a two-layer film formed by laminating, for example, a silicon oxide film formed by plasma CVD and a phosphosilicate glass (PSG) film on top of the silicon oxide film.

Next, the specific manufacturing process of the MI S FET of this example will be explained.

5 to 16 are cross-sectional views in the manufacturing process of MISFET, and the right side of FIGS. , the left figure is a sectional view of the same part as the line BB in FIG. 1 during the manufacturing process.

As shown in FIG. 5, by a well-known technique, P
Well area 2. N-well region 3 shown in FIGS. 1 and 4. Field insulating film 4 consisting of a silicon oxide film formed by oxidizing the surface of the substrate 1. A gate insulating film 6 made of a silicon oxide film formed by oxidizing the surface of the substrate 1 exposed from the P-type channel stopper region 5 and the field insulating film 4 is formed, respectively.

Next, a polycrystalline silicon film 8A is formed on the entire surface of the substrate l by, for example, CVD.
An n-type impurity such as phosphorus is introduced by thermal diffusion, ion implantation, or the like. Next, a tungsten silicide film 8B is formed over the entire surface of the polycrystalline silicon film 8A by, for example, CVD. Note that instead of the tungsten silicide film 8B,
A film of a high-melting point metal such as MO, W, Ta, or Ti may be formed by sputtering or CVD, or a silicide film of the above-mentioned high-melting point metal may be formed.

Next, as shown in FIG. 6, an insulating film 9 made of a silicon oxide film or a silicon nitride film is formed on the entire upper surface of the tungsten silicide film 8B by, for example, low-temperature CVD (1, PCVD). Form thick. The insulating film 9 is made of arsenic (
It is a damage prevention film for the tungsten silicide film 8B during ion implantation in A, s), and is an out-di layer for n-type impurities such as phosphorus (P) in the polycrystalline silicon film 8A.
It is an anti-ffusion film.

Next, as shown in FIG. 7, an etching stopper layer 10 made of a polycrystalline silicon film or an amorphous silicon film is formed on the entire upper surface of the insulating film 9 by, for example, CVD or sputtering to a thickness of about 100 to 300 layers. The etching stopper 10 is an end point detection film when forming sidewall spacers 11 which will be formed later.

Next, as shown in FIG. 8, the etching stopper lO1 insulating film 9 is etched using a resist l~mask.
, tungsten silicide film 8B.

The gate electrode 8 is formed by sequentially patterning the polycrystalline silicon film 8A. The resist mask used for etching is removed after etching. The electrode 8 to the gate 1 is made of a polycrystalline silicon film 8A and a tungsten silicide film 8B. Next, annealing is performed to activate the tungsten silicide film 8B. Next, although not shown, during ion implantation to form an n-type semiconductor region 7A that will later be part of the source and drain regions of the N-channel MISFET, P-channel MISFET? n in the ET area
In order to prevent type impurities from being introduced, the P-channel MI S FET region is covered with a resist mask. After this, an n-type impurity such as phosphorus (P) is added to the N-channel M I
The n-type semiconductor region 7A, which is a part of the source and drain regions, is introduced into the S FET region by ion implantation.
form. The mask for ion implantation in the N-channel MISFET region is the gate electrode 8, the insulating film 9 on its upper surface, and the etching pattern 11=pa 10. The resist mask covering the P-channel MISFET region is removed after the ion implantation. Since the tungsten silicide film 8B is only slightly damaged by the phosphorous ion implantation, the tungsten silicide film 8B and the conductive layer 17A made of an aluminum film to be formed later do not undergo any abnormal reaction due to the ion implantation.

Next, as shown in FIG.
1 (see FIGS. 2 to 4), for example, 8
C at a high temperature of about 00°C and a low pressure of about I T o r r
A silicon oxide film 1 is formed over the entire area on the semiconductor substrate l by VD.
form 1.

Next, as shown in FIG. 10, sidewall spacers 11 are formed by etching the silicon oxide film 11 from its upper surface by reactive ion etching (RIE). This etching is performed until the etching stopper lO on the gate electrode 8 is exposed. Furthermore, in order to prevent the silicon oxide film 11 other than the sidewall spacers 11 from remaining on the semiconductor substrate 1 in unnecessary areas, the etching is performed by over-etching. Therefore, if the etching stopper 10 and the insulating film 9 are not provided, the tungsten silicide film 8B will be damaged by etching ions. However, the tungsten silicide film 8 n
-1: Since the insulating film 9 is provided, the tungsten silicide film 8B is not damaged by the etching. Since the gate insulating film 6 exposed from the sidewall spacer 11 is removed when forming the sidewall spacer 11,
The surface of semiconductor substrate 1 is exposed. The exposed surface of the semiconductor substrate l also suffers damage from overetching. However, by providing the etching stopper 10 as an end point detection film, over-etching can be reduced and damage to the surface of the semiconductor substrate 1 can also be reduced.

Note that the etching stopper 10 as an etching end point detection film is not necessarily required when a silicon nitride film is used as the insulating film 9 as a damage prevention film. A damage prevention film, that is, an insulating film 9 made of a silicon nitride film, and a sidewall spacer 11 made of a silicon oxide film.
This is because there is a selectivity ratio between

Next, as shown in FIG. 11, the surface of the semiconductor substrate 1 exposed during the formation of the sidewall spacers 11 is oxidized again to form the gate insulating film 6 on the surface again. During this oxidation, although not shown, an oxide film is formed on the surface of the etching stopper 10 made of a polycrystalline silicon film or an amorphous silicon film.

Next, during ion implantation of an n-type impurity such as arsenic (AS) to form an n+ type semiconductor region 7B which is a part of the source and drain of the N-channel MISFET shown in FIG. In order to prevent it from entering the MISFET region, the P-channel MISFET region is covered with a resist mask (not shown).

This resist mask is removed after forming the square shaped semiconductor region 7B. Next, as shown in FIG. 12, an n-type impurity such as arsenic (As) is introduced into the N-channel MISFET region by ion implantation to form an n""-type semiconductor region 7B which is a part of the source and drain regions. do. The mask for ion implantation in the N-channel MISFET region is the gate electrode 8, the insulating film 9 thereon, and the etching stopper IO. The energy of the arsenic (A s ) implanted is the same as that of the phosphorus (P) implanted to form the i-type semiconductor region 7A, the source of the P-channel MISFET,
The energy is higher than the energy of boron (B) implanted to form the P+ type semiconductor region 18 (see FIG. 1) which is the drain region. Therefore, if only the etching stopper 10 is made of a polycrystalline silicon film or an amorphous silicon film, arsenic (As) ions penetrate through the etching stopper 10 and damage the tungsten silicide film 8B.

However, an insulating film 9 made of a silicon nitride film or a silicon oxide film is provided on the tungsten silicide film 8B to prevent damage caused by arsenic (A s ) ion implantation to the tungsten silicide film 8B. That is, the tungsten silicide film 8B is
A conductive layer 17 made of B and an aluminum film to be formed later.
Prevent A from causing abnormal reactions at their contact parts,
This is to prevent an increase in contact resistance or conduction failure of the conductive layer 14 made of a polycrystalline silicon film connected adjacent to the portion to which the conductive layer 17A is connected.

Next, although not shown, n-type impurities, such as boron (
In order to prevent B) from being introduced into the N-channel MISFET region, the N-channel MISFET region is covered with a resist mask.

This resist mask is removed after the P″″ type semiconductor region 18 is formed. Thereafter, an n-type impurity, such as boron (B), is introduced into the P-channel MISFET region by ion implantation to form the P-channel MISFET shown in FIGS. 1 and 4.
P' type semiconductor region 1 which is the source and drain region of ET
form 8.

-16= Since the damage caused by boron (B) ion implantation is small, the conductive layer 17 made of tungsten silicide film 8B and aluminum film is not affected by boron ion implantation.
A does not cause any abnormal reaction.

Note that ions in the n-type semiconductor region 7A and n'-type semiconductor region 7B, which are the source and drain regions of the N-channel MISFET, and the p4-type half region 18, which is the source and drain region of the P-channel MISFET. After implantation, annealing is performed to activate the impurities.

Next, as shown in FIG. 13, an insulating film 12 made of a silicon oxide film is formed over the entire area on the semiconductor substrate 1 by CVD at a high temperature of, for example, about 800° C. and a low pressure of about I Torr. Next, a connection hole 13 for connecting a conductive layer 14 made of a polycrystalline silicon film to be formed later to the upper surface of the gate electrode 8 is formed by etching using a resist mask. The resist mask is removed after the connection hole 13 is formed.

Next, in order to form the conductive layer 14 and the resistive element 14A shown in FIG.
A polycrystalline silicon film is formed over the entire area of 2. Next, for example, a resist mask is formed on the portion of this polycrystalline silicon film that will become the resistive element 14A, and then an n-type impurity, such as phosphorus (P), is introduced into the polycrystalline silicon film by, for example, ion implantation. The aim is to lower the resistance of the polycrystalline silicon film.

The ion implantation resist mask is removed after ion implantation. Next, the polycrystalline silicon film is patterned by etching using a resist mask to form a conductive layer 14 and a resistive element 14A. Resistance element 14A
The resistance value is about 10 to 100 gigaohms. The conductive layer 14 is connected to the tungsten silicide film 8B forming the gate electrode 8 through the connection hole 13.

Next, a silicon oxide film is formed over the entire area of the semiconductor substrate 1 by CVD at a high temperature of about 800° C. and a low pressure of about IToor, and further, by CVD, for example, phosphosilicate glass (PSG) is laminated to form an insulating film 15. do.

Next, as shown in FIG. 15, the n''' type semiconductor region 7B
Insulating film 15 on top, insulating film 15 on Glu-electrode 8 and P
The insulating film 15 on the p-type semiconductor region 18, which is the source and drain region of the channel MISFET, is selectively removed by dry etching using a resist mask to form a connection hole 16. The resist mask is removed after etching. In the connection hole 16 on the gate electrode 8, not only the insulating film 15 but also the etching stopper 10 is formed.
, the insulating film 9 is also removed. That is, a part of the gate electrode 8, that is, a part of the tungsten silicide film 8B is exposed from the connection hole 16 between the electrodes 1 to 8-.

Although not shown, the n4 type semiconductor region 7B, which is part of the source and drain regions of the N-channel MISFET,
Then, an n-type impurity such as phosphorus (P) is reintroduced through the connection hole 16 above it. In this ion implantation, the P-channel MISFET region is covered with a resist mask, and the resist mask is removed after the ion implantation.

In the plasma etching for forming the contact hole 16, overetching is performed to prevent the insulating film 15 from remaining within the contact hole 16. During this over-etching, the sputtering effect of the etching gas causes the glue electrode 8 to become thinner.
Two surfaces, ie, the upper surface of the tungsten silicide film 8B, are damaged.

However, the tungsten silicide film 8B must be prevented from being damaged by arsenic (As) ion implantation when forming the r1+ type semiconductor region 7B, which is part of the source and drain regions of the N-channel MTS FET. Therefore, the tungsten silicide film 8B and the conductive layer 17A made of an aluminum film, which will be formed later, will not cause an abnormal reaction only due to the damage received during the plasma etching. Furthermore, although the two surfaces of the tungsten silicide film 8B are contaminated by C and F in the etching gas, the upper surface of the tungsten silicide film 8B is not contaminated when the sidewall spacer 11 is formed, so the upper surface of the tungsten silicide film 8B is contaminated. is decreasing.

Next, in order to form the conductive layer 17A shown in FIG. 16 and the conductive layers 17B to 17F shown in FIG. Patterning is performed by etching using a mask to form conductive layers 17A to 17F. The resist mask is removed after patterning.

After this, the threshold value of MISFET is stabilized, the aluminum wirings 17A to 17F and the tungsten silicide film 8
In order to stabilize the ohmic contact with B or the semiconductor substrate 1, hydrogen annealing is performed at about 400 to 500°C.

If the upper surface of the tungsten silicide film 8B is severely damaged, an abnormal reaction occurs at the contact portion with the aluminum film 17A connected to the tungsten silicide film 8B. This occurs at temperatures as low as 450°C.

The inventor has discovered that when an abnormal reaction occurs between the tungsten silicide film 8B and the aluminum film 17A, contact 1 between the tungsten silicide film 8B and the aluminum film 17A occurs.
Although ohmic contact can be made at the bottom part itself, an experiment showed that ohmic contact 1- cannot be made with the conductive layer 14 made of a polycrystalline silicon film adjacent to the contact part and in contact with the same tungsten silicide film 8B. It has been confirmed by Moreover, the tungsten silicide film 8B and the aluminum film 17A
It has been confirmed by the present inventors that the abnormal reaction with the above-mentioned material has an effect over a long period of about 20 to 30 μm.

In this embodiment, damage caused by ion implantation and reactive ion etching to the two surfaces of the tungsten silicide film 8B are prevented, so that no abnormal reaction occurs between the tungsten silicide film 8B and the aluminum film 17A. Therefore, good ohmic contact characteristics between the tungsten silicide film 8B and the polycrystalline silicon film 14 can be obtained.

Thereafter, although not shown, a PSG film is formed as a final protective film over the entire surface of the semiconductor substrate 1 by, for example, plasma CVD, and a silicon nitride film is further laminated thereon, thereby completing the present embodiment.

According to this embodiment, the following effects can be obtained.

(1) By providing a damage prevention film made of a silicon oxide film or a silicon nitride film on the tungsten silicide film 8B, the upper surface of the tungsten silicide film 8B is prevented from being damaged by high-energy ion implantation such as arsenic (As). It disappears.

(2) Due to the damage prevention film, the upper surface of the tungsten silicide film 8B is not damaged or contaminated by reactive ion etching during the formation of the sidewall spacer 11.

(3) Due to (1) and (2) above, the contact resistance of the polycrystalline silicon film 14 in the vicinity of the contact area between the tungsten silicide [8B and the aluminum film 17A does not increase significantly, or conduction failure occurs. Never.

Note that the insulating film 9 as a damage prevention film and the etching stopper lO on the tungsten silicide film 8B of the gate electrode 8 are formed by ion implantation of arsenic (As) into the n+ type semiconductor region 7B, which is the source and drain region of the N-channel MI 5FET. It may be removed after being formed by.

Furthermore, when using a silicon oxide film as a damage prevention film, several percent of 02 is added to the annealing gas during annealing of the tungsten silicide film 8B, which is performed after patterning the gate electrode 8 and before forming the n-type semiconductor region 7A. A silicon oxide film having a thickness of approximately 100 to 200 λ may be formed by including the silicon oxide film.

Further, if the sidewall spacer 11 is not provided, it is not necessary to form the etching stopper 10 made of a polycrystalline silicon film or an amorphous silicon film.

The gate electrode 8 is not limited to the two-layer film of the polycrystalline silicon film 8A and the tungsten silicide film 8B;
It may be a two-layer film in which a high melting point metal film such as Mo, W, Ta, Ti, etc. is laminated on the polycrystalline silicon film 8A. Further, the gate electrode 8 may be formed only of the high melting point metal film or its silicide film.

Tungsten silicide film 8 shown in FIGS. 1 to 3
A conductive layer 14 made of a second layer of polycrystalline silicon film connected to B and a resistive element 1 formed integrally therewith.
4A is formed in the same process as the load resistor R of the SRAM memory cell shown in FIG. In addition, the first
FIG. 7 shows an equivalent circuit of an SRAM memory cell.

In FIG. 17, R is a load resistance made of a second layer of polycrystalline silicon film, Q is a driver MISFET, Qsw
is a selection MISFET, WL is a word line having the same structure as the gate electrode 8, and DL is a data line made of an aluminum film.

[Example ■]

18 to 25 are cross-sectional views in the manufacturing process of a DRAM memory cell.

In Example 2, on the upper surface of the gate electrode 28 made of a polycrystalline silicon film 28A and a tungsten silicide film 28B,
This is to prevent damage caused by reactive ion etching when forming the sidewall spacer 31 and to prevent the tungsten silicide film 28B from peeling off.

As shown in FIG. 18, a p-type single crystal silicon substrate 20 is coated with a field insulating film 21 made of a silicon oxide film, a P-type channel stopper region 22, and a dielectric film made of a silicon oxide film of a capacitive element, for example. A film 23, an n-type semiconductor region 24 serving as one electrode, a conductive plate 25 made of, for example, a polycrystalline silicon film, and a conductive plate 1-2.
An insulating film 26 made of a silicon oxide film obtained by oxidizing the exposed surface of the substrate 1, and a gate insulating film 27 made of a silicon oxide film obtained by oxidizing the surface of the substrate 1 are formed.

Next, as shown in FIG. 19, for example, low pressure CD (L
By PCVD) the electrode 28 (see Figure 20)
A polycrystalline silicon film 28A, which is a part of the substrate l''-, is formed over the entire area of the substrate l''-. An n-type impurity such as phosphorus (P) is introduced into this polycrystalline silicon film 28A by, for example, thermal diffusion or ion implantation to lower the resistance. Next, a tungsten silicide film 28B is formed on the entire upper surface of the polycrystalline silicon film 28A by, for example, CVD or sputtering.

Note that the tungsten silicide film 28B is made of Mo, W,
It may also be a film of a high melting point metal such as Ta or Ti.

Alternatively, a silicide film of the high melting point metal may be used.

Next, the entire surface of the tungsten silicide film 28B is coated by, for example, low pressure CVD (LPCVD).

The silicon nitride film 29, which will serve as a damage prevention film when forming the sidewall spacers 31 later, has a thickness of 200 to 300λ.
Form the film to a thickness of about The silicon nitride film 29 also serves as an etching stopper when forming the sidewall spacers 31.

Next, as shown in FIG. 20, the silicon nitride film 29 is etched using a resist mask (not shown).
, the tungsten silicide film 28B, and the polycrystalline silicon film 28A are sequentially etched and patterned into the pattern of the gate electrode 28. Note that the gate electrode 28 is made of a polycrystalline silicon film 28A and a tungsten silicide film 2.
It consists of 8B. A silicon nitride film 29 serving as a damage prevention film and an etching stopper is deposited on the upper surface of the tungsten silicide film 28B in the same pattern as the gate electrode 28. The resist mask used for etching is removed after etching.

Next, as shown in FIG. 21, using the silicon nitride film 29 and the gate electrode 28 as masks for ion implantation, an n-type impurity such as phosphorus (P) is introduced into the substrate 20, and the source and drain of the N-channel MISFET are An i-type semiconductor region 30, which is a part of the region, is formed.

Next, as shown in FIG. 22, similarly to Example I, a silicon oxide film is formed on the substrate 20 by, for example, CVD, and this silicon oxide film is etched by reactive ion etching (RI).
The sidewall spacers 31 are formed by etching from the top surface according to step E). Side wall spacer 31
After the formation, the tungsten silicide film 28B is annealed to achieve crystallization.

The RIE includes sidewall spacers 31 on the substrate 20.
Overetching is performed to prevent the silicon oxide film for forming the sidewall spacer 31 from remaining unnecessarily in areas other than the sidewall spacer 31. In this overetching,
Since the silicon nitride film 29 is provided on the upper surface of the tungsten silicide film 28B, the tungsten silicide film 28B
No damage is done to the top surface of 8B. In addition, it may be contaminated by C and F in the etching gas).

When forming the side wall space 31, the exposed gate insulating film 27 on the surface of the substrate 20 is removed. Therefore, by re-oxidizing the surface of the substrate 20, the gate insulating film 27 is formed again on the exposed surface of the substrate 20. Alternatively, a silicon oxide film is formed over the entire surface of the substrate 2 ( ) to form the gate insulating film 27 by CVD at a high temperature of about 800° C. and a low pressure of about ITorr. During this reoxidation or oxide film deposition, the tungsten silicide film 2
If the tungsten silicide film 28B is severely damaged or contaminated with C or F, the tungsten silicide film 28B will be abnormally oxidized.

When this abnormal oxidation occurs, the tungsten silicide film 28
B peels off from the polycrystalline silicon film 28A. However, in this embodiment, the silicon nitride film 29 is provided to prevent the tungsten silicide film 28B from being seriously damaged or contaminated, so the tungsten silicide film 28B is not abnormally oxidized. That is, the reliability of the electrical characteristics of the gate electrode 28 is improved by preventing the tungsten silicide film 28B from peeling off from the polycrystalline silicon film 28A.

Next, as shown in FIG. 23, using the sidewall spacers 31 and gate electrodes 28 as masks, n-type impurities such as arsenic (As) are introduced into the substrate 20 by ion implantation to form part of the source and drain regions. A certain n''' type semiconductor region 32 is formed.

Since the silicon nitride film 29 is formed on the gate electrode 28, the tungsten silicide film 28B is not damaged by the ion implantation.

Next, as shown in FIG. 24, an insulating film 33 is formed by laminating a silicon oxide film and a PSG film from below on the substrate 20 by, for example, plasma CVD.

Next, as shown in FIG. 25, a connection hole 34 is formed by selectively removing the insulating film 33 on the n3 type semiconductor region 32, which becomes a part of the drain region when reading the memory cell. After the connection hole 34 is formed, an n is inserted into the substrate 20 through the connection hole 34.
A type impurity such as phosphorus (P) is introduced. Next, an aluminum film is formed on the entire surface of the substrate 20 by sputtering, for example, and this aluminum film is patterned by etching using a resist mask to form data lines DL. The resist mask is removed after etching. Thereafter, a final protective film (not shown) is formed by laminating a PSG film and a silicon nitride film from below by, for example, plasma CVD, and this embodiment ends.

31-1 According to this embodiment, the following effects can be obtained.

(1) Since a silicon nitride film is provided as a damage prevention film and a contamination prevention film on the tungsten silicide film 28B, which is a part of the gate electrode 28, the upper surface of the tungsten silicide film 28B is damaged when the sidewall spacer 31 is formed. It will never get contaminated again.

(2) According to (1) above, the tungsten silicide film 2
Because 8B will not be abnormally oxidized.

The tungsten silicide film 28B is the polycrystalline silicon film 2
No more peeling than 8A. Therefore, the gate electrode 28
The reliability of the electrical characteristics of the device is improved.

Although the present invention has been specifically explained above using examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof.

〔Effect of the invention〕

A brief explanation of the effects of typical inventions disclosed in this application is as follows.

That is, by providing a film different from the high melting point metal film or the silicide film on the high melting point metal film or the silicide film of the high melting point metal, the high melting point metal film or the silicide film is damaged or contaminated. Therefore, the electrical reliability of a conductive layer having a high melting point metal film or a silicide film of the high melting point metal is improved.

[Brief explanation of drawings]

Fig. 1 is a plan view of an N-channel MI S FET and a P-channel M I S FET, Fig. 2 is a cross-sectional view taken along the line A-A in Fig. 1, and Fig. 3 is a cross-sectional view taken along the line A-A in Fig. 1. A cross-sectional view along the line, Figure 4 is the 1st
5 to 16 are cross-sectional views in the manufacturing process of MISFET, and FIG. 17 is an equivalent circuit of an SRAM memory cell. FIGS. 18 to 25 are cross-sectional views of memory cells in the DRAM manufacturing process. 1.20...Semiconductor substrate, 2...P-type well region, 3
... N-type well region, 4.21 ... Field insulating film, 5.22 ... Channels 1-flange region, 6.27
...Goo 1~Insulating film, 7A, 7B, 18.24.30.
32... Semiconductor region, 8... Gate electrode (polycrystalline silicon film 8A, high melting point metal silicide film aB), 28...
...Gate electrode (polycrystalline silicon film 28A, high melting point metal silicide film 28B), 9.29...Damage prevention film made of silicon nitride film or silicon oxide film, 10.
...Etching stopper (polycrystalline silicon or amorphous silicon), 11.31...Side wall spacer, 12.15.26.33...Insulating film, 14...
・Conductive layer (polycrystalline silicon), 14A...resistance element (
polycrystalline silicon), 13.16.34... connection hole, 1
7A to 17F and 35... conductive layer made of aluminum film, 25... conductive plate, 23... dielectric film, WL... word line, DL... data line, R... load resistance, Qsw...selection MISFET, Qo-driver MISFET.・'Ding\\, Patent Attorney Katsuyu Ogawa, 1 Figure 17 Figure 18 (25'A, 2013) Figure 25 20 $ (2/yA, 20''13) Complete set of procedural amendments) of the case Indication 1988 Patent Application No. 60505 Name of the invention Relationship to the Semiconductor Integrated Circuit Device Amendment Case Patent Applicant

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device characterized in that a protective film during ion implantation or etching is provided on the upper surface of a conductive layer having a high melting point metal layer film or a silicide film of the high melting point metal. . 2. The protective film is made of a silicon oxide film or a silicon nitride film, or a polycrystalline silicon film or an amorphous silicon film is provided on the silicon oxide film or the silicon nitride film.
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is made of a layered film. 3. The semiconductor integrated circuit device according to claim 1, wherein a conductive layer made of a polycrystalline silicon film and a conductive layer made of an aluminum layer are connected to the upper surface of the conductive layer.