JPS62219518A - Formation of electrode of compound semiconductor element - Google Patents
Formation of electrode of compound semiconductor elementInfo
- Publication number
- JPS62219518A JPS62219518A JP6330586A JP6330586A JPS62219518A JP S62219518 A JPS62219518 A JP S62219518A JP 6330586 A JP6330586 A JP 6330586A JP 6330586 A JP6330586 A JP 6330586A JP S62219518 A JPS62219518 A JP S62219518A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal film
- compound semiconductor
- semiconductor
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 150000001875 compounds Chemical class 0.000 title claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000002184 metal Substances 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000009684 ion beam mixing Methods 0.000 claims abstract description 7
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 6
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 6
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 5
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 3
- 239000002344 surface layer Substances 0.000 claims description 6
- 239000000956 alloy Substances 0.000 abstract description 8
- 229910045601 alloy Inorganic materials 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 abstract description 2
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 238000011282 treatment Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 27
- 239000010410 layer Substances 0.000 description 9
- 230000006866 deterioration Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- -1 silica compound Chemical class 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は化合物半導体素子の電極形成方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for forming electrodes of compound semiconductor devices.
化合物半導体は光通信用素子等に広く用いられて来てい
るが、これらの素子は場合によっては厳しい条件下で、
かつまた保守が困難という状況下で使用される。従って
、これらの素子には優れた特性と同時に、その使用環境
によっては高い信頼性が要求される。信頼性に最も影響
する因子の1つに電極と半導体との反応によって進行す
る電極劣化が挙げられる。従来、半導体素子の電極とし
て少量のドーピング不純物(Zn、Ge等)を含む九を
直接半導体に接触させる構造のオーム性電極が広く用い
られて来た。しかし、この電極構造において拡Auが2
00℃程度から半導体と反応するため、時に紘素子特性
を著しく劣化させていた。これを改善するために、Ti
、Pd、Pt、W等の高融点金属を挾んだTi/Pt(
又1d Pd 、W ) /Au多層構造の電極が注目
されて来た。Ti/Pt/Au電極は、第3図に示すよ
うに化合物半導体10表面にコンタクト層としてTi4
f:付け、ポンディングパッドとしてAu8を使用し
、それら2層の間にAuのバリアメタルとして高融点金
属であるPt5を挾んだ3層構造から成ってお夛、多層
構造電極の中でも代表的なもので強い関心を集めている
。なお、2は絶縁膜である。Compound semiconductors have been widely used in optical communication devices, etc., but in some cases these devices can be used under harsh conditions.
It is also used in situations where maintenance is difficult. Therefore, these devices are required to have not only excellent characteristics but also high reliability depending on the environment in which they are used. One of the factors that most affects reliability is electrode deterioration that progresses due to the reaction between the electrode and the semiconductor. Conventionally, ohmic electrodes having a structure in which a metal containing a small amount of doping impurities (Zn, Ge, etc.) is brought into direct contact with a semiconductor have been widely used as electrodes of semiconductor devices. However, in this electrode structure, the expanded Au
Because it reacts with semiconductors at temperatures as low as 00°C, it has sometimes caused significant deterioration of the characteristics of electronic devices. To improve this, Ti
, Ti/Pt (
Also, electrodes with a 1d Pd , W ) /Au multilayer structure have attracted attention. The Ti/Pt/Au electrode is made of Ti4 as a contact layer on the surface of the compound semiconductor 10 as shown in FIG.
f: It has a three-layer structure in which Au8 is used as a bonding pad and Pt5, a high melting point metal, is sandwiched between the two layers as a barrier metal for the Au.It is a typical multilayer structure electrode. It is attracting strong interest. Note that 2 is an insulating film.
しかし、Ti/Pt/Au系電極は、熱的には安定で信
頼性の高い電極を提供するものの、下地となる半導体と
ほとんど合金層を形成せず、電極はがれが生じ易く%ま
た接触抵抗が高いという問題点があった。電極はがれは
素子歩留シの著しい低下を招いた。また接触抵抗が高い
ことは、高速動作をさせる場合の妨げとなるばかシでな
く、サージに対する劣化等を招くものであり 、Ti
/ Pt /Au系電極のこれらの問題点の解決が太き
力課題となっていた。However, although Ti/Pt/Au-based electrodes provide thermally stable and highly reliable electrodes, they hardly form an alloy layer with the underlying semiconductor, and the electrodes tend to peel off easily and have low contact resistance. The problem was that it was expensive. Electrode peeling caused a significant drop in device yield. In addition, high contact resistance is not just a hindrance to high-speed operation, but also causes deterioration due to surges, and Ti
Solving these problems with /Pt/Au based electrodes has been a major challenge.
本発明の目的は、上記従来の欠点を除き、信頼性が高く
、かつ半導体との密着性に優れ、接触抵抗も低くなる化
合物半導体素子の電極の形成方法を提供することにある
。An object of the present invention is to provide a method for forming an electrode for a compound semiconductor device, which eliminates the above-mentioned conventional drawbacks, has high reliability, has excellent adhesion to a semiconductor, and has low contact resistance.
前述の問題点を解決するために本発明が提供する化合物
半導体の電極形成方法は、絶縁膜によって選択的に化合
物半導体を露出させた領域にTi/Ptから成る第1の
多層金属膜を形成する工程と、この金属薄膜にドーピン
グ原子をイオン注入して金属膜と化合物半導体表層部と
の間でイオンビームミキシングを起こさせる工程と、熱
処理を施す工程と、上記第1の多層金属膜とその周辺部
の絶縁膜を含む領域にTi、Pt、Pd、Wの少なくと
も1種類を含む金属膜とその表面に設けられたAu膜か
ら成る第2の多層金属膜を形成する工程とを有すること
を特徴とする。In order to solve the above-mentioned problems, the present invention provides a method for forming an electrode of a compound semiconductor, in which a first multilayer metal film made of Ti/Pt is formed in a region where the compound semiconductor is selectively exposed by an insulating film. a step of ion-implanting doping atoms into the metal thin film to cause ion beam mixing between the metal film and the compound semiconductor surface layer, a heat treatment step, and the first multilayer metal film and its surroundings. forming a second multilayer metal film consisting of a metal film containing at least one of Ti, Pt, Pd, and W and an Au film provided on the surface of the metal film in the region including the insulating film of the second part; shall be.
本発明は上述の構成によシ従来技術の問題点を解決した
。即ち、第1の多層金属膜を形成稜、ドーピング原子を
イオン注入することによシ、金属と半導体界面でイオン
ビームミキシングを行ない次に続く熱処理工程と併せて
等測的に金属と半導体の合金化進行を助長することが可
能となる。加えて、半導体表面付近にイオン注入された
ドーピング原子も入り込むために、表面不純物濃度が高
まり、やは多接触抵抗の低減が可能となる。また、第1
の多層金属MKはAuは含まれていないので、熱処理時
にAuが半導体と反応を起こして(アロイスパイクを生
じさせたりして)素子特性の劣化を招くことがない。ポ
ンディングパッドとなる第2の多層金属膜は、選択的に
露出された第1の多層金属膜表面及びその周辺の絶縁膜
表面に吟って形成されておシ、金属と絶縁膜との密着性
が高いことから、全体として電極の密着強度に優れ、か
つ接触抵抗の小さい高信頼電極が得られる。The present invention solves the problems of the prior art with the above-described configuration. That is, when the first multilayer metal film is formed, doping atoms are ion-implanted, ion beam mixing is performed at the metal-semiconductor interface, and in conjunction with the subsequent heat treatment step, the metal-semiconductor alloy is isometrically formed. This makes it possible to promote the progress of chemical transformation. In addition, doping atoms ion-implanted near the semiconductor surface also enter, increasing the surface impurity concentration and making it possible to reduce multi-contact resistance. Also, the first
Since the multilayer metal MK does not contain Au, the Au does not react with the semiconductor during heat treatment (such as forming alloy spikes), thereby preventing deterioration of device characteristics. The second multilayer metal film, which serves as a bonding pad, is formed on the selectively exposed surface of the first multilayer metal film and the surface of the insulating film in the vicinity thereof, thereby ensuring close contact between the metal and the insulating film. Because of its high properties, it is possible to obtain a highly reliable electrode with excellent overall electrode adhesion strength and low contact resistance.
以下本発明の一実施例について図面を参照して詳細に説
明する。本実施例では■−■族化合物半導体のP側電極
形成例について述べる。まず、第1図(aJに示す様に
化合物半導体lの表面に絶縁膜2を形成し、その後フォ
トレジスト3t[JiL、露光、現像によシ特定領域の
7オトレジストを除失する。次に図(bJのように特定
領域の絶縁膜2をエツチングによシ除去し、化合物半導
体1の表面を露出させる。しかる後、図(C1に示すよ
うにTi4/Pt5膜を蒸着する。続いて図(dlに示
す様に、P型ドーパントであるBeのイオン注入を行な
ってイオンビームミキシングを施す。次に7オトレジス
トを剥離し、リフトオフ技術によシ特定領域のみに選択
的にTi4/Pi5を残し、この状態で熱処理を施して
電極金属と半導体との合金を形成してオーミック電極を
得る(図(e))。しかる後、図(f)に示す様に7オ
トレジスト6を塗布し、露光、現像によp Pts面及
びその周辺の絶縁膜2の表面が露出する様に特定領域の
7オトレジストを除去する0続いて、図(f)に示すよ
うにTi7/Au8を蒸着し、最後に、フォトレジスト
を剥離してリフトオフ技術によシボンディングパッ)”
Ti7 / Au8 カ%定領域に選択的に形成される
(図(h)=) 。An embodiment of the present invention will be described in detail below with reference to the drawings. In this embodiment, an example of forming a P-side electrode of a ■-■ group compound semiconductor will be described. First, an insulating film 2 is formed on the surface of a compound semiconductor 1 as shown in FIG. (As shown in bJ, a specific region of the insulating film 2 is removed by etching to expose the surface of the compound semiconductor 1. After that, a Ti4/Pt5 film is deposited as shown in Fig. (C1). As shown in dl, Be, which is a P-type dopant, is ion-implanted and ion beam mixing is performed.Next, the photoresist 7 is peeled off, and Ti4/Pi5 is left selectively only in specific areas using a lift-off technique. In this state, heat treatment is performed to form an alloy of the electrode metal and the semiconductor to obtain an ohmic electrode (Fig. Then, remove the photoresist in a specific area so that the Pts surface and the surface of the insulating film 2 around it are exposed.Next, as shown in Figure (f), Ti7/Au8 is deposited, and finally, photoresist is removed. (Remove the resist and apply lift-off technology to bonding pad)
Ti7/Au8 is selectively formed in the constant region (Figure (h) =).
次に第4図(d)の工程について、第2図を使って詳し
く説明する。半導体上に蒸着したT i /P tは第
2図(alの様に急峻な界面を持っている。一般にTi
/Pt系電極は熱処理によっても、下地となる半導体層
と#1とんど合金層を形成せず、このために電極はがれ
が生じ易く、また接触抵抗も高いという問題点があった
。本発明によれば、第2図(b)に示す様に、蒸着した
T i / P を膜にP型ドーパントであるBeをイ
オン注入してイオンビームミキシングを施すことにより
s Tsと半導体との界面急峻性を乱し、Ti原子を
半導体表層部に混入させることができる。続いて熱処理
を施すことによシ1等価的に合金進行が助長された効果
を得る。Next, the process shown in FIG. 4(d) will be explained in detail using FIG. 2. Ti/Pt deposited on a semiconductor has a steep interface as shown in Figure 2 (al).
/Pt-based electrodes do not form a #1 alloy layer with the underlying semiconductor layer even when subjected to heat treatment, and as a result, the electrodes tend to peel off easily and have high contact resistance. According to the present invention, as shown in FIG. 2(b), by ion-implanting Be, which is a P-type dopant, into the deposited Ti/P film and performing ion beam mixing, the interaction between sTs and the semiconductor is achieved. It is possible to disturb the steepness of the interface and mix Ti atoms into the semiconductor surface layer. Subsequently, heat treatment is performed to obtain the effect of promoting alloy progress equivalently.
またAuに対するバリアメタルとしてのストッパー効果
は、TiとPtの化合物が寄与することが知られている
が、この点に関しても本発明によれば Ill iとP
tのミキシングによシ化合物が形成され易くなるため、
高温下での素子の信頼性にも優れる。またTi/Pt’
iつき抜けて半導体表層部に達したBeは半導体表層部
のP型不純物濃度を高め、接触抵抗低減に寄与する。こ
こではTi/Pt/半導体で十分なミキシング効果が得
られ、Be+イオン自体も半導体表層部まで達する様に
、加速電圧t”150kV、注入量をlXl0 cm
、Ti及びPtの層厚を各々800A、1200Aと
した。Furthermore, it is known that a compound of Ti and Pt contributes to the stopper effect as a barrier metal for Au, and in this regard, according to the present invention, Ill i and P
Because the mixing of t makes it easier to form a silica compound,
The device also has excellent reliability under high temperatures. Also Ti/Pt'
The Be that has passed through i and reached the semiconductor surface layer increases the P-type impurity concentration in the semiconductor surface layer, contributing to a reduction in contact resistance. Here, a sufficient mixing effect can be obtained with Ti/Pt/semiconductor, and the acceleration voltage t" is 150 kV and the implantation amount is 1Xl0 cm so that the Be+ ions themselves reach the semiconductor surface layer.
, Ti and Pt layer thicknesses were set to 800A and 1200A, respectively.
さらに本発明によれば、第1のTi/Pt金属膜にはA
uは含まれていないので、熱処理時にAuが半導体と反
応を起こし、アロイスパイクを生じさせる等して素子特
性の劣化を招くこともない。Furthermore, according to the present invention, the first Ti/Pt metal film has A
Since it does not contain u, Au will not react with the semiconductor during heat treatment and will not cause alloy spikes or other deterioration in device characteristics.
また第2のT i /Au金属金属膜第1層目のTi/
Pt金属膜とその周辺の絶縁膜表面に縛って形成されて
おシ、金属と絶縁膜との密着性が高いことから電極線が
れが無くなる。更に出来上り構造として、半導体表面が
雰囲気中に露出する部分が無いので表面劣化の懸念も無
い。In addition, the second Ti/Au metal film is the Ti/Au metal film of the first layer.
The electrode wire is formed so as to be bound to the surface of the Pt metal film and the surrounding insulating film, and the electrode wire does not come loose due to the high adhesion between the metal and the insulating film. Furthermore, since there is no part of the semiconductor surface exposed to the atmosphere in the finished structure, there is no concern about surface deterioration.
なお、上記実施例ではAuのすぐ内側の金属膜としてT
iを用いた場合を示したが、Tiに限らすPd、Pt、
Wおよびこれらの組合せでも同様の効果が得られる。In addition, in the above example, T was used as the metal film immediately inside the Au.
Although the case is shown in which Ti is used, Pd, Pt,
Similar effects can be obtained with W and combinations thereof.
以上説明した様に、本発明によれば信頼性が高く、かつ
密着性にも優れ、接触抵抗も低い、良好な化合物半導体
素子の電極が得られる。As explained above, according to the present invention, it is possible to obtain an electrode for a compound semiconductor device that is highly reliable, has excellent adhesion, and has low contact resistance.
第1図(a)〜(h)は本発明の一実施例の製造工程を
示す断面模式図、第2図(a) 、 (b)は第1図(
d)の工程を説明するために金属原子と半導体との、界
面の状態を概念的に示した模式図、第を図は従来のTi
/P t/Au 3層構造の電極を有する化合物半導体
素子の断面模式図である。Figures 1 (a) to (h) are schematic cross-sectional views showing the manufacturing process of an embodiment of the present invention, and Figures 2 (a) and (b) are Figure 1 (
A schematic diagram conceptually showing the state of the interface between a metal atom and a semiconductor to explain the step d).
FIG. 2 is a schematic cross-sectional view of a compound semiconductor device having an electrode with a /P t/Au three-layer structure.
Claims (1)
にTi/Pt膜から成る第1の多層金属膜を形成する工
程と、該金属膜にドーピング原子をイオン注入して金属
膜と化合物半導体表層部との間でイオンビームミキシン
グを起こさせる工程と、熱処理を施す工程と、前記第1
の多層金属膜とその周辺部の絶縁膜を含む領域にTi、
Pt、Pd、Wの少なくとも1種類の金属膜とその表面
に設けられたAu膜から成る第2の多層金属膜を形成す
る工程とを有することを特徴とする化合物半導体素子の
電極形成方法。A step of forming a first multilayer metal film made of a Ti/Pt film in a region where the compound semiconductor is selectively exposed by the insulating film, and ion-implanting doping atoms into the metal film to form a surface layer of the metal film and the compound semiconductor. a step of causing ion beam mixing between the
Ti, Ti,
A method for forming electrodes of a compound semiconductor device, comprising the step of forming a second multilayer metal film consisting of at least one metal film of Pt, Pd, and W and an Au film provided on the surface of the second multilayer metal film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6330586A JPS62219518A (en) | 1986-03-19 | 1986-03-19 | Formation of electrode of compound semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6330586A JPS62219518A (en) | 1986-03-19 | 1986-03-19 | Formation of electrode of compound semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62219518A true JPS62219518A (en) | 1987-09-26 |
Family
ID=13225448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6330586A Pending JPS62219518A (en) | 1986-03-19 | 1986-03-19 | Formation of electrode of compound semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62219518A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5523623A (en) * | 1994-03-09 | 1996-06-04 | Matsushita Electric Industrial Co., Ltd. | Ohmic electrode for a p-type compound semiconductor and a bipolar transistor incorporating the ohmic electrode |
-
1986
- 1986-03-19 JP JP6330586A patent/JPS62219518A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5523623A (en) * | 1994-03-09 | 1996-06-04 | Matsushita Electric Industrial Co., Ltd. | Ohmic electrode for a p-type compound semiconductor and a bipolar transistor incorporating the ohmic electrode |
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