JPS62216348A - Package for semiconductor element and manufacture thereof - Google Patents
Package for semiconductor element and manufacture thereofInfo
- Publication number
- JPS62216348A JPS62216348A JP6021886A JP6021886A JPS62216348A JP S62216348 A JPS62216348 A JP S62216348A JP 6021886 A JP6021886 A JP 6021886A JP 6021886 A JP6021886 A JP 6021886A JP S62216348 A JPS62216348 A JP S62216348A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metallized layer
- metal
- electrode
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000000919 ceramic Substances 0.000 claims abstract description 24
- 229910000679 solder Inorganic materials 0.000 claims abstract description 15
- 238000001259 photo etching Methods 0.000 claims abstract description 7
- 238000005476 soldering Methods 0.000 claims abstract description 7
- 238000010304 firing Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 8
- 238000007747 plating Methods 0.000 abstract description 8
- 238000005219 brazing Methods 0.000 abstract description 4
- 238000007772 electroless plating Methods 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000003973 paint Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000006089 photosensitive glass Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は高密度集積回路のような極めて多数の電極を有
する半導体素子を支持するためのセラミック製の半導体
素子用パッケージとその製造法に関するものである。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a ceramic semiconductor device package for supporting a semiconductor device having an extremely large number of electrodes such as a high-density integrated circuit, and a manufacturing method thereof. It is.
（従来の技術）
半導体素子用パッケージの表面には半導体装置の多数の
電極と接続されるためのフィンガパターンと呼ばれる極
めて細い多数の線状の電極や、半導体素子用パッケージ
を回路基板と接続するための多数の電極などが形成され
でおり、従来はこれらの電極はセラミックグリーンシー
ト上にＭｏＸＷ等の高融点の金属を含む導電ペーストを
印刷し焼成する方法によって形成されていた。ところが
最近の半導体素子の集積度の著しい向上に伴ない端子数
の多いものでは端子数が１００個以上の多数のものあり
、しかもその全体の大きさは小型化する一方である。こ
の結果電極に要求される寸法精度は極度に高まり、セラ
ミックグリーンシートを焼成する際に不可避的に生ずる
不均等な焼成収縮で要求される電極の寸法精度を満足で
きず、従来法によってはこのような集積度の高い半導体
素子のためのパッケージを製造することが困難となりつ
つあった。(Prior art) On the surface of a semiconductor element package, there are many extremely thin linear electrodes called finger patterns for connecting to many electrodes of a semiconductor device, and for connecting the semiconductor element package to a circuit board. Conventionally, these electrodes have been formed by printing a conductive paste containing a high melting point metal such as MoXW on a ceramic green sheet and firing it. However, with the recent remarkable improvement in the degree of integration of semiconductor devices, there are many devices with a large number of terminals, such as 100 or more, and the overall size of these devices is becoming smaller and smaller. As a result, the dimensional accuracy required for the electrodes has increased to an extremely high level, and due to the uneven firing shrinkage that inevitably occurs when ceramic green sheets are fired, the dimensional accuracy required for the electrodes cannot be satisfied. It was becoming difficult to manufacture packages for highly integrated semiconductor devices.
（発明が解決しようとする問題点）
本発明はこのような従来の問題点を解決して、１００個
を越えるような多数の電極を備えた集積度の高い半導体
素子を支持するために要求される寸法精度を十分に満た
すことができる新規な半導体素子用パッケージとその製
造法を目的として完成されたものである。(Problems to be Solved by the Invention) The present invention solves these conventional problems and solves the problems required to support highly integrated semiconductor devices having a large number of electrodes exceeding 100. It was completed with the aim of creating a new semiconductor device package and its manufacturing method that can fully satisfy the dimensional accuracy required.
（問題点を解決するための手段）
本発明はセラミックシート上に焼成された電極用メタラ
イズ層上に、ホトエツチングにより形成された開口部を
有する感光性電気絶縁層が被覆され、この開口部内の電
極用メタライズ層上にははんだとの親和性に優れた金属
層が形成されていることを特徴とする半導体素子用パッ
ケージに関する第１の発明と、所要部分に電極用メタラ
イズ層が形成されたセラミックグリーンシートを焼成し
た後その電極用メタライズ層を含む部分の表面全体に感
光性電気絶縁層を形成し、これをホトエツチングして正
確な位置に開口部を形成したうえ、外部金属リードをろ
う付けし、その後はんだとの親和性に優れた金属による
めっきを施して開口部内の電極用メタライズ層上にはん
だ付け用の金属層を形成することを特徴とする半導体素
子用パッケージの製造法に関する第２の発明と、所要部
分に電極用メタライズ層が形成されたセラミックグリー
ンシートを焼成したうえ端子ピンのような外部金属リー
ドをろう付けし、該電極用メタライズ層を含む部分の表
面全体に感光性電気絶縁層を塗布し、その後この感光性
電気絶縁層をホトエツチングして正確な位置に電極用メ
タライズ層に連通ずる開口部を形成し、その後はんだと
の親和性に優れた金属によるめっきを施して開口部内の
メタライズ層上にはんだ付け用の金属層を形成すること
を特徴とする半導体素子用パッケージの製造法に関する
第３の発明とからなるものである。(Means for Solving the Problems) The present invention is characterized in that a metallized layer for electrodes fired on a ceramic sheet is coated with a photosensitive electrical insulating layer having openings formed by photoetching, and the electrodes inside the openings are coated with a photosensitive electrical insulating layer having openings formed by photoetching. A first invention relating to a package for a semiconductor element, characterized in that a metal layer having excellent affinity with solder is formed on a metallized layer for use in solder, and a ceramic green in which a metallized layer for electrodes is formed in required parts. After firing the sheet, a photosensitive electrical insulating layer is formed on the entire surface of the part including the electrode metallized layer, and this is photo-etched to form openings at precise positions, and external metal leads are brazed. A second invention relating to a method for manufacturing a package for a semiconductor device, characterized in that a metal layer for soldering is formed on the electrode metallized layer in the opening by plating with a metal having excellent affinity with solder. Then, a ceramic green sheet with a metallized layer for electrodes formed on the required parts is fired, external metal leads such as terminal pins are brazed, and a photosensitive electrical insulating layer is applied to the entire surface of the part including the metallized layer for electrodes. This photosensitive electrical insulating layer is then photoetched to form an opening that communicates with the electrode metallized layer at a precise location, and then plated with a metal that has excellent affinity with solder to fill the opening. The third invention relates to a method for manufacturing a package for a semiconductor device, characterized in that a metal layer for soldering is formed on the metallized layer.
（実施例）
次に本発明を図示のワイヤボンディング用タブタイプの
実施例について詳細に説明する。(Example) Next, the present invention will be described in detail with regard to an example of a wire bonding tab type shown in the drawings.
第１図〜第４図は本願第２の発明の実施例の製造工程を
示すもので、先ず第１図に示されるように従来技法によ
り未焼成のセラミックグリーンシート＋１１の表面に半
導体素子をマウントするためのメタライズ層（２）と、
半導体素子の多数の電極端子とワイヤボンディングによ
り接続されるフィンガパターン状の電極用メタライズ層
（３）とが形成され、またセラミックグリーンシート（
１）には各電極用メタライズ層（３）と端子用のピン（
９）とを接続するための導電体（４）が充填されたスル
ーホール（５）が透設される。このようなセラミックグ
リーンシート（１）は次に常法により焼成されてセラミ
ックシート（１）となるが、この際に焼成収縮を生じて
特に電極用メタライズ層（３）の寸法精度に狂いを生ず
ることは従来と同様である。そこで本発明においては、
セラミックシート（１）のこのような電極用メタライズ
層（３）を含む部分の表面全体に第２図のように感光性
電気絶縁層（６）を塗布する。この感光性電気絶縁層（
６）は後工程のろう付け（８００℃程度）、はんだ付け
（２００℃程度）、半導体素子のグイマウント（４５０
℃程度）等に耐えられる耐熱性を有するものとする必要
があり、無機塗料を用いることが好ましい。次に感光性
電気絶縁層（６）はホトエツチングされ、本来電極用メ
タライズ層があるべき正確な位置に高精度で開口部（７
）が形成される。1 to 4 show the manufacturing process of an embodiment of the second invention of the present application. First, as shown in FIG. 1, a semiconductor element is mounted on the surface of an unfired ceramic green sheet +11 using a conventional technique. a metallized layer (2) for
A finger pattern electrode metallized layer (3) is formed which is connected to a large number of electrode terminals of a semiconductor element by wire bonding, and a ceramic green sheet (3) is formed.
1) includes a metallized layer for each electrode (3) and a terminal pin (
A through-hole (5) filled with a conductor (4) for connection to (9) is provided. Such a ceramic green sheet (1) is then fired by a conventional method to become a ceramic sheet (1), but at this time, firing shrinkage occurs and the dimensional accuracy of the metallized layer for electrodes (3) is particularly disturbed. This is the same as before. Therefore, in the present invention,
A photosensitive electrical insulating layer (6) is applied to the entire surface of the ceramic sheet (1) including the electrode metallized layer (3) as shown in FIG. This photosensitive electrical insulation layer (
6) Post-process brazing (approximately 800℃), soldering (approximately 200℃), and semiconductor element mount (approximately 450℃)
It is necessary to have heat resistance that can withstand temperatures such as 0.7°C or so, and it is preferable to use an inorganic paint. Next, the photosensitive electrical insulating layer (6) is photoetched, and openings (7) are formed with high precision at the exact positions where the electrode metallized layer should originally be.
) is formed.
このホトエツチングはセラミックシートの焼成収縮とは
無関係に光学的手段によって極めて正確に行われる。そ
の後必要に応じて無電解めっき及びろう付け用のめっき
を施して第３図のようにこの開口部（７）内の電極用メ
タライズ層（３）、半導体素子をマウントするためのメ
タライズ層（２）、スルーホール（５）の下地めっき層
（８）を形成し、次に端子用のビン（９）等の外部金属
リードをろう付けしたうえ旧、Ｃｕ、 Ａｕ、 Ａｇの
ようなはんだとの親和性に優れた金属によるめっきを施
せば第４図に示されるとおり開口部（７）内の電極用メ
タライズ層（３）及びメタライズ層（２）にははんだ付
けに適した金属層α０）が形成されることとなる。This photoetching is carried out very accurately by optical means, independent of firing shrinkage of the ceramic sheet. After that, electroless plating and brazing plating are applied as needed, and as shown in FIG. ), form a base plating layer (8) for the through hole (5), then braze external metal leads such as pins (9) for terminals, and then solder with old solder such as Cu, Au, or Ag. If plating is performed using a metal with excellent affinity, the electrode metallized layer (3) and metallized layer (2) in the opening (7) will have a metal layer α0) suitable for soldering, as shown in Figure 4. It will be formed.
次に本願第３の発明の実施例を第５図〜第８図により詳
細に説明すると、先ず第５図に示されるように従来技法
により未焼成のセラミックグリーンシート（１１の表面
に半導体素子をマウントするためのメタライズ層（２）
と、半導体素子の多数の電極端子とワイヤポンディング
により接続されるフィンガパターン状の電極用メタライ
ズ層（３）とが形成され、またセラミックグリーンシー
ト＋１１には各電極用メタライズ層（３）と端子用のビ
ン（９）とを接続するための導電体（４）が充填された
スルーホール（５）が透設される。このようなセラミッ
クグリーンシート（１）は次に常法により焼成されてセ
ラミックシート（１）となるが、この際に焼成収縮を生
じて特に電極用メタライズ層（３）の寸法精度に狂いを
生ずることは従来と同様である。次に第６図に示される
ようにセラミックシート（１）の下面のスルーホール（
５）の部分にろう付け用のめっき層（８）が形成され、
端子用のビン（９）のような外部金属リードがろう付け
される。次にセラミックシート（１）の電極用メタライ
ズ層（３）を含む部分の表面全体に感光性電気絶縁層（
６）が塗布される。この感光性電気絶縁層（６）は後工
程のはんだ付け工程（約２００℃程度）及び半導体素子
のグイマウント工程等に耐えられる耐熱性を有する有機
塗料を用いることができる。なお、感光性電気絶縁層（
６）の材料として感光性ポリイミド、感光性ガラス等を
用い、半導体素子を囲むようにすると半導体素子のアル
ミナセラミックから放散されるα線を遮蔽できる効果が
ある。次に感光性電気絶縁層（６）は第７図に示される
ようにホトエツチングされ、本来電極用メタライズ層か
あるべき正確な位置に高精度で開口部（７）が形成され
る。このホトエツチングはセラミックシートの焼成収縮
とは無関係に光学的手段によって極めて正確に行われる
。その後、Ｎｉｓ Ａｕ、 Ａｇのようなはんだとの親
和性に優れた金属による仕上げめっきを施せば、第８図
に示されるように電解用メタライズ層（３）の表面が感
光性電気絶縁層（６）に覆われ、この感光性電気絶縁層
（６）の正確な位置にホトレジストにより開口部（７）
が形成されるとともに開口部（７）内にはんだとの親和
性に優れた金属ＮａＯが形成された半導体素子用パンケ
ージが得られることとなる。Next, the embodiment of the third invention of the present application will be described in detail with reference to FIGS. 5 to 8. First, as shown in FIG. Metallized layer for mounting (2)
A metallized layer (3) for electrodes in a finger pattern shape is formed to be connected to a large number of electrode terminals of a semiconductor element by wire bonding, and a metallized layer (3) for each electrode and a terminal are formed on the ceramic green sheet +11. A through-hole (5) filled with a conductor (4) for connection with a bottle (9) is provided. Such a ceramic green sheet (1) is then fired by a conventional method to become a ceramic sheet (1), but at this time, firing shrinkage occurs and the dimensional accuracy of the metallized layer (3) for electrodes in particular is disturbed. This is the same as before. Next, as shown in Figure 6, the through holes (
A plating layer (8) for brazing is formed on the part 5),
External metal leads such as pins (9) for terminals are brazed. Next, a photosensitive electrical insulating layer (
6) is applied. For this photosensitive electrical insulating layer (6), an organic paint having heat resistance that can withstand the subsequent soldering process (approximately 200° C.) and the semiconductor element mounting process can be used. In addition, the photosensitive electrical insulating layer (
If a photosensitive polyimide, photosensitive glass, or the like is used as the material in 6) to surround the semiconductor element, it is effective in shielding alpha rays emitted from the alumina ceramic of the semiconductor element. Next, the photosensitive electrical insulating layer (6) is photoetched as shown in FIG. 7, and openings (7) are formed with high precision at the exact positions where the electrode metallized layer should originally be. This photoetching is carried out very accurately by optical means, independent of firing shrinkage of the ceramic sheet. After that, by finishing plating with a metal that has excellent affinity with solder, such as Nis Au or Ag, the surface of the electrolytic metallized layer (3) becomes a photosensitive electrical insulating layer (6), as shown in Figure 8. ), and openings (7) are made with photoresist at precise locations in this photosensitive electrically insulating layer (6).
is formed, and a pancage for a semiconductor element is obtained in which metal NaO having excellent affinity with solder is formed in the opening (7).
（作用）
このようにして製造された半導体素子用パンケージは、
この開口部（７）内にはんだ等を流し込んで直接半導体
素子の端子又はＴＡＢ等による接続を行わせるものであ
り、セラミックグリーンシートの焼成時に不可避的に生
ずるセラミックシート（１）の焼成収縮によって電極用
メタライズＮ（３）の寸法精度が低下した場合にもその
表面の感光性電気絶縁層（６）にホトエツチングによっ
て正確に形成された開口部（７）を介して半導体素子の
電極等との接続を正しく行うことができる。従って本発
明によれば電極数が１００を越えるというような集積度
の高い半導体素子のためのパッケージを容易に製造する
ことができる。(Function) The semiconductor device pancage manufactured in this way is
Solder or the like is poured into this opening (7) to directly connect the semiconductor element with terminals or TAB, etc., and the electrodes are formed by the firing shrinkage of the ceramic sheet (1) that inevitably occurs when the ceramic green sheet is fired. Even if the dimensional accuracy of the metallized N (3) deteriorates, the connection to the electrodes of the semiconductor element etc. can be made through the openings (7) accurately formed by photoetching in the photosensitive electrical insulating layer (6) on the surface. can be done correctly. Therefore, according to the present invention, it is possible to easily manufacture a package for a highly integrated semiconductor element having more than 100 electrodes.
なお以上の説明では電極用メタライズ層（３）をワイヤ
ボンディング用のものとして説明したが、フリップチッ
プタイプのものにおいては半導体素子の下面の電極と直
接接触する点状電極が電極用メタライズ層（３）に相当
するものとなる。またリードレスタイプのパッケージに
あってはパッケージの下面に回路基板との接続用の多数
の点状の電極が形成されるが、この場合にはこれらの点
状電極が電極用メタライズ層（３）に相当するものとな
り、本発明をこれらの点状電極の形成にも適用できるこ
とは言うまでもない。In the above explanation, the electrode metallized layer (3) is used for wire bonding, but in flip-chip type devices, the electrode metallized layer (3) is used for dotted electrodes that directly contact the electrodes on the lower surface of the semiconductor element. ). In addition, in a leadless type package, many dot-like electrodes are formed on the bottom surface of the package for connection with the circuit board, but in this case, these dot-like electrodes are connected to the electrode metallization layer (3). It goes without saying that the present invention can also be applied to the formation of these point-like electrodes.
（発明の効果）
本発明は以上の説明からも明らかなように、不可避的に
生ずるセラミックシートの焼成収縮にかかわらず、ホト
レジスト法によって高精度の電極を形成することに成功
したものであるから、高集積度の半導体素子を支持する
ために好適な半導体素子用パッケージ及びその製造方法
として、産業の発展に寄与するところは極めて大である
。(Effects of the Invention) As is clear from the above description, the present invention has succeeded in forming highly accurate electrodes by the photoresist method regardless of the inevitable firing shrinkage of the ceramic sheet. The present invention will greatly contribute to the development of industry as a semiconductor device package suitable for supporting highly integrated semiconductor devices and a manufacturing method thereof.
第１図〜第４図は本願筒２の発明の実施例の製造工程を
示す断面図、第５図〜第８図は本願筒３の発明の実施例
の製造工程を示す断面図である。
（１）；セラミックシート、（３） ：電極用メタライ
ズ層、（６）：感光性電気絶縁層、（７）：開口部、ａ
Ｏ）：金属層。1 to 4 are cross-sectional views showing the manufacturing process of an embodiment of the invention of the cylinder 2 of the present application, and Figures 5 to 8 are sectional views showing the manufacturing process of the invention of the cylinder 3 of the present application. (1): Ceramic sheet, (3): Electrode metallized layer, (6): Photosensitive electrical insulation layer, (7): Opening, a
O): Metal layer.
Claims (1)
ライズ層（３）上に、ホトエッチングにより形成された
開口部（７）を有する感光性電気絶縁層（６）が被覆さ
れ、この開口部（７）内の電極用メタライズ層（３）上
にははんだとの親和性に優れた金属層（１０）が形成さ
れていることを特徴とする半導体素子用パッケージ。 ２、所要部分に電極用メタライズ層が形成されたセラミ
ックグリーンシートを焼成した後その電極用メタライズ
層を含む部分の表面全体に感光性電気絶縁層を形成し、
これをホトエッチングして正確な位置に開口部を形成し
たうえ、外部金属リードをろう付けし、その後はんだと
の親和性に優れた金属によるめっきを施して開口部内の
電極用メタライズ層上にはんだ付け用の金属層を形成す
ることを特徴とする半導体素子用パッケージの製造法。 ３、所要部分に電極用メタライズ層が形成されたセラミ
ックグリーンシートを焼成したうえ端子ピンのような外
部金属リードをろう付けし、該電極用メタライズ層を含
む部分の表面全体に感光性電気絶縁層を塗布し、その後
この感光性電気絶縁層をホトエッチングして正確な位置
に電極用メタライズ層に連通する開口部を形成し、その
後はんだとの親和性に優れた金属によるめっきを施して
開口部内のメタライズ層上にはんだ付け用の金属層を形
成することを特徴とする半導体素子用パッケージの製造
法。[Claims] 1. A photosensitive electrical insulating layer (6) having openings (7) formed by photoetching is provided on the electrode metallized layer (3) fired on the ceramic sheet (1). A semiconductor device package characterized in that a metal layer (10) having excellent affinity with solder is formed on the electrode metallized layer (3) in the opening (7). 2. After firing the ceramic green sheet on which the electrode metallized layer is formed in the required portions, a photosensitive electrical insulating layer is formed on the entire surface of the portion including the electrode metallized layer,
This is photo-etched to form openings at precise positions, external metal leads are brazed, and then plated with a metal that has excellent affinity with solder to solder onto the electrode metallized layer inside the openings. A method for manufacturing a package for a semiconductor device, comprising forming a metal layer for attachment. 3. After firing the ceramic green sheet on which the metallized layer for electrodes is formed in the required areas, external metal leads such as terminal pins are brazed, and a photosensitive electrical insulating layer is applied to the entire surface of the area including the metallized layer for electrodes. This photosensitive electrical insulating layer is then photoetched to form an opening that communicates with the electrode metallized layer at a precise location, and then plated with a metal that has excellent affinity with solder to fill the inside of the opening. A method for manufacturing a package for a semiconductor device, comprising forming a metal layer for soldering on a metallized layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6021886A JPS62216348A (en) | 1986-03-18 | 1986-03-18 | Package for semiconductor element and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6021886A JPS62216348A (en) | 1986-03-18 | 1986-03-18 | Package for semiconductor element and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62216348A true JPS62216348A (en) | 1987-09-22 |
| JPH0466386B2 JPH0466386B2 (en) | 1992-10-23 |
Family
ID=13135803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6021886A Granted JPS62216348A (en) | 1986-03-18 | 1986-03-18 | Package for semiconductor element and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62216348A (en) |
-
1986
- 1986-03-18 JP JP6021886A patent/JPS62216348A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0466386B2 (en) | 1992-10-23 |
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|---|---|---|---|
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