JPS62216285A - Drive circuit for light-emitting element - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] A light-emitting element drive circuit that has a configuration in which a Zener diode is connected to the source of a field-effect transistor to keep the source potential constant, and that drives a light-emitting element by the field-effect transistor, It is disclosed that the amplitude level of the pulse train voltage applied to the gate of the field effect transistor is controlled according to the mark rate, thereby preventing the output of one light emitting element from varying depending on the mark rate.

(Industrial Application) The present invention relates to a two-light emitting element drive circuit, particularly a light emitting element (hereinafter abbreviated as LD) using a field effect transistor (hereinafter abbreviated as FET) that uses a Zener diode to keep the source potential constant. ) The present invention relates to a light emitting element drive circuit that suppresses fluctuations in output due to fluctuations in mark ratio in the drive circuit.

[Conventional technology]

Conventionally, a nine-light emitting element drive circuit has a configuration as shown in FIG. 4(a). The code 1 in the figure is an FET.

2 is LD (or LED), 3 is Zener diode,
4 represents a bypass capacitor.

A Zener diode 3 connected to the source of the FET 1 is for keeping the source potential constant. When a pulse train voltage as shown in the figure is supplied to the gate of FET 1, LD 2 emits light in a pulsed manner in response.

[Problem that the invention seeks to solve]

In the configuration shown in FIG. 4(a), as the mark rate of the pulse train voltage supplied to the gate becomes smaller,
The period during which the Zener diode 3 is conductive is reduced, and the potential difference across the Zener diode becomes smaller on average.

Therefore, the source voltage is.

-■, and the source potential given as an average value decreases as shown in Figure 4 (b1).Assuming that the drain voltage is 1 due to the decrease in the source potential and is constant due to the voltage drop of D. As the voltage between the gate and source increases, the current flowing through the LD increases, as shown in FIG. 4(C).
The output pulse increases as the mark rate decreases.

To prevent this problem, the source potential should be kept constant regardless of the mark rate by some means, but no suitable means existed.

[Means for solving problems]

The present invention solves the above-mentioned problems, and FIG. 1+al shows a basic configuration diagram of the present invention. Code 1 in the figure is FET, 2
is LD (or LED), 3 is Zener diode, 4
5 represents a capacitor, and 5 represents a level control circuit prepared in the present invention.

The level control circuit 5 controls the mark rate of the pulse train voltage input to be applied to the gate of the FETI as shown in FIG.
1)) Control the amplitude level of the pulse train voltage as shown. That is, as explained in conjunction with the explanation of FIG. 4 with reference to the conventional circuit, since the potential of the source created by the Zener diode 3 fluctuates as shown in FIG. The amplitude level of the pulse train voltage supplied to the gate is controlled so as to cancel out the effects.

The mark rate signal supplied to the level control circuit 5 is as follows.

For example, a pulse train voltage input to be applied to the gate may be introduced into a low-pass filter to extract a DC voltage.

[Effect]

The pulse train voltage input to be applied to the gate is:

In the level control circuit 5, the amplitude level is controlled so as to have the relationship shown in FIG. 1 (h1) in accordance with the mark rate.

As a result, even if the source potential varies depending on the mark rate,
The amplitude level of the pulse train voltage is controlled to compensate for this, and as shown in FIG. 1 (Q), the output becomes independent of the mark rate.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the present invention. Code 1 in the figure.
2. 3. 4. 5 corresponds to FIG. 1, 6 is a comparator that outputs a voltage corresponding to the mark rate,
7 represents a control transistor, 8 represents a drive transistor, and 9 represents a clamp circuit.

Mark rate information is given to comparator 6, which controls the base potential of transistor 7. This controls the current in transistor 8 and the amplitude of the pulse train voltage supplied to the gate of FET 1. and,
The clamp circuit 9 is used to fix the "0" level potential of the signal input to the gate of the FETI, and only change the @1" level potential.

FIG. 3 shows an example of application of the circuit of the present invention to an automatic power control (APC) circuit in optical communications.

Reference numeral 2 in the figure corresponds to that in Figure 2, 10 is the circuit shown in Figure 2 (excluding the dotted line), and 11 is a bias current control circuit that supplies bias current from the dotted line in Figure 2. 12 is a monitor water diode, and 13 is a comparator.

1, the output from D2 is detected by a monitoring photodiode 12. Then, power control is performed through the comparator 13, and in the case shown in FIG.
At 0, power fluctuations due to mark rate fluctuations are suppressed, and power control is effectively performed.

〔Effect of the invention〕

As described above, according to one aspect of the present invention, it is possible to suppress fluctuations in the output caused by fluctuations in the mark rate of the pulse train voltage to be applied to the gate of the FET.

[Brief explanation of drawings]

FIG. 1 shows the principle configuration of the present invention, FIG. 2 shows an embodiment of the invention, FIG. 3 shows an application example of the invention, and FIG. 4 shows an explanatory diagram for explaining a conventional problem. In the figure, 1 represents a field effect transistor, and 2 represents a light emitting element circuit.

Claims (1)

[Claims] A light emitting element (2) is connected to the drain of the field effect transistor (1).
) and a Zener diode (3) is connected to the source of the field effect transistor (1), and the light emitting element (2) is connected in response to the pulse train voltage applied to the gate.
), the level control circuit (5) controls the amplitude level of the input pulse train voltage based on the result of detecting the mark rate of the input pulse train voltage to be applied to the gate.
1. A light emitting device driving circuit characterized in that the pulse train voltage whose amplitude level is controlled by the level control circuit (5) is supplied to the gate of the field effect transistor (1).