JPS62216250A - Manufacture of printed substrate type pga package - Google Patents
Manufacture of printed substrate type pga packageInfo
- Publication number
- JPS62216250A JPS62216250A JP24865685A JP24865685A JPS62216250A JP S62216250 A JPS62216250 A JP S62216250A JP 24865685 A JP24865685 A JP 24865685A JP 24865685 A JP24865685 A JP 24865685A JP S62216250 A JPS62216250 A JP S62216250A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- holes
- opening
- plate
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 title description 11
- 238000007747 plating Methods 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000003860 storage Methods 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 28
- 239000011889 copper foil Substances 0.000 abstract description 14
- 238000007493 shaping process Methods 0.000 abstract 1
- 229910052802 copper Inorganic materials 0.000 description 14
- 239000010949 copper Substances 0.000 description 14
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（発明の技術分野）
本発明はＰＧＡパッケージの製造方法に係り、特にプリ
ント基板型ＰＧＡパッケージの製造方法の改良に関する
。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method for manufacturing a PGA package, and more particularly to an improvement in a method for manufacturing a printed circuit board type PGA package.
（技術の背景）
従来からのＰＧ＾パッケージ（ピングリットアレイパッ
ケージ）はセラミックを使用していたため、高価であり
、低価格化が課題となっていた。そこで、近年、ガラス
繊維入り合成樹脂等の板体を積層してなるプリント基板
型ＰＧ＾パッケージが開発され、多ピン化への対応と低
価格化を同時に実現し得るようになってきた。(Technical background) Conventional PG^ packages (pin grid array packages) use ceramics and are therefore expensive, making cost reduction an issue. Therefore, in recent years, a printed circuit board type PG^ package, which is made by laminating plates made of glass fiber-containing synthetic resin, etc., has been developed, and it has become possible to simultaneously accommodate a large number of pins and reduce costs.
まず、このようなプリント基板型ＰＧＡパッケージの従
来の製造方法を第２図（Ａ）、 （Ｂ）により説明す
る。First, a conventional manufacturing method of such a printed circuit board type PGA package will be explained with reference to FIGS. 2(A) and 2(B).
第２図（Ａ）は、プリント基板型ＰＧ＾パッケージの基
板１の構成を示す説明図であり、この基板１の最下部に
は、上面に配線パターンが形成され所要のめっきが施さ
れる半導体素子搭載用の銅ＷＭ３が貼着され、下面には
配線パターンが形成され所要のめっきが施されるｗ４箔
４が貼着された絶縁材料製の板体２が配設されている。FIG. 2(A) is an explanatory diagram showing the structure of a substrate 1 of a printed circuit board type PG^ package. At the bottom of this substrate 1, a wiring pattern is formed on the upper surface and a semiconductor is coated with the required plating. A plate body 2 made of an insulating material is provided, on which a copper WM3 for mounting elements is adhered, and a W4 foil 4 on which a wiring pattern is formed and required plating is adhered on the lower surface.
この板体２上には、開口６が形成された絶縁材料製の板
体５が積層して貼着されるようになっており、この板体
５の上面には半導体素子実装用端子パターンが形成され
所要のめっきが施される銅箔７が貼着されている。この
板体５上には、板体５の開口６に合致し、かつこの間口
６より大きな開口９が形成された絶縁材料製の板体８が
積層して貼着されるようになっている。さらに、この板
体８上には、板体８の開口９に合致し、かつこの間口９
より大きな開口１１が形成された絶縁材料製の板体１０
が積層して貼着されるようになっている。この板体１０
の上面には、配線パターンが形成され所要のめっきが施
される銅箔１２が貼着されている。A plate 5 made of an insulating material and having an opening 6 formed therein is laminated and pasted on the plate 2, and a terminal pattern for mounting a semiconductor element is formed on the upper surface of the plate 5. A copper foil 7 that is formed and subjected to required plating is attached. A plate 8 made of an insulating material and having an opening 9 that matches the opening 6 of the plate 5 and is larger than the width 6 is laminated and pasted on the plate 5. . Furthermore, on this plate body 8, there is a space that matches the opening 9 of the plate body 8, and which
Plate body 10 made of insulating material with larger opening 11 formed therein
are layered and pasted together. This plate 10
A copper foil 12 on which a wiring pattern is formed and a required plating is applied is adhered to the upper surface of the .
このような第２図（Ａ）の各板体２，５，８゜１０によ
り第２図（Ｂ）に示す基板１を形成するには、まず板体
２，５間、板体５．８間ならびに板体８，１０間にそれ
ぞれ接着剤シー）１３，１４゜１５を介して、銅箔３．
７に所要の配線パターンが形成され所要のめっき（図示
しないが、一般にはニッケルめっき下地の金めつき）が
施された板体２．５．板体８．１０を積層して貼着する
。すると、各開口６，９．１１により半導体素子収納穴
１６が形成される。ついで、第２図（Ｂ）に示すように
、基板１に貫通孔１７． １？、・・・を形成し、各
貫通孔１７内に無電解銅めっき等のめっきを施し、板体
２の銅箔４および板体１０の銅箔１２に所要の配線パタ
ーンを形成し、所要のめっきを施す。さらにリードピン
（図示せず）をこの貫通孔１７に挿通してはんだ付は等
により固定することによりプリンＩ−基板型ＰＧ＾パッ
ケージとなる。In order to form the substrate 1 shown in FIG. 2(B) using the plates 2, 5, and 8° 10 of FIG. 2(A), first, between the plates 2 and 5, Copper foil 3.
7, a required wiring pattern is formed and required plating (not shown, but generally gold plating on a nickel plating base) is applied to the plate body 2.5. The plates 8 and 10 are laminated and pasted. Then, a semiconductor element housing hole 16 is formed by each opening 6, 9, 11. Next, as shown in FIG. 2(B), a through hole 17. is formed in the substrate 1. 1? . Apply plating. Further, lead pins (not shown) are inserted into the through holes 17 and fixed by soldering or the like, thereby forming a printed circuit board type PG^ package.
（従来技術の問題点）
しかしながら、このような従来の方法では貫ｉ１孔１７
へ無電解銅めっき等を施すと、めっきが金めっきされた
銅箔３や半導体素子実装用の金めっきされた端子パター
ンが形成された銅箔７はもとより基板１の全体に析出し
、端子パターンが全て短絡してしまう等の問題点があっ
た。(Problems with the prior art) However, in such a conventional method, the through hole 17
When electroless copper plating or the like is applied to the substrate, the plating is deposited not only on the gold-plated copper foil 3 and the copper foil 7 on which the gold-plated terminal pattern for mounting semiconductor elements is formed, but also on the entire substrate 1, and the terminal pattern is formed. There were problems such as all of them being short-circuited.
このため無電解銅めっきを基板１に施した後貫通孔１７
や貫通孔周囲の銅めっき必要部のみをエツチングレジス
トで被覆し、不要部分の銅めっきを選択的に剥離除去し
て金めつきが施された端子パターンを露出させて独立の
パターンにするか、または貫通孔等の銅めっき必要線以
外を予めマスキング状態で被覆しておき、必要部のみに
選択的に無電解銅めっきを施す必要があった。For this reason, after electroless copper plating is applied to the substrate 1, the through holes 17
Either cover only the parts that require copper plating around the through-holes with etching resist, selectively peel off the copper plating on unnecessary parts, and expose the gold-plated terminal pattern to create an independent pattern. Alternatively, it was necessary to cover lines other than lines requiring copper plating, such as through holes, in advance in a masked state, and selectively apply electroless copper plating only to the necessary areas.
従ってこのような方法では、エツチングレジストやマス
キング材の塗布や剥離除去という工程が必要で作業性が
悪く、また端子パターンの金めつき面がエツチングレジ
ストおよび銅めっきの剥離液、またはマスキング材の剥
離液に接触するため表面状態が悪化し、ワイヤボンディ
ング特性が低下する等の問題点があった。また、マスキ
ング材を使用した場合は、マスキング材上に析出した銅
めっき皮膜が箔状となってめっき液中に剥落して浮遊す
るため、めっき液の寿命を著しく損なうという問題点が
あった。Therefore, with this method, the process of applying and peeling off the etching resist or masking material is required, resulting in poor workability.In addition, the gold-plated surface of the terminal pattern may be exposed to the etching resist or copper plating stripping solution, or the stripping of the masking material. There were problems such as deterioration of the surface condition due to contact with liquid and deterioration of wire bonding characteristics. Further, when a masking material is used, there is a problem in that the copper plating film deposited on the masking material becomes a foil and peels off and floats in the plating solution, significantly shortening the life of the plating solution.
（発明の目的）
本発明は、前述した従来の製造方法における問題点を克
服し、銅箔３や銅箔７に１１通孔をめっきする際のめっ
きが被着しないようにしたプリント基板型ＰＧＡパッケ
ージの製造方法を提供することを目的としている。(Object of the Invention) The present invention overcomes the problems in the conventional manufacturing method described above, and provides a printed circuit board type PGA that prevents the plating from adhering when plating 11 through holes on the copper foil 3 and the copper foil 7. The purpose is to provide a method for manufacturing packages.
（発明の構成）
本発明は、積層された複数枚の板体に半導体素子収納穴
、貫通孔ならびに配線パターンが形成され、貫通孔には
メッキが施されているプリント基盤型ＰＧＡパッケージ
の製造方法において、前記積層された複数枚の板体は、
両外側の板体には半導体素子収納穴を形成するための開
口が形成されておらず、両外側の板体の外面を除く配線
パターンは、両外側の板体によって密閉されるように積
層されており、該積層された複数枚の板体に貫通孔を形
成するとともに貫通孔にめっきを施し、その後両外側の
板体の少なくとも一方に半導体素子収納穴を形成するた
めの開口を形成するようにしたことを特徴としている。(Structure of the Invention) The present invention provides a method for manufacturing a printed circuit board type PGA package in which a semiconductor element housing hole, a through hole, and a wiring pattern are formed in a plurality of laminated plates, and the through hole is plated. In the above, the plurality of laminated plates are:
No opening for forming a semiconductor element storage hole is formed in the outer plates, and the wiring pattern except for the outer surface of the outer plates is stacked so as to be sealed by the outer plates. A through-hole is formed in the plurality of laminated plates, and the through-hole is plated, and then an opening for forming a semiconductor element storage hole is formed in at least one of both outer plates. It is characterized by the fact that
（発明の実施例）
以下、本発明を第１図（Ａ）〜（Ｈ）に示す実施例によ
り説明する。なお、前述した従来のものと同一の構成に
ついては、図面中に同一の符号を付し、その説明は省略
する。(Embodiments of the Invention) The present invention will be described below with reference to embodiments shown in FIGS. 1(A) to 1(H). Note that the same components as those of the conventional device described above are denoted by the same reference numerals in the drawings, and the explanation thereof will be omitted.
第１図（Ｆ）に示すプリント基板型ＰＧＡパッケージの
基板１を形成するためには、第１図（Ａ）に示すように
、従来の方法において用いた３枚の板体２，５．８のほ
か開口の形成されていない板体１０Ａを用いる。そして
、板体２の銅ｔｆ３３ならびに板体５の銅箔７をそれぞ
れエツチングして配線パターンを形成する。その後、第
１図（Ｂ）に示すように、これらの配線パターン上に下
地にニッケルめっきを施した金の皮膜１８．１９をメッ
キにより被着する。ついで、第１図（Ｃ）に示すように
、接着剤シート１３．１４．１５により各板体２，５，
８．板体１０Ａを積層して接着する。In order to form the substrate 1 of the printed circuit board type PGA package shown in FIG. 1(F), as shown in FIG. 1(A), three plates 2, 5. In addition to the above, a plate body 10A having no openings is used. Then, the copper tf 33 of the plate 2 and the copper foil 7 of the plate 5 are etched to form a wiring pattern. Thereafter, as shown in FIG. 1(B), gold films 18 and 19 with a nickel-plated base are deposited on these wiring patterns by plating. Then, as shown in FIG. 1(C), each plate body 2, 5,
8. The plates 10A are stacked and bonded.
なお、板体８．板体１０Ａを接着するための接着剤シー
ト１５は、板体１０Ａに後で形成される開口１１Ａ（第
１図（Ｆ））の部位を接着しないよている。In addition, plate body 8. The adhesive sheet 15 for bonding the plate body 10A does not adhere to the opening 11A (FIG. 1(F)) that will be formed later in the plate body 10A.
つぎに、第１図（Ｄ）に示すように、板体２゜５．８．
板体１０Ａにかけて貫通孔１７．１７、・・・を形成し
、各貫通孔１７に無電解銅めっき２０を施し、各銅箔３
，４，７、＋２Ａに必要な電気的導通を与える。さらに
、第１図（Ｅ）に示すように、板体２の下面の銅箔４な
らびに、板体１０Ａの上面の銅Ｆｆｉ ｌ ２ Ａをエ
ツチングして配線パターン２１．２２を形成し、これら
の配線パターン２１゜２２および貫通孔に下地にニッケ
ルめっきを施した金の皮膜２３をめっきにより施してリ
ードピンを固定するための配線パターンを形成する。そ
して、最後に、第１図（Ｆ）に示すように、板体］ＯＡ
に開口１１Ａを穿設して、板体５．８の開口６゜９とと
もに半導体素子収納穴１６を形成する。Next, as shown in FIG. 1(D), the plate body 2°5.8.
Through holes 17, 17, .
, 4, 7, +2A. Furthermore, as shown in FIG. 1(E), the copper foil 4 on the lower surface of the plate 2 and the copper Ffil 2 A on the upper surface of the plate 10A are etched to form wiring patterns 21 and 22. A gold film 23 with a nickel-plated base is applied to the wiring patterns 21 and 22 and the through holes by plating to form a wiring pattern for fixing the lead pins. Finally, as shown in FIG. 1 (F), the plate] OA
An opening 11A is bored in the plate 5.8 to form a semiconductor element storage hole 16 together with the opening 6.9 of the plate 5.8.
この際板体１０Ａの開口１１Ａと接する部分の板体８の
上面には開口１１Ａを形成する際の力・ツタ−等により
若干の凹部が形成されるためこの面に配線パターンを設
けることは極めて困難である。At this time, it is extremely difficult to provide a wiring pattern on this surface because a slight recess is formed on the upper surface of the plate 8 in the part that contacts the opening 11A of the plate 10A due to the force, tumble, etc. when forming the opening 11A. Have difficulty.
この凹部は半導体素子搭載後に蓋体で気密封止する際の
接着剤流入凹部となり、不具合が生じる個所への接着剤
の流出を防止して、蓋体の接着強度を高めることができ
る。This recess serves as an adhesive inflow recess when airtightly sealing with the lid after mounting the semiconductor element, and prevents the adhesive from flowing out to areas where problems occur, thereby increasing the adhesive strength of the lid.
なお、第１図（Ｇ）に示すように板体１０Ａの開口１１
Ａの形成部全周に積層前に予め凹溝２４を形成しておく
ことにより、板体８に何ら影響を与えることなく開口１
１Ａを形成できるため、板体８にも配線パターンを形成
することができ、一層の多ピン化、高密度化が可能とな
る。この凹溝２４は開口形成部へ接着剤が流出し、板体
１０Ａの開口形成部が板体８と接着することを防止でき
る。また、板体８に配線パターンを形成する必要がない
場合は、板体８を取り去って板体５と板体１０Ａを直接
積層しても配線パターンを損なうことなく開口を形成す
ることもできるのでより小型化が可能となる。In addition, as shown in FIG. 1(G), the opening 11 of the plate body 10A
By forming the concave groove 24 in advance around the entire circumference of the forming part A before lamination, the opening 1 can be formed without affecting the plate body 8 in any way.
Since 1A can be formed, a wiring pattern can also be formed on the plate 8, making it possible to further increase the number of pins and increase the density. This groove 24 can prevent the adhesive from flowing out to the opening forming portion and preventing the opening forming portion of the plate body 10A from adhering to the plate body 8. Further, if it is not necessary to form a wiring pattern on the plate 8, the opening can be formed without damaging the wiring pattern even if the plate 8 is removed and the plate 5 and the plate 10A are directly laminated. Further downsizing is possible.
また第１図（Ｈ）に示すようにパッケージの熱放散性を
一層高めるために半導体素子を銅板等の放熱板２Ａ上に
搭載する場合には、板体５Ａの開口６Ａの形成は、貫通
孔１７にめっきを施し、板体１０Ａに開口１１Ａを形成
した後に行い、最後に放熱板２Ａを板体５Ａに貼着して
半導体素子収納穴を形成することにより、貫通孔１７に
無電解めっきを施す際に配線パターン７Ａにこのめっき
が被着することを阻止することができる。Further, as shown in FIG. 1(H), when a semiconductor element is mounted on a heat dissipating plate 2A such as a copper plate in order to further improve the heat dissipation performance of the package, the opening 6A of the plate 5A is formed as a through hole. Electroless plating is applied to the through hole 17 by plating the through hole 17 and forming the opening 11A in the plate 10A, and finally attaching the heat sink 2A to the plate 5A to form the semiconductor element storage hole. This plating can be prevented from adhering to the wiring pattern 7A during plating.
さらにこの場合には板体１０Ａに第１図（Ｇ）に示す凹
溝２４を形成することにより板体８を取り去ることが可
能となり、板体１０Ａ、５Ａの半導体素子収納穴を形成
するための開口は、貫通孔１７にめっきを施して後に形
成し、その後放熱板２人を貼着することもできる。Furthermore, in this case, by forming the groove 24 shown in FIG. 1(G) in the plate body 10A, the plate body 8 can be removed, and the groove 24 shown in FIG. 1(G) can be removed. The opening can also be formed after plating the through hole 17 and then attaching the two heat sinks.
以上述べたように本実施例によれば、半導体素子収納穴
１６の端に位置する板体１０Ａの開口１１Ａを最後に形
成するので、貫通孔１７にめっきを施す際にめっきが板
体２，５の銅箔３．７の配線パターンに被着するという
事態を確実に阻止することができる。As described above, according to this embodiment, the opening 11A of the plate body 10A located at the end of the semiconductor element storage hole 16 is formed last, so that when plating the through hole 17, the plating is applied to the plate body 2, It is possible to reliably prevent the copper foil 3.5 from adhering to the wiring pattern 7.
なお、銅箔３，７には、配線パターン形成後に所要のめ
っきを施さずに積層し、貫通孔１７に無電解銅めっき等
を施した後に開口１１Ａを形成し、金等のめっき皮膜２
３を施す際に同時に銅箔３゜７にも金等のめっき皮膜１
８．１９を形成することによっても、銅箔３，７には不
要な無電解銅めっき等が被着することを阻止することが
できる。Note that the copper foils 3 and 7 are laminated without any required plating after the wiring pattern is formed, and the opening 11A is formed after electroless copper plating or the like is applied to the through hole 17, and the plating film 2 of gold or the like is formed.
When applying step 3, a plating film 1 of gold etc. is also applied to the copper foil 3°7 at the same time.
8.19 also prevents unnecessary electroless copper plating from being deposited on the copper foils 3 and 7.
（発明の効果）
以上説明したように、本発明によれば、基板の貫通孔に
無電解めっき等を施す際に半導体素子収納穴内の配線パ
ターンにこのめっきが被着することを完全に阻止できる
ため、量産性に優れる等の効果を奏する。(Effects of the Invention) As explained above, according to the present invention, when electroless plating or the like is applied to the through-hole of a substrate, it is possible to completely prevent the plating from adhering to the wiring pattern in the semiconductor element housing hole. Therefore, it has advantages such as excellent mass productivity.
第１図（Ａ）、 （Ｂ）、 （Ｃ）、 （Ｄ）、
（Ｅ）。
（Ｆ）、 （Ｇ）、 Ｈ（）は本発明に係るプリン
ト基板型ＰＧＡパッケージの製造方法の実施例をしめず
説明図、第１図（Ａ＞、 （Ｂ）は従来の方法を示す
説明図である。
１・・・基板、
２．５，８，１０．ＩＯＡ・・・板体、６．９，１１．
ＩＩＡ・・・開口、
１６・・・半導体阻止収納穴、
１７・・・貫通孔、 ２４・・・凹溝。Figure 1 (A), (B), (C), (D),
(E). (F), (G), and H() are explanatory diagrams showing an embodiment of the method for manufacturing a printed circuit board type PGA package according to the present invention, and Figures 1 (A> and (B) are explanatory diagrams showing a conventional method. 1... Substrate, 2.5, 8, 10. IOA... Plate body, 6.9, 11.
IIA...Opening, 16...Semiconductor blocking storage hole, 17...Through hole, 24...Concave groove.
Claims (1)
孔ならびに配線パターンが形成され、貫通孔にはメッキ
が施されているプリント基盤型ＰＧＡパッケージの製造
方法において、前記積層された複数枚の板体は、両外側
の板体には半導体素子収納穴を形成するための開口が形
成されておらず、両外側の板体の外面を除く配線パター
ンは、両外側の板体によって密閉されるように積層され
ており、該積層された複数枚の板体に貫通孔を形成する
とともに貫通孔にめっきを施し、その後両外側の板体の
少なくとも一方に半導体素子収納穴を形成するための開
口を形成するようにしたことを特徴とするプリント基板
型ＰＧＡパッケージの製造方法。1. A method for manufacturing a printed circuit board type PGA package in which semiconductor element storage holes, through holes, and wiring patterns are formed in a plurality of laminated plates, and the through holes are plated. The two outer plates do not have openings for forming semiconductor element storage holes, and the wiring pattern except for the outer surface of the two outer plates is sealed by the outer plates. In order to form a through hole in the plurality of laminated plates and apply plating to the through hole, and then to form a semiconductor element storage hole in at least one of both outer plates. 1. A method for manufacturing a printed circuit board type PGA package, characterized in that an opening is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24865685A JPS62216250A (en) | 1985-11-06 | 1985-11-06 | Manufacture of printed substrate type pga package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24865685A JPS62216250A (en) | 1985-11-06 | 1985-11-06 | Manufacture of printed substrate type pga package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62216250A true JPS62216250A (en) | 1987-09-22 |
| JPH025014B2 JPH025014B2 (en) | 1990-01-31 |
Family
ID=17181373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24865685A Granted JPS62216250A (en) | 1985-11-06 | 1985-11-06 | Manufacture of printed substrate type pga package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62216250A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63255996A (en) * | 1987-04-14 | 1988-10-24 | シチズン時計株式会社 | Multilayer board for semiconductor chip mounting |
| JPH01112739A (en) * | 1987-10-27 | 1989-05-01 | Matsushita Electric Works Ltd | Printed circuit board for mounting electronic component |
| US5804422A (en) * | 1995-09-20 | 1998-09-08 | Shinko Electric Industries Co., Ltd. | Process for producing a semiconductor package |
| US6011694A (en) * | 1996-08-01 | 2000-01-04 | Fuji Machinery Mfg. & Electronics Co., Ltd. | Ball grid array semiconductor package with solder ball openings in an insulative base |
| US6040984A (en) * | 1996-02-27 | 2000-03-21 | Fuji Machinery Mfg. & Electronics Co., Ltd. | Printed circuit board with opposed bonding shelves for semiconductor chip wire bonding at different levels |
| KR100285116B1 (en) * | 1997-02-12 | 2001-06-01 | 모기 쥰이찌 | Manufacturing method of semiconductor package |
| CN103227164A (en) * | 2013-03-21 | 2013-07-31 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS568855A (en) * | 1979-07-04 | 1981-01-29 | Mitsubishi Electric Corp | Container for semiconductor |
| JPS5892248A (en) * | 1981-11-28 | 1983-06-01 | Mitsubishi Electric Corp | Large scale mounted semiconductor device |
| JPS59201449A (en) * | 1983-03-09 | 1984-11-15 | プリンテツド・サ−キツツ・インタ−ナシヨナル・インコ−ポレイテツド | Semiconductor chip carrier pacakge having heat sink and its producing method |
-
1985
- 1985-11-06 JP JP24865685A patent/JPS62216250A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS568855A (en) * | 1979-07-04 | 1981-01-29 | Mitsubishi Electric Corp | Container for semiconductor |
| JPS5892248A (en) * | 1981-11-28 | 1983-06-01 | Mitsubishi Electric Corp | Large scale mounted semiconductor device |
| JPS59201449A (en) * | 1983-03-09 | 1984-11-15 | プリンテツド・サ−キツツ・インタ−ナシヨナル・インコ−ポレイテツド | Semiconductor chip carrier pacakge having heat sink and its producing method |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63255996A (en) * | 1987-04-14 | 1988-10-24 | シチズン時計株式会社 | Multilayer board for semiconductor chip mounting |
| JPH01112739A (en) * | 1987-10-27 | 1989-05-01 | Matsushita Electric Works Ltd | Printed circuit board for mounting electronic component |
| US5804422A (en) * | 1995-09-20 | 1998-09-08 | Shinko Electric Industries Co., Ltd. | Process for producing a semiconductor package |
| US6040984A (en) * | 1996-02-27 | 2000-03-21 | Fuji Machinery Mfg. & Electronics Co., Ltd. | Printed circuit board with opposed bonding shelves for semiconductor chip wire bonding at different levels |
| US6011694A (en) * | 1996-08-01 | 2000-01-04 | Fuji Machinery Mfg. & Electronics Co., Ltd. | Ball grid array semiconductor package with solder ball openings in an insulative base |
| KR100285116B1 (en) * | 1997-02-12 | 2001-06-01 | 모기 쥰이찌 | Manufacturing method of semiconductor package |
| CN103227164A (en) * | 2013-03-21 | 2013-07-31 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH025014B2 (en) | 1990-01-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |