JPS6221018Y2 - - Google Patents
Info
- Publication number
- JPS6221018Y2 JPS6221018Y2 JP16390981U JP16390981U JPS6221018Y2 JP S6221018 Y2 JPS6221018 Y2 JP S6221018Y2 JP 16390981 U JP16390981 U JP 16390981U JP 16390981 U JP16390981 U JP 16390981U JP S6221018 Y2 JPS6221018 Y2 JP S6221018Y2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- diffusion layer
- terminal
- type region
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 7
- 230000002159 abnormal effect Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 24
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000007257 malfunction Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
Description
【考案の詳細な説明】
本考案は半導体素子が高周波サージ等によつて
誤動作するのを防ぐ半導体素子用入力保護装置に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input protection device for semiconductor devices that prevents semiconductor devices from malfunctioning due to high frequency surges and the like.
従来の半導体素子用入力保護装置として、例え
ば、第１図に示すものがあり、シリコン（Ｎ）基
板５にＰウエル４、P+拡散層８およびN+拡散層
９が形成され、Ｐウエル４にN+拡散層６および
P+拡散層７が形成されており、また、シリコン
基板５上に各拡散層６，７，８，９に通じるコン
タクトホールを有するシリコン酸化物絶縁層３が
形成されている。シリコン酸化物絶縁層３の表面
にはアルミニウム蒸着等によつて金属配線２が設
けられ、前記コンタクトホールを介して所定の電
気的接続が行われており、金属配線２の入力パツ
ド部２ａに入力保護抵抗となる多結晶シリコン抵
抗層１が接続されている。 As a conventional input protection device for a semiconductor device, for example , there is one shown in FIG. N + diffusion layer 6 and
A P + diffusion layer 7 is formed, and a silicon oxide insulating layer 3 having contact holes communicating with each diffusion layer 6, 7, 8, and 9 is formed on the silicon substrate 5. A metal wiring 2 is provided on the surface of the silicon oxide insulating layer 3 by aluminum evaporation or the like, and a predetermined electrical connection is made through the contact hole. A polycrystalline silicon resistance layer 1 serving as a protective resistance is connected.
第２図イは第１図の半導体素子用入力保護装置
の等価回路を示し、入力端子（入力パツド）２ａ
に入力保護抵抗１が接続され、P+拡散層８およ
びN+拡散層９より成るダイオード１３を介しＶD
Ｄ端子１１に接続され、N+拡散層６およびP+拡散
層７より成るダイオード１４を介してアースされ
（第１図の１２がアース端子）、端子１０より入力
信号が出力される。 Figure 2A shows an equivalent circuit of the input protection device for semiconductor devices in Figure 1, and shows the input terminal (input pad) 2a.
An input protection resistor 1 is connected to V D through a diode 13 consisting of a P + diffusion layer 8 and an N + diffusion layer 9.
It is connected to the D terminal 11 and grounded via a diode 14 consisting of the N + diffusion layer 6 and the P + diffusion layer 7 (12 in FIG. 1 is the ground terminal), and an input signal is output from the terminal 10.
以上の構成において、入力端子２ａに加えられ
る制御電圧に応じて出力端子１０に接続される半
導体素子が例えばMOSFETを含むICが制御さ
れ、一方、入力端子２ａに雑音として、例えば高
周波サージが入力したとき、該高周波サージの正
の部分に対してはダイオード１３によつてクラン
プし、負の部分に対してはダイオード１４によつ
てクランプすることによつて出力端子１０に接続
されるMOS FETのゲート酸化膜が絶縁破壊する
のを防ぎ、また、入力保護抵抗１がダイオード１
３，１４に流入する電流を抑制してダイオード１
３，１４を保護する。 In the above configuration, the semiconductor element connected to the output terminal 10 is controlled, for example, an IC including a MOSFET, according to the control voltage applied to the input terminal 2a, and on the other hand, when noise, for example, a high frequency surge, is input to the input terminal 2a. At this time, the gate of the MOS FET connected to the output terminal 10 is clamped by the diode 13 for the positive part of the high frequency surge, and by the diode 14 for the negative part. It prevents dielectric breakdown of the oxide film, and input protection resistor 1 is connected to diode 1.
Diode 1 suppresses the current flowing into 3 and 14.
Protect 3,14.
しかし、従来の半導体素子用入力保護装置によ
れば、第２図ロに示すように、ダイオード１３，
１４に流れ込んだ電流が基板５、各拡散層６，
７，８，９、およびＰウエル４等を介してICの
共通の電源ラインに流入するような構成になつて
いるため（１９はICの内部回路、例れば、
NAND，NOR等より成るゲート回路であり、１
５はインバータであり、１６はIC出力端子であ
る）、出力端子１６に表われる高周波サージによ
つて該端子１６に接続される装置（さらにまた半
導体素子が含まれ得る）が誤作動する恐れがあ
る。 However, according to the conventional input protection device for semiconductor devices, as shown in FIG.
The current flowing into the substrate 5, each diffusion layer 6,
7, 8, 9, P well 4, etc., to the common power supply line of the IC (19 is the internal circuit of the IC, for example,
It is a gate circuit consisting of NAND, NOR, etc.
5 is an inverter, 16 is an IC output terminal), and a high-frequency surge appearing at the output terminal 16 may cause a device connected to the terminal 16 (which may also include a semiconductor element) to malfunction. be.
本考案は、上記に鑑みてなされたものであり、
半導体素子が高周波サージ等によつて誤作動しな
いようにするため、クランプ（入力保護）用ダイ
オードに関し、第一導電型領域中に形成した第二
導電型領域と、該導電型領域をとり囲み、第二導
電型領域よりも深く形成した第一導電型の高濃度
不純物領域とを含み、該高濃度不純物領域が前記
半導体素子の電源ラインとは切り離された電源ラ
インに接続されている半導体素子用入力保護装置
を提供するものである。 This invention was made in view of the above,
In order to prevent the semiconductor element from malfunctioning due to high frequency surges, etc., a clamp (input protection) diode is provided with a second conductivity type region formed in the first conductivity type region, and surrounding the conductivity type region, for a semiconductor device, including a first conductivity type high concentration impurity region formed deeper than a second conductivity type region, and the high concentration impurity region is connected to a power supply line separated from the power supply line of the semiconductor element. It provides an input protection device.
以下本考案による半導体素子用入力保護装置を
詳細に説明する。 Hereinafter, the input protection device for semiconductor devices according to the present invention will be described in detail.
第３図イ，ロは本考案の第１の実施例を示し、
第１図と同一の部分は同一の引用数字で示したの
で重復する説明は省略するが、Ｐウエル４にN+
拡散層６を囲むようにして該拡散層６より深く拡
散したP+拡散層７ａが設けられ、P+拡散層８を
囲むようにして該拡散層８より深く拡散したN+
拡散層９ａが設けられ、N+拡散層６に接続され
た金属配電２ｂを金属配線２に接続する金属配線
１０ａ（出力端子１０に接続される）が設けら
れ、また、前記拡散層７ａ，９ａに接続された金
属配線２ｃ，２ｄは出力端子１０に接続される
IC内部回路１９等の電源ラインと切り離した電
源ラインに接続される端子２２（アース用）、端
子２１（ＶDD用）に接続されている（尚、IC内
部回路等用のＶDD端子１１（第１図）は図示上省
略されている。 Figures 3A and 3B show the first embodiment of the present invention,
The same parts as in FIG .
A P+ diffusion layer 7a is provided surrounding the diffusion layer 6 and is diffused deeper than the diffusion layer 6, and a P + diffusion layer 7a is provided surrounding the P + diffusion layer 8 and being diffused deeper than the diffusion layer 8 .
A diffusion layer 9a is provided, a metal wiring 10a (connected to the output terminal 10) is provided for connecting the metal power distribution 2b connected to the N + diffusion layer 6 to the metal wiring 2, and the diffusion layers 7a, 9a are provided. The metal wirings 2c and 2d connected to the output terminal 10 are connected to the output terminal 10.
It is connected to a terminal 22 (for ground) and a terminal 21 (for V DD ), which are connected to a power line separated from the power line for the IC internal circuit 19, etc. (Note that the V DD terminal 11 (for the IC internal circuit, etc.) 1) is omitted for illustration.
以上の構成において、IC内部では第４図に示
すように、ダイオード１３が接続されるＶDD端子
２１とIC内部回路等が接続されるＶDD端子１１
が切り離すことができ、かつ、ダイオード１４の
アース端子（ＶSS端子）も同じように切り離すこ
とができるため（この切り離し方法は、パツドを
それぞれ別にして共通のピンを使用してもよく、
あるいは、パツドおよびピンとも別々にしても良
い。言うまでもなく、後者の方が効果上望ましい
が、ピン数が増える）、入力端子２ａに入つた高
周波サージ等を適確にICの外部へバイパスする
ことができ、それによつてMOS FETあるいは
MOS FETを含むＣの誤動作を防ぐことができ
る。すなわちP+拡散層７ａがN+拡散層６よりN+
拡散層９がP+拡散層８より深いため、サージ電
流がＰウエル４および基板５を介して流れ込むの
を適確に防ぐことができる。 In the above configuration, inside the IC, as shown in FIG. 4, the V DD terminal 21 to which the diode 13 is connected and the V DD terminal 11 to which the IC internal circuit etc. are connected.
can be disconnected, and the ground terminal (V SS terminal) of the diode 14 can also be disconnected in the same way (this disconnection method can be done by separating each pad and using a common pin,
Alternatively, the pad and pin may also be separate. Needless to say, the latter is more desirable in terms of effectiveness, but the number of pins increases), and high-frequency surges that enter the input terminal 2a can be properly bypassed to the outside of the IC, thereby allowing the MOS FET or
Malfunction of C including MOS FET can be prevented. That is, the P + diffusion layer 7a is more N + than the N + diffusion layer 6.
Since the diffusion layer 9 is deeper than the P + diffusion layer 8, it is possible to appropriately prevent surge current from flowing through the P well 4 and the substrate 5.
第５図は本考案の第２の実施例を示し、前記第
１の実施例と同一の部分は同一の引用数字で示し
たので重復する説明は省略するが、P+拡散層８
ａを長方形状に長く拡散することによつて拡散抵
抗値を大にし、多結晶シリコン抵抗層１の抵抗値
との和（直列）によつてゲート保護能力を高めた
ものである。 FIG. 5 shows a second embodiment of the present invention, in which the same parts as in the first embodiment are indicated by the same reference numerals, so repeated explanations will be omitted, but the P + diffusion layer 8
By diffusing a into a long rectangular shape, the diffusion resistance value is increased, and the sum (in series) with the resistance value of the polycrystalline silicon resistance layer 1 increases the gate protection ability.
このように、基板５やＰウエル４を通過しての
サー電流は、深く形成した高不純物濃度領域から
吸い出し、上述の通り別個の電源ラインへバイパ
スされるので半導体素子への流れ込みが防止され
て誤動作を防ぐことができる。 In this way, the current passing through the substrate 5 and the P-well 4 is sucked out from the deeply formed high impurity concentration region and bypassed to a separate power supply line as described above, thereby preventing it from flowing into the semiconductor element. Malfunctions can be prevented.
以上説明した通り、本考案による半導体素子用
入力保護装置によれば、クランプ（入力保護用ダ
イオードに関し、第一導電型領域中に形成した第
二導電型領域と、該導電型領域をとり囲み、第二
導電型領域よりも深く形成した第一導電型の高濃
度不純物領域とを含み、該高濃度不純物領域が前
記半導体素子の電源ラインとは切り離された電源
ラインに接続されているため、高周波サージ等に
よつて生じる恐れがある半導体素子の誤作動を防
ぐことができる。 As explained above, according to the input protection device for a semiconductor device according to the present invention, the clamp (regarding the input protection diode, the second conductivity type region formed in the first conductivity type region, surrounding the conductivity type region, and a first conductivity type high concentration impurity region formed deeper than the second conductivity type region, and since the high concentration impurity region is connected to a power supply line separated from the power supply line of the semiconductor element, high frequency Malfunctions of semiconductor elements that may occur due to surges or the like can be prevented.
第１図は従来の半導体素子用入力保護装置を示
す断面図。第２図イは第１図の電気的等価回路
図、第２図ロはIC内部で高周波サージが伝播す
る状況を示す回路図、第３図イ，ロは本考案の第
１の実施例を示し、イは平面図、ロはイのＡ−Ａ
断面図。第４図は第１の実施例におけるIC内部
の高周波サージ遮断状況を示す回路図。第５図は
本考案の第２の実施例を示す断面図。
符号の説明、１……多結晶シリコン抵抗層、２
ａ……入力端子、２，２ｂ，２ｃ，２ｄ……金属
配線、３……シリコン酸化物絶縁層、４……Ｐウ
エル、５……シリコン基板、６，７，７ａ，８，
８ａ，９，９ａ……拡散層、１０……出力端子、
１０ａ……金属配線、１１，２１……ＶDD端子、
１２，２２……アース端子（ＶSS端子）、１３，
１４……クランプ用ダイオード。
FIG. 1 is a sectional view showing a conventional input protection device for semiconductor devices. Figure 2A is an electrical equivalent circuit diagram of Figure 1, Figure 2B is a circuit diagram showing the situation in which a high frequency surge propagates inside the IC, and Figures 3A and 3B are the electrical equivalent circuit diagram of Figure 1. A is a plan view, B is A-A of A
Cross-sectional view. FIG. 4 is a circuit diagram showing the high frequency surge cutoff situation inside the IC in the first embodiment. FIG. 5 is a sectional view showing a second embodiment of the present invention. Explanation of symbols, 1...Polycrystalline silicon resistance layer, 2
a...Input terminal, 2, 2b, 2c, 2d...Metal wiring, 3...Silicon oxide insulating layer, 4...P well, 5...Silicon substrate, 6, 7, 7a, 8,
8a, 9, 9a...diffusion layer, 10...output terminal,
10a...Metal wiring, 11, 21...V DD terminal,
12, 22...Earth terminal (V SS terminal), 13,
14...Clamp diode.
Claims (1)
該半導体素子を異常電圧から保護する保護用ダイ
オードを備えた入力保護装置において、 前記保護用ダイオードは、第一導電型領域中に
形成された第二導電型領域と、該第二導電型領域
をとり囲み、第二導電型領域よりも深く形成され
た第一導電型の高濃度不純物領域とを含み、該高
濃度不純物領域が前記半導体素子の電源ラインと
は切り離された電源ラインに接続されていること
を特徴とする半導体素子用入力保護装置。[Claims for Utility Model Registration] An input protection device including a protection diode on an input line for inputting a control signal to a semiconductor device to protect the semiconductor device from abnormal voltage, wherein the protection diode is in a first conductivity type region. a second conductivity type region formed therein, and a first conductivity type high concentration impurity region surrounding the second conductivity type region and formed deeper than the second conductivity type region, the high concentration impurity region 1. An input protection device for a semiconductor device, wherein the region is connected to a power supply line separated from the power supply line of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16390981U JPS5868043U (en) | 1981-11-02 | 1981-11-02 | Input protection device for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16390981U JPS5868043U (en) | 1981-11-02 | 1981-11-02 | Input protection device for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5868043U JPS5868043U (en) | 1983-05-09 |
| JPS6221018Y2 true JPS6221018Y2 (en) | 1987-05-28 |
Family
ID=29956186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16390981U Granted JPS5868043U (en) | 1981-11-02 | 1981-11-02 | Input protection device for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5868043U (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6014460A (en) * | 1983-07-04 | 1985-01-25 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
| JPS61137359A (en) * | 1984-12-10 | 1986-06-25 | Nec Corp | Protective circuit |
| JPH0525250Y2 (en) * | 1985-10-08 | 1993-06-25 | ||
| JPH06105740B2 (en) * | 1987-05-27 | 1994-12-21 | 日本電気株式会社 | Integrated circuit device |
-
1981
- 1981-11-02 JP JP16390981U patent/JPS5868043U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5868043U (en) | 1983-05-09 |
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