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JPS62209831A - Manufacture of silicon oxide film - Google Patents

Manufacture of silicon oxide film

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Publication number
JPS62209831A
JPS62209831A JP5148486A JP5148486A JPS62209831A JP S62209831 A JPS62209831 A JP S62209831A JP 5148486 A JP5148486 A JP 5148486A JP 5148486 A JP5148486 A JP 5148486A JP S62209831 A JPS62209831 A JP S62209831A
Authority
JP
Japan
Prior art keywords
silicon oxide
oxide film
deposition rate
frequency power
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5148486A
Other languages
Japanese (ja)
Inventor
Yuichi Masaki
裕一 正木
Katsuaki Sakamoto
勝昭 坂本
Hiroaki Kakinuma
柿沼 弘明
Tsukasa Watanabe
渡辺 宦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP5148486A priority Critical patent/JPS62209831A/en
Publication of JPS62209831A publication Critical patent/JPS62209831A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To facilitate formation of a high performance silicon oxide film which conforms to three conditions, i.e., small internal stress, high resistance and high deposition rate, by a method wherein a radio frequency power, which is applied when the silicon oxide film is deposited, is set at the specific magnification. CONSTITUTION:A plasma CVD apparatus is constituted by a vacuum reaction furnace, a vacuum pump system for evacuating the reaction furnace, a gas introducing system for introducing a material gas into the reaction furnace, a radio frequency source (frequency=13.56MHz) for generating a plasma and electrodes. When a silicon oxide film is deposited on a substrate by plasma CVD with the material gas containing silane system gas, a radio frequency power P applied to the reaction system is set within a range of 2-3.3 times of a saturation starting power Ps at which a deposition rate (D.R.) is saturated with predetermined temperature, gas flow and pressure. With this constitution, a silicon oxide film which conforms to conditions of small internal stress, high resistance and high deposition rate can be formed.

Description

【発明の詳細な説明】 〔産業上の利用分骨〕 この発明は、プラズマCVD法による高特性を有するシ
リコン酸化膜の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a method for manufacturing a silicon oxide film having high properties by plasma CVD.

〔従来の技術〕[Conventional technology]

シリコン酸化膜(Sin、)は絶縁性に優れ、しかもド
ナ、アクセプタの拡散係数が小さいこと等から、半導体
素子の製造プロセスにおいて、選択拡訴マスク一層間絶
縁臆及びパッシベーション膜と広範囲に渡って用いられ
ている。
Silicon oxide film (Sin) has excellent insulating properties and low donor and acceptor diffusion coefficients, so it is widely used as a selective mask, interlayer insulation film, and passivation film in the manufacturing process of semiconductor devices. It is being

このシリコン酸化膜の製造方法としては、高温熱酸化法
、CVD法等があるが、CVD法のうち特にプラズマC
VD法は成膜温度が低いという特徴を有する。以下、こ
のプラズマCVD法を用いた従来のシリコン酸化膜の製
造方法を簡単に説明する。原料ガスとしてアルゴンガス
(Ar)によって希釈されたシランガス(SiH2)ト
笑気がス(Nto)とを用い、この原料ガスを真空に引
いた減圧下(数Pa〜数百Pa)の反応系に流量を調整
しながら導入する。この反応系に高周波グロー放電を起
こして非平衡プラズマを作り、分解生成物の気相中また
は基板上での化学反応によって、被堆積物である基板上
にシリコン酸化膜を堆積させる。なお、この時の基板温
度は200〜300℃程度に保持される(ジャーナル 
オツ エレクトロケミカルソサエティ:ソリッド−ステ
ート サイエンスアンド テクノp)(J、Elect
rochem、Soc、 :5OLID−8TATE 
 5CIENCE  AND  TECHNOLOGY
)Vol、 128  Nl 71981 (7月) 
P、1545〜1551参照)。
Methods for producing this silicon oxide film include high-temperature thermal oxidation, CVD, etc. Among the CVD methods, especially plasma carbon
The VD method is characterized by low film formation temperature. A conventional method of manufacturing a silicon oxide film using this plasma CVD method will be briefly described below. Using silane gas (SiH2) diluted with argon gas (Ar) and laughing gas (Nto) as raw material gases, the raw material gases are evacuated into a reaction system under reduced pressure (several Pa to several hundred Pa). Introduce while adjusting the flow rate. A high-frequency glow discharge is generated in this reaction system to create non-equilibrium plasma, and a silicon oxide film is deposited on the substrate as a deposition target by a chemical reaction in the gas phase of the decomposition product or on the substrate. Note that the substrate temperature at this time is maintained at approximately 200 to 300°C (journal
Otsu Electrochemical Society: Solid-State Science and Technology p) (J, Elect
rochem, Soc, :5OLID-8TATE
5CIENCE AND TECHNOLOGY
) Vol, 128 Nl 71981 (July)
P, 1545-1551).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、上述したプラズマCVD法を用いてシリ
コン酸化膜を形成する場合、その形成条件は温度、高周
波電力及びガス成分等に大きく依存するものであり、形
成されるシリコン酸化膜がアモルファスで熱的に準平衡
状態の為内部応力(圧縮応力又は引張応力)が極めて大
きいことと相まって、最適な形成条件に基自特性的に十
分なものを得ることが困難であるという問題があった。
However, when forming a silicon oxide film using the above-mentioned plasma CVD method, the formation conditions largely depend on temperature, high frequency power, gas components, etc., and the silicon oxide film formed is amorphous and thermally unstable. Coupled with the fact that the internal stress (compressive stress or tensile stress) is extremely large due to the quasi-equilibrium state, there is a problem in that it is difficult to obtain sufficient basic characteristics under optimal forming conditions.

実際、電気的絶縁やパッジベージ日ンを目的として膜厚
の大きなシリ、コン酸化膜を形成すると、被膜のクラッ
クや基板からの剥離等が生じ易い。
In fact, when a thick silicon or silicon oxide film is formed for the purpose of electrical insulation or padding, cracks in the film and peeling from the substrate tend to occur.

また半導体素子の製造プロセスに適用する場合、上述し
た内部応力を抑える他、高抵抗、高堆積速度という条件
も同時に満足することが必要であり、従来これが製造プ
ロセス上重要な問題となっていた。
Furthermore, when applied to the manufacturing process of semiconductor devices, it is necessary to suppress the internal stress described above, and also satisfy the conditions of high resistance and high deposition rate, which has conventionally been an important problem in the manufacturing process.

従って本発明は、以上の様な問題を解消する為になされ
たもので、形成条件のうち高周波電力に着目し、小さい
内部応力、高抵抗及び高堆積速度の3条件を同時に満足
するシリコン酸化膜の製造方法を提供することを目的と
する。
Therefore, the present invention has been made to solve the above problems, and focuses on high frequency power among the formation conditions, and creates a silicon oxide film that simultaneously satisfies the three conditions of low internal stress, high resistance, and high deposition rate. The purpose is to provide a manufacturing method for.

〔問題点を解決するための手段〕[Means for solving problems]

本発明に係るシリコン酸化膜の製造方法は、シラン系ガ
スを含む原料ガスを用い、プラズマCVD法によって基
板上にシリコン酸化膜を堆積する場合に、反応系に印加
する高周波電力を、所定の基板温度、ガス流量及び気圧
で堆積速度が飽和する飽和開始電力の2〜3.3倍の範
囲に設定するようにしたものである。
The method for manufacturing a silicon oxide film according to the present invention uses a raw material gas containing a silane gas to deposit a silicon oxide film on a substrate by plasma CVD, and the high frequency power applied to the reaction system is applied to a predetermined substrate. The temperature, gas flow rate, and atmospheric pressure are set in a range of 2 to 3.3 times the saturation starting power at which the deposition rate is saturated.

〔作 用〕[For production]

本発明によれば、シリコン酸化膜を製造するに際し以上
のような方法を採るようにしたので、内部応力が小さく
しかも高抵抗、高堆積速度を満たすシリコン酸化膜を形
成することができる。
According to the present invention, since the above-described method is adopted when manufacturing a silicon oxide film, it is possible to form a silicon oxide film with low internal stress, high resistance, and high deposition rate.

〔実施例〕〔Example〕

以下、第1図ないし第3図に基き、本発明の一実施例を
詳細に説明する。なおプラズマCVD装置は、周知のよ
うに真空反応炉、反応炉を真空にする為の真空ポンプ系
、原料ガスを反応炉へ導入する為のガス導入系、プラズ
マを発生させる為の高周波電源(屑波数−13,56M
Hz )及び電極から構成されている。
Hereinafter, one embodiment of the present invention will be described in detail based on FIGS. 1 to 3. As is well known, a plasma CVD apparatus consists of a vacuum reactor, a vacuum pump system to make the reactor a vacuum, a gas introduction system to introduce raw material gas into the reactor, and a high-frequency power supply (waste) to generate plasma. Wave number -13,56M
Hz) and electrodes.

シリコン酸化膜(Sin2)を堆積させる為の基板とし
ては、ガラス、金属、結晶シリコン等を用いる。そして
基板をアース側の電極に配置させて、所定の到達真空度
となるように反応炉を排気する。
Glass, metal, crystalline silicon, or the like is used as the substrate on which the silicon oxide film (Sin2) is deposited. Then, the substrate is placed on the ground-side electrode, and the reactor is evacuated to a predetermined ultimate vacuum level.

次に、原料ガスとして水素ガス(Hl)で1%に希釈さ
れたシランガス(St)L)と笑気がス(N、O)とを
流量比(NtO:l l (SiH*) = 120で
混合したガスを用い、そのガス流量を0.5〜3 SL
M程度として反応炉内に導入し、反応炉内の圧力を80
〜120Pa程度に保つ。この状態で電極に高周波電場
を加えグロー放電を行うと、原料ガスがグロー放電のエ
ネルギーによって分解され基板上にシリコン酸化膜が堆
積する。この時、基板温度を200〜300℃程度に保
持する。
Next, silane gas (St) diluted to 1% with hydrogen gas (Hl) as a raw material gas and laughing gas (N, O) were mixed at a flow rate ratio (NtO:l (SiH*) = 120). Using a mixed gas, the gas flow rate is 0.5 to 3 SL.
The pressure inside the reactor was increased to 80°C.
Maintain the pressure at ~120 Pa. When a high frequency electric field is applied to the electrode in this state to cause glow discharge, the source gas is decomposed by the energy of the glow discharge and a silicon oxide film is deposited on the substrate. At this time, the substrate temperature is maintained at about 200 to 300°C.

ここにおいて高周波電力Pを0〜250Wtで変化する
と、堆積速度り、R,の高周波電力P依存性+、J−内
管16”711/ ;亭−h frn  /  l−f
’s、 M     1 7%j  ■61妊11f 
6)Rfp−る領域が得られる。なお第2図及び第3図
は、基板温度を230℃、上述した原料ガスのガス流量
を1.58LM、反応炉内の圧力を100PaK設定し
た場合の、内部応力S及び抵抗率Rの高周波電力依存性
を夫々示したものである。また抵抗率の測定は、測定電
界をI MV/cm、 2 MV/an及び3 MV/
mの3水準としている。
Here, when the high frequency power P is changed from 0 to 250 Wt, the deposition rate R, the high frequency power P dependence of R, +, J-inner tube 16"711/; tei-h frn/l-f
's, M 1 7%j ■61 pregnancy 11f
6) An Rfp region is obtained. Note that FIGS. 2 and 3 show the high-frequency power of internal stress S and resistivity R when the substrate temperature is set to 230°C, the gas flow rate of the above-mentioned raw material gas is set to 1.58LM, and the pressure inside the reactor is set to 100 PaK. This shows the dependence of each. In addition, when measuring resistivity, the measurement electric field is set to I MV/cm, 2 MV/an, and 3 MV/an.
There are three levels: m.

以下、各領域における高周波電力と、堆積速度、内部応
力及び抵抗率との関係について述べる。まず領域(1)
は、高周波電力に比例して堆積速度が増加する領域で、
第2図及び第3図ではO≦P≦60の範囲に相当する。
The relationship between high frequency power, deposition rate, internal stress, and resistivity in each region will be described below. First, area (1)
is the region where the deposition rate increases in proportion to the radio frequency power;
In FIGS. 2 and 3, this corresponds to the range O≦P≦60.

内部応力は、高周波電力の増加に比例して圧縮応力が増
加する(第2図)c。
As for the internal stress, the compressive stress increases in proportion to the increase in high frequency power (Fig. 2) c.

また電気的抵抗率は、高周波電力の増加に対して各水準
ともやや減少する。
Furthermore, the electrical resistivity slightly decreases at each level as the high frequency power increases.

次に領域(n)は、高周波電力の増加に対し堆積速度が
飽和する領域で、その飽和開始を与える高周波電力、即
ち飽和開始電力をPs(第1図)とすればPs < P
 < 2.7 Psの範囲を指す。第2図及び第3図で
は、60≦P≦120の範囲に相当する。なお基板温度
230℃、ガス流量1.5SLM。
Next, region (n) is a region where the deposition rate is saturated as the radio frequency power increases.If the radio frequency power that starts saturation, that is, the saturation start power, is Ps (Fig. 1), then Ps < P.
<2.7 Ps. In FIGS. 2 and 3, this corresponds to a range of 60≦P≦120. Note that the substrate temperature was 230°C and the gas flow rate was 1.5SLM.

圧力100 Paの上記条件では、堆積速度の飽和開始
値は160A/−程度である。内部応力は、第2図に示
されるように、この領域において高周波電力Pの増加に
伴い圧縮応力から引張応力へと転する。
Under the above conditions of pressure 100 Pa, the saturation start value of the deposition rate is about 160 A/-. As shown in FIG. 2, the internal stress changes from compressive stress to tensile stress as the high frequency power P increases in this region.

この為、途中に内部応力を零とする高周波電力P0(第
1図)が存在する。第2図及び第3図では、PO=12
0Wである。このPoで堆積した被膜は、第3図に示す
如く抵抗率も極大となる。
For this reason, there is a high frequency power P0 (FIG. 1) that makes the internal stress zero in the middle. In Figures 2 and 3, PO=12
It is 0W. The film deposited with Po has a maximum resistivity as shown in FIG.

そして領域(In)は堆積速度が飽和した後、再び増加
傾向を示す領域で(形成条件によっては増加を示さない
場合もあるが、後述する内部応力と抵抗率の動向は変わ
らない。)、第2図及び第3Fl!JではP≧160に
相当する。内部応力は、第2図のように高周波電力Pの
増加に伴い引張応力から圧縮応力へと転する。この為、
再度内部応力を零とする高周波電力pt(第1図)がこ
の領域に存在する。第2図及び第3図では、pi=2o
owである。また抵抗率は、第3Fg!Jの如く高周波
電力Pの増加に対し減少する。
The region (In) is a region that shows an increasing tendency again after the deposition rate is saturated (depending on the formation conditions, it may not show an increase, but the trends of internal stress and resistivity, which will be described later, do not change). Figure 2 and 3rd Fl! In J, this corresponds to P≧160. As shown in FIG. 2, the internal stress changes from tensile stress to compressive stress as the high frequency power P increases. For this reason,
A high frequency power pt (FIG. 1) that makes the internal stress zero again exists in this region. In Figures 2 and 3, pi=2o
It is OW. Also, the resistivity is the 3rd Fg! J decreases as the high frequency power P increases.

内部応力の点からすれば内部応力=0が理想的であるが
、基板と被膜との付着力を考慮すると、圧縮・引張応力
ともにI X 10’ dyne/−程度内であれば実
用上問題はない。一方抵抗率は、各水準とも広範囲に渡
って1014Ω・G を超える高抵抗率を示しており、
半導体素子の製造プロセスに適用するには十分な値を示
している。
From the point of view of internal stress, it is ideal that internal stress = 0, but considering the adhesion between the substrate and the coating, there is no practical problem if both compressive and tensile stress are within about I x 10' dyne/-. do not have. On the other hand, the resistivity shows a high resistivity exceeding 1014Ω・G over a wide range at each level.
This value is sufficient for application to the manufacturing process of semiconductor devices.

以上述べたように、基板からの被膜の剥離が起こらない
小さな内部応力を与える高周波電力は、堆積速度が飽和
し始める飽和開始電力をPaとすると2 Pa≦P≦3
.3 Psの範囲にある。第2図及び第3図で言えば、
120≦P≦200に相当する。
As mentioned above, the high frequency power that provides a small internal stress that does not cause peeling of the film from the substrate is 2 Pa≦P≦3, where Pa is the saturation starting power at which the deposition rate starts to become saturated.
.. It is in the range of 3 Ps. In terms of Figures 2 and 3,
This corresponds to 120≦P≦200.

上記範囲の条件を用いることによって、小内部応力、高
抵抗及び高堆積速度の3条件を満たしたシリコン酸化膜
を形成することができる。
By using the conditions in the above range, it is possible to form a silicon oxide film that satisfies the three conditions of low internal stress, high resistance, and high deposition rate.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によれば、シラン系
ガスを含む原料ガスを用いてプラズマCVD法によって
基板上にシリコン酸化膜を堆積する際に、印加する高周
波電力を、所定のガス流量、反応炉内の圧力で堆積速度
の飽和開始を与える飽和開始電力の2〜3.3倍の間に
設定するようにしたので、小内部応力、高抵抗、高堆積
速度の3条件を同時に満たした高特性シリコン酸化膜を
得ることができる。
As explained in detail above, according to the present invention, when depositing a silicon oxide film on a substrate by plasma CVD using a raw material gas containing a silane gas, the applied high frequency power is adjusted to a predetermined gas flow rate. Since the pressure inside the reactor was set between 2 and 3.3 times the saturation start power, which gives the start of saturation of the deposition rate, the three conditions of low internal stress, high resistance, and high deposition rate were simultaneously satisfied. A silicon oxide film with high properties can be obtained.

従って、本発明は半導体素子の特性向上、信頼度向上を
実現するものであり、極めて高い工業的利用価値を有す
る。
Therefore, the present invention improves the characteristics and reliability of semiconductor devices, and has extremely high industrial utility value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明における堆積速度の高周波電力依存性を
示す特性図、第2図は同様の内部応力の高周波電力依存
性を示す特性図、第3図は同様の抵抗率の高周波電力依
存性を示す特性図である。 Ps・・・堆積速度の飽和開始を与える飽和開始電力、
Po = Pt・・・内部応力=0を与える高周波電力
。 特許出願人 沖電気工業株式会社 高廟褒を力 Iv1周流電流電力W) る周1丸呪力(W)
Figure 1 is a characteristic diagram showing the dependence of deposition rate on high frequency power in the present invention, Figure 2 is a characteristic diagram showing the dependence of similar internal stress on high frequency power, and Figure 3 is a similar diagram showing the dependence of resistivity on high frequency power. FIG. Ps...Saturation start power that gives the start of saturation of the deposition rate;
Po = Pt... High frequency power that gives internal stress = 0. Patent applicant: Oki Electric Industry Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] (1)シラン系ガスを含む原料ガスを用い、プラズマC
VD法により基板上にシリコン酸化膜を堆積するシリコ
ン酸化膜の製造方法において、反応系に印加する高周波
電力を、所定の基板温度、ガス流量及び気圧で堆積速度
の飽和開始を与える飽和開始電力の2〜3.3倍の範囲
に設定することを特徴とするシリコン酸化膜の製造方法
(1) Plasma C using source gas containing silane gas
In a method for manufacturing a silicon oxide film in which a silicon oxide film is deposited on a substrate by the VD method, the high frequency power applied to the reaction system is adjusted to a saturation start power that starts to saturate the deposition rate at a predetermined substrate temperature, gas flow rate, and atmospheric pressure. A method for manufacturing a silicon oxide film, characterized in that the film is set in a range of 2 to 3.3 times.
JP5148486A 1986-03-11 1986-03-11 Manufacture of silicon oxide film Pending JPS62209831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5148486A JPS62209831A (en) 1986-03-11 1986-03-11 Manufacture of silicon oxide film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5148486A JPS62209831A (en) 1986-03-11 1986-03-11 Manufacture of silicon oxide film

Publications (1)

Publication Number Publication Date
JPS62209831A true JPS62209831A (en) 1987-09-16

Family

ID=12888229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5148486A Pending JPS62209831A (en) 1986-03-11 1986-03-11 Manufacture of silicon oxide film

Country Status (1)

Country Link
JP (1) JPS62209831A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5039625A (en) * 1990-04-27 1991-08-13 Mcnc Maximum areal density recessed oxide isolation (MADROX) process
US20140238574A1 (en) * 2013-02-27 2014-08-28 Yale University Design of a mold for forming complex 3d mems components
CN112760615A (en) * 2020-12-17 2021-05-07 武汉新芯集成电路制造有限公司 Silicon dioxide film and low-temperature preparation method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5039625A (en) * 1990-04-27 1991-08-13 Mcnc Maximum areal density recessed oxide isolation (MADROX) process
US20140238574A1 (en) * 2013-02-27 2014-08-28 Yale University Design of a mold for forming complex 3d mems components
US9249015B2 (en) * 2013-02-27 2016-02-02 International Business Machines Corporation Mold for forming complex 3D MEMS components
CN112760615A (en) * 2020-12-17 2021-05-07 武汉新芯集成电路制造有限公司 Silicon dioxide film and low-temperature preparation method thereof

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