JPS62205470A - Image memory multi-processing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multi-processing circuit for an image memory, and in particular,
Color information and image information output from a line segment interpolator (hereinafter referred to as DDA), which is used in graphic display devices, is written into an image memory, and a color graphic is created based on the written color information and image information. The present invention relates to a multi-processing circuit for an image memory that displays images on a CRT monitor.

[Prior Art] FIG. 4 is a schematic block diagram of an image memory control section of a graphic display device, which is the background of the present invention.

First, a conventional image memory control section will be explained with reference to FIG. DDAl is a vector-rusk converter for writing image information representing a figure to be displayed on the CRT monitor 11 into the image memories 3, 4, and 5 as rask information. That is, DDAI interpolates vector information having a starting point and an ending point between the starting point and the ending point, and converts it into rask information in pixel units. The pixel information a output from DDAl is sent to the write control unit 2 together with the store control signal C.
given to. The write control unit 2 stores the pixel information a as the brightness pixel data d in response to the store control signal.

output as e and color pixel data f, and store signal C
is converted into a write signal 0. The brightness pixel data d output from the write control unit 2 is given to the image memory 3, the brightness pixel data e is given to the image memory 4, the color pixel data f is given to the image memory 5, and each The image memories 3, 4 and 5 are written individually by write signal 0.

The image memories 3 and 4 respectively store luminance pixel data d,
Two systems are provided for dual mode. The image memory 5 stores only color pixel data f and cannot store any other data. Image memory 3, 4 and 5
The pixel data respectively written in are read out as luminance data g and h and color data i, respectively. The read luminance data g and h are given to the mask control section 6 and selected by the mask control signal. That is,
When displaying the image in the image memory 3 on the CRT monitor 11, only the luminance data g read out from the image memory 3 is selected.

The luminance data j selected by the mask control section 6 is given to the overlap circuit 12 together with the color data i read from the image memory 5, and each is combined. and,
The synthesized data n is given to the look-up table memory 7, and is converted into red, green, and blue color codes with shading corresponding to the synthesized data n, and is converted into CR.
To realize high-quality color graphics on a T-monitor 11.

By the way, in the image memory control unit shown in FIG. 4, the image memories 3 and 4 are fixed to store only luminance pixel data d and e, and the image memory 5 is fixed to store only color pixel data f. ing.

FIG. 5 is a block diagram showing another example of the conventional image memory control section. In the image memory control section shown in FIG. 5, the image memory 3 stores pixel data d of brightness, and the image memory 4 stores information for blinking the image displayed on the CRT monitor 11. The image memory 5 is predetermined to store interactive data p for dragging an image, and color pixel data f. Then, the write control unit 2 writes the luminance pixel data d to the image memory 3 and the interactive data p to the image memory 4 based on the pixel information a output from the DDAl, the store control signal S, and the store signal C. Write, color pixel data f is written into the image memory 5. Then, the luminance data g read from the image memory 3, the interactive data q read from the image memory 4, and the color data i read from the image memory 5 are given to the overlap circuit 12, and the respective data are combined. . The composite data r synthesized by the overlap circuit 12 is given to the lookup table memory 7. Then, in the same manner as described above with reference to FIG. 4, the lookup table memory 7 stores red and green with shading corresponding to the composite data r.

Convert to blue color code, Q,, m, D/A
to converters 8, 9 and 10. And D/A
Each of the signals is converted into an analog video signal by converters 8.9 and 10 and displayed on the CRT monitor 11.

[Problems to be Solved by the Invention] As mentioned above, the image memory control section shown in FIG.
The image memories 3 and 4 are fixedly determined in advance to store only luminance data, and the image memory 5 is set to store only color data.In the image memory control section shown in FIG. The image memory 4 is fixedly determined to store only luminance data, the image memory 4 stores only interactive data, and the image memory 5 stores only color data. Therefore, each image memory 3
．． 4 and 5, it was not possible to arbitrarily store color data or brightness data, and there was a drawback that flexibility was lacking.

Therefore, the main object of the present invention is to eliminate the need to fixedly determine the data to be stored in a plurality of image memories in advance.
It is an object of the present invention to provide a multi-processing circuit of an image memory which can arbitrarily select desired color data and image data as needed and store and read them.

[Means for Solving the Problems] The present invention provides an image memory multiplexer that controls writing and reading of data to and from a plurality of image memories provided so that at least color information and image information can be individually stored. A processing circuit that selects one of the number of stages of image memories according to color information and image information given from the outside, and writes the color information and image information to the selected image memory. readout control means for reading out color information and image information written in a plurality of image memories; 1. The color code signal output means outputs a color code signal to be displayed on a CRT display based on the read color information and image information.

[Function] The image memory multi-processing circuit according to the present invention can select any one of the image memories provided in several sets and arbitrarily write and read color information and image information, respectively. Flexibility can be provided in the use of memory.

[Embodiments of the invention] FIG. 1 is a schematic block diagram of an embodiment of the present invention.

First, the configuration will be explained with reference to FIG. In the embodiment shown in FIG. 1, the multi-write control section 20 and
Multiple image memories 31, 32...3n-1 and 3n
, an erase control section 40, and a brain control section 50, and the DDAI, overlap circuit 12, and look-up table memory 7 are constructed in the same manner as in FIGS. 4 and 5 described above.

The multi-write control unit 20 has image memories 31, 32...3
It controls which of n-1 and 3n the color data and luminance data are written to.

For this purpose, the multi-write control unit 20 is supplied with raster information A, write control signal B, store control signal C, and store signal p from DDAl. Raster information A is pixel data obtained by line segment interpolation from vector information by DDAl. The write control signal B is sent to the image memory 31, 32...3n-
The store control signal C is used to allocate the image memories 31, 32...3n-1 and 3n according to their uses, as shown in FIG. 2, which will be described later. It is something. The store signal enables write operations to the image memories 31, 32, . . . 3n-1 and 3n. Then, the multi-write control unit 20 determines the configuration of the image memories 31, 32...3n-1 and 3n based on the write control signal B and the store signal C, and the determined image Raster information A is stored in the memory.

Data is read out from the image memories 31, 32, . The plane control unit 50 controls the image memories 3i, 32...3n-1 and 3
Necessary pixel data is selected based on the plane control signal V from the pixel data read out from the pixel data n, and is applied to the overlap circuit 12.

The erase control unit 40 includes image memories 31, 32...3n.
This is to erase the pixel data written to each of -1 and 3n. For this purpose, the erase control section 40 is given information indicating pixel data to be erased via the data bus. Then, the erase control unit 40
When the TR signal is given, determines the information on the data bus,
Image memories 31, 32, 3n-1 and 3n
erase signal W.

Give x, y, z. As a result, the pixel data written in the image memory to which the erase signal has been applied is erased.

FIG. 2 is a diagram for explaining the operation of the multi-processing circuit of the image memory shown in FIG.

Next, the operation of one embodiment of the present invention will be described with reference to FIGS. 1 and 2. As described above, in this embodiment, a plurality of image memories 31, 32, . . FIG. 2 shows an example of how to use it. For example, eight image memories 31, 32...3n-1 and 3n are provided. For example, type 1 has line smoothing, brightness and color. This is a dual operation.

That is, in type 1, two image memories store brightness data iA, the next two image memories store different brightness data iB, the next two image memories store color data CA, and the last two image memories store different brightness data iB. The two image memories will store different color data CB. - If type 1 is selected in this way, the store control signal C output from DDAl is the image memory 31, 32...3n-
1 and 3n are determined to be type 1, and it is determined whether the data is iA, iA, CA, CA or iB, iB, CB, CB. For example, if the configuration is luminance data tA, iA and recolor data CA, CA, the multi-write control unit 20 considers the write control signal B, and when the store signal is given from DDAI, the image memory 3
1, brightness data E and write enable signal G are applied to image memory 32, brightness data F and write enable signal H are applied to image memory 3n-1, and color data I is applied to image memory 3n-1. and a write enable signal K, and color data J and a write enable signal are applied to the image memory 3n.

The store signal is converted into a write signal M by the multi-write control unit 20, and this write signal M is sent to the image memory 31.32.
. . 3n-1 and 3n, only the image memory to which the write enable signal is applied writes luminance and color pixel data.

Pixel data written in image memories 31.32.3n-1 and 32 is read out for display on CRT monitor 11.

Reading of pixel data from the image memories 31, 32, . . . 3n-1 and 3n is performed within the - pattern.

The read pixel data N, P, O, and Q are then given to the plane control section 50. The plane control unit 50 selects the image memories 31, 32, .

The pixel data of the image you want to display on the CRT monitor 11 is
Since this is pixel data of the image memories 31, 32.3n-1 and 3n, the plane control signal V is given to select these image memories 31, 32, 3n-1 and 3n. Based on the plane control signal V, the plane control unit 50 outputs only the pixel data N, O, P, and Q as pixel data R to the overlap circuit 12. The Opara-tube circuit 12 synthesizes the given pixel data R,
The composite data j is given to the lookup table 7.

The look-up table 7 supplies α1m to the D/A converters 8, 9, and 10 as a color code having shading corresponding to the composite data j. Then, the D/A converters 8, 9 and 10 convert the color code into an analog signal in the same manner as explained above in FIG.
Display on monitor IJ.

Note that the other types shown in FIG. 2 can be similarly realized using the store control signal C, write control signal B, and plane control signal M.

In addition, image memories 31, 32...3n-1 and 3n
can be erased for each image memory by the erase control section 40. For example, image memory 31.3
When you want to erase the pixel data written to 2.3n,
When the data representing these image memories is output to the data bus and the ERSTR signal is given to the erase control unit 40, the erase control unit 40 judges the information output to the data bus and issues an erase signal to the corresponding image memory. is given to erase the pixel data written in each image memory.

FIG. 3 is a schematic block diagram of another embodiment of the invention. In the embodiment shown in FIG. 3, interactive data for blinking or dragging images can also be stored in one of the image memories 31, 32...3n-1 and 3n. This embodiment is the same as the embodiment shown in FIG. 1 described above except that a selector circuit 60 is provided. The selector circuit 60 is connected to the image memory 31, 32...
When the interactive data is read from either of 3n-1 and 3n, the interactive data is directly given to the overlap circuit 12 without being given to the plane control section 50.

Next, the operation will be explained with reference to FIG. When color data and brightness data are stored in the image memories 31, 32, . Perform the action.

However, for example, when color data is stored in the image memory 31, brightness data is stored in the image memory 32, and interactive data is stored in the image memory 3n-1, and each data is read out, the selector circuit 60 Based on the control signal from the multi-write control unit 20, only interactive data is extracted and provided to the overlap circuit 12. However, the read color data and luminance data are not output from the selector circuit 60 but are given to the plane control section 50, and the respective data are given to the overlap circuit 12. Then, the overlap circuit 12 synthesizes the color data, luminance data, and interactive data, applies it to the lookup table memory 7, and performs the same operation as in FIG. 1 described above. Note that when writing interactive data to the image memory 3n-1, the multi-write control unit 20 writes the interactive data to the image memory 3n-1 according to the write control signal B output from the DDAI.
1 to write interactive data.

As mentioned above, in this embodiment, the image memories 31, 32
... arbitrarily select either 3n-1 or 3n,
Since not only color data and luminance data but also interactive data is written, any data can be written into and read from any image memory.

[Effects of the Invention] As described above, according to the present invention, one of a plurality of image memories is selected according to color information and image information provided from the outside, and the color information and image are stored in the selected image memory. Since information is written and each data is read after being written, the image memory can be used flexibly. For example, when the number of colors may be small but the brightness needs to be increased for brieging, the image memory for color information can be reduced and the image memory for brightness information can be increased. Conversely, if you want to use less brightness information and more color information, you can also use less image memory for brightness information and more image memory for color information. Thus, each of the plurality of image memories can be stored in correspondence with necessary information.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention. FIG. 2 is a diagram for explaining the operation of the multi-processing circuit of the image memory shown in FIG. FIG. 3 is a schematic block diagram of another embodiment of the invention. FIG. 4 is a block diagram showing an example of a conventional image memory processing circuit. FIG. 5 is a block diagram showing another example of a conventional image memory processing circuit. In the figure, 1 is a DDA, 7 is a lookup table memory, and 8. 9. 10 is a D/A converter, 11 is a C
RT monitor, 12 is an overlap circuit, 20 is a multi-write control unit, 31, 32...3n-1 and 3n are image memories, 40 is an erase control circuit, 50 is a brain control unit, and 60 is a selector circuit. . Figure 2

Claims (4)

[Claims] (1) A multi-processing circuit that controls writing and reading of data to and from an image memory having a storage area corresponding to a display area of a CRT display that displays an image, the image memory having at least color information and an image. Multiple sets are provided so that information can be stored individually, and according to color information and image information given from the outside,
writing control means for selecting one of the plurality of image memories and writing the color information and the image information into the selected image memory, respectively; a readout control means for reading out image information, and based on the color information and image information read out by the readout control means,
A multi-processing circuit for an image memory, comprising a color code signal output means for outputting a color code signal to be displayed on the CRT display. (2) The readout control means collectively reads the color information and image information written in each of the plurality of image memories, and the color code signal output means is configured to read out the color information and image information written in each of the plurality of image memories at once, and the color code signal output means is configured to read out the collectively read color information. and image information,
a selection means for selecting only necessary information; a synthesis means for synthesizing the color information and image information selected by the selection means; based on the information synthesized by the synthesis means, red color corresponding to the information; 2. A multi-processing circuit for an image memory according to claim 1, further comprising a mixing ratio converting means for converting into a mixing ratio of the three primary colors of green and blue and outputting the mixed ratio. (3) The image memory multi-processing circuit according to claim 1 or 2, wherein the image information includes brightness information. (4) The image memory multi-processing circuit according to claim 1 or 2, wherein the image information includes information for blinking the image displayed on the CRT display.