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JPS62204558A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS62204558A
JPS62204558A JP4779686A JP4779686A JPS62204558A JP S62204558 A JPS62204558 A JP S62204558A JP 4779686 A JP4779686 A JP 4779686A JP 4779686 A JP4779686 A JP 4779686A JP S62204558 A JPS62204558 A JP S62204558A
Authority
JP
Japan
Prior art keywords
copper
alloy
zinc
film
tin alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4779686A
Other languages
Japanese (ja)
Inventor
Toshihiko Shimada
島田 寿彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP4779686A priority Critical patent/JPS62204558A/en
Publication of JPS62204558A publication Critical patent/JPS62204558A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the solderability of the titled lead frame as well as to reduce the adverse effect inflicting on a semiconductor element and the like by a method wherein a copper-alloy plated film of a copper-tin alloy, copper- zinc-tin alloy, or copper-zinc alloy is formed on an external lead part. CONSTITUTION:The necessary plated film such as a precious metal plated film and the like is partially plated on a stage 2 and the external surface of the tip of an inner lead part 3, and a copper alloy plated film 7 of a copper-tin alloy, a copper-zinc-tin alloy, or a copper-zinc alloy is formed on the external surface of an external lead part 4. An oxide film is grown on the film 7 by experiencing a thermal hystereses in an assembling process, but this oxide film can be removed easily using a weak flux. The weal flux can be effectively used in the oxide film removing process which is performed as the treatment to be performed before a solder dipping operation, and the problem of lowering of reliability of the semiconductor device can be removed. Moreover, the external lead part formed as above has an excellent solderability, and also the corrosion-resisting property of the above-mentioned alloy film is also excellent.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体装置などの電子部品に用いられるリード
フレームに関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a lead frame used for electronic components such as semiconductor devices.

(従来の技術) 樹脂封止型半導体装置においては、樹脂封止後プリント
基板等とのはんだ付は性を確保する目的でリードフレー
ムの外部リード部に、錫めっき、はんだめっき、あるい
ははんだ?f ?A処理が施されて製品化される。
(Prior Art) In resin-sealed semiconductor devices, the external leads of the lead frame are tin-plated, solder-plated, or solder-plated to ensure properties when soldering to a printed circuit board, etc. after resin-sealing. f? A treatment is applied and the product is manufactured.

上記のはんだ浸漬を行う場合、樹脂封止された半導体装
置は半導体素子接合、ワイヤボンディング、樹脂封止等
の組立て工程の熱履歴により生じた外部リード部(Fe
−Ni合金、 Cu合金製など)の酸化膜を除去するた
めの強いフラックス、すなわちハロゲン価(特に塩素)
の高いフラックスによる処理が必要である。外部リード
部にニッケルめっきが施されている場合にも同様である
。このためフラックスに起因するハロゲンイオンが浸入
し、半導体素子上のアルミニウム配線回路などが損傷を
受けやすい。
When the above solder immersion is performed, the resin-sealed semiconductor device is exposed to external lead parts (Fe
- Strong flux for removing oxide films (made of Ni alloy, Cu alloy, etc.), i.e. halogen value (especially chlorine)
treatment with high flux is required. The same applies when the external lead portion is nickel plated. For this reason, halogen ions caused by the flux infiltrate, and aluminum wiring circuits on semiconductor elements are likely to be damaged.

このように樹脂封止後に外部リード部に、はんだ浸漬処
理を行うことは、半導体素子などに種々の悪影響を与え
ることから、半導体素子を固定する前、すなわち組立工
程前のリードフレームの表面処理段階で、外部リード部
にあらかじめ必要な錫あるいははんだ皮膜を形成してお
(方法が提案されている。しかしながらこの方法による
ときは、半導体装置の組立工程をこれらの皮膜が融解し
ない温度、すなわち200℃以下に抑えることが必要で
あり、組立ての信頼性低下や所要時間が長くなる等の問
題がある。さらに低温とはいえ、組立て時の熱履歴によ
り上記の錫、はんだ皮膜が変色(酸化)し、製品のはん
だ付は性が低下する問題がある。
In this way, performing solder immersion treatment on the external lead part after resin sealing has various adverse effects on the semiconductor element, so it is recommended that the surface treatment stage of the lead frame before the semiconductor element is fixed, that is, before the assembly process, be performed. A method has been proposed in which the required tin or solder film is formed on the external lead portion in advance. However, when using this method, the assembly process of the semiconductor device is carried out at a temperature at which these films do not melt, that is, 200°C. It is necessary to suppress the temperature below, which poses problems such as lower assembly reliability and longer assembly times.Furthermore, even at low temperatures, the tin and solder films mentioned above may discolor (oxidize) due to the heat history during assembly. However, there is a problem in that the soldering properties of the product deteriorate.

また、外部リード部はむき出しのため錆に対し弱く、装
置組立後の耐久性低下の原因になる。
Furthermore, since the external lead portion is exposed, it is susceptible to rust, which causes a decrease in durability after assembly of the device.

(考案が解決しようとする問題点) 本発明は半導体装置の信頼性を低下させる要因となるは
んだ浸漬を行う場合の酸化膜除去に用いる強いフラック
スを弱いフラックスで可能とし、外部リード部のはんだ
付は性および耐久性の向上にある。
(Problems to be Solved by the Invention) The present invention makes it possible to use a weak flux instead of the strong flux used to remove the oxide film during solder immersion, which is a factor that reduces the reliability of semiconductor devices, and to improve the soldering of external leads. The purpose is to improve durability and durability.

(問題点を解決するための手段) 本発明は上記の種々の問題解決にあたり、少なくとも外
部リード部にあらかじめ銅−錫合金(青銅)、銅−亜鉛
−錫合金、あるいは銅亜鉛合金の銅合金めっき皮膜を形
成させるものである。この合金皮膜は以後の組立て工程
内の熱履歴を経ることにより酸化膜を生じるが、この酸
化膜ははんだ浸?Aを行う場合に、弱いフラックスで容
易に除去することが出来る利点があり、はんだ付は性が
良く、半導体素子などに与える悪影響を極力低減するこ
とのできるリードフレームを提供するものである。
(Means for Solving the Problems) The present invention solves the above-mentioned various problems by pre-plating at least the external lead portion with copper-tin alloy (bronze), copper-zinc-tin alloy, or copper-zinc alloy. It forms a film. This alloy film forms an oxide film as it undergoes thermal history during the subsequent assembly process, but is this oxide film immersed in solder? When performing A, the lead frame has the advantage of being easily removed with a weak flux, has good soldering properties, and can minimize adverse effects on semiconductor elements and the like.

すなわち本発明の特徴は、内部リード部および外部リー
ド部を有するリードフレームにおいて、その少なくとも
外部リード部に、銅−錫合金(青銅)、銅−亜鉛−錫合
金、あるいは銅−亜鉛合金の銅合金めっき皮膜を形成し
て成るところにある。
That is, the present invention is characterized in that, in a lead frame having an inner lead portion and an outer lead portion, at least the outer lead portion is made of a copper alloy such as a copper-tin alloy (bronze), a copper-zinc-tin alloy, or a copper-zinc alloy. It is formed by forming a plating film.

(実施例) 以下本発明の好適な実施例を添付図面に基づいて詳細に
説明する。
(Embodiments) Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

第1図は樹脂封止型半導体装置に用いるリードフレーム
1を示す。
FIG. 1 shows a lead frame 1 used in a resin-sealed semiconductor device.

図において、2はステージ部であり、金、銀等の貴金属
めっきが施されており、金−シリコン共晶合金等によっ
て半導体素子が固定される部位である。
In the figure, reference numeral 2 denotes a stage portion, which is plated with a noble metal such as gold or silver, and is a portion to which a semiconductor element is fixed using a gold-silicon eutectic alloy or the like.

3は、ステージ部2を囲んで設けられた内部リード部で
あり、これの先端には同じく金、銀等の貴金属めっきが
施されており、ステージ部2に搭載された半導体素子と
ワイヤーによって接続される。
Reference numeral 3 denotes an internal lead part provided surrounding the stage part 2. The tip of this lead part is similarly plated with precious metals such as gold and silver, and is connected to the semiconductor element mounted on the stage part 2 by a wire. be done.

4は内部リード部3に続く外部リード部であり、後述す
るように、銅−錫合金(青銅)、銅−亜鉛−錫合金、あ
るいは銅−亜鉛合金めっきが施されている。
Reference numeral 4 designates an external lead portion following the internal lead portion 3, and is plated with a copper-tin alloy (bronze), a copper-zinc-tin alloy, or a copper-zinc alloy, as described later.

5はダムバーであり、樹脂の堰止めをする。5 is a dam bar, which dams the resin.

6は外枠である。6 is an outer frame.

図上破線で示すのは、樹脂モールド領域である。The area indicated by the broken line in the figure is the resin mold area.

第2図および第3図に示すものは、めっきの種類および
めっきの被着範囲を示す種々の実施例である。
What is shown in FIGS. 2 and 3 are various examples showing the type of plating and the coverage area of the plating.

第2図に示すものは、ステージ部2および内部リード部
3先端に銀めっき皮膜(あるいは金めつき皮膜)8が部
分めっきされ、また外部リード部4上に、内部リード部
3上に若干及ぶように、銅−錫合金(青銅)、銅−亜鉛
−錫合金、あるいは銅−亜鉛合金めっき皮膜7が部分め
っきされて成る。
In the case shown in FIG. 2, a silver plating film (or gold plating film) 8 is partially plated on the tips of the stage part 2 and the inner lead part 3, and also extends slightly onto the outer lead part 4 and the inner lead part 3. The plating film 7 is partially plated with a copper-tin alloy (bronze), a copper-zinc-tin alloy, or a copper-zinc alloy.

第3図に示すものは、リードフレーム2全体に亘って銅
−錫合金(青銅)、銅−亜鉛−錫合金、あるいは銅−亜
鉛合金めっき皮膜7が形成され、さらにステージ部2お
よび内部リード部3先端に、銅−錫合金(青銅)、銅−
亜鉛−錫合金、あるいは銅−亜鉛合金めっき皮膜7の上
に銀めっき皮膜あるいは金めつき皮膜8が部分めっきさ
れて成る。
In the case shown in FIG. 3, a copper-tin alloy (bronze), copper-zinc-tin alloy, or copper-zinc alloy plating film 7 is formed over the entire lead frame 2, and the stage section 2 and internal lead section 3 At the tip, copper-tin alloy (bronze), copper-
A silver plating film or a gold plating film 8 is partially plated on a zinc-tin alloy or copper-zinc alloy plating film 7.

本発明においては、要するに、ステージ部2および内部
リード部3先端の外表面に貴金属めっき皮膜等の必要な
めっき皮膜が部分めっきされ、外部リード部4外表面に
銅−錫合金、銅−亜鉛−錫合金、あるいは銅−亜鉛合金
の銅合金めっき皮膜が形成されていればよい。   ゛ しかして、銅−錫合金、銅−亜鉛−錫合金、あるいは銅
−亜鉛合金の銅合金めっき皮膜7は、組立て工程の熱履
歴を経ることにより酸化膜を生じるが、この酸化膜は弱
いフラックスで容易に除去出来るものである。
In short, in the present invention, the outer surfaces of the stage section 2 and the tips of the internal lead sections 3 are partially plated with a necessary plating film such as a precious metal plating film, and the outer surface of the external lead section 4 is plated with copper-tin alloy, copper-zinc alloy, etc. A copper alloy plating film of tin alloy or copper-zinc alloy may be formed.゛However, the copper alloy plating film 7 of copper-tin alloy, copper-zinc-tin alloy, or copper-zinc alloy produces an oxide film through the thermal history of the assembly process, but this oxide film is a weak flux. It can be easily removed.

し、たがって、従来におけるはんだ浸漬の前処理として
酸化膜除去工程に強いフラックスを用いて行っていたの
が、弱いもので充分となり、半導体装置の信頼性低下の
問題を解消しえた。
Therefore, instead of using a strong flux in the oxide film removal process as a pretreatment for solder dipping in the past, a weak flux is now sufficient, and the problem of lower reliability of semiconductor devices can be solved.

さらに、このようにして形成された外部リード部ははん
だ付は性が極めて良好であった。また、これら合金の皮
膜は耐食性の点でも優れていた。
Furthermore, the external lead portion formed in this manner had extremely good solderability. Furthermore, the coatings of these alloys were also excellent in terms of corrosion resistance.

実施例1 銅−錫合金めっき浴 シアン化宴同           35g/ 1スズ
酸すトリウム       38g/ 1シアン化ナト
リウム      54g/ 1水酸化ナトリウム  
     7.5g/βPH12,6 浴温             65℃電流密度   
        3へ/dm実施例2 銅−亜鉛−錫合金めっき浴 シアン化銅          30g/ IIシアン
化亜鉛         27g/ Itシアン化ナナ
トリウム     35g/ 1スズ酸すトリウム  
      2g/l炭酸ナトリウム        
10g/ ePH13 浴温             20°C実施例3 銅−亜鉛合金めっき浴 シアン化銅           30g/ j2シア
ン化亜鉛         log/ 1シアン化ナト
リウム      60g/ j2炭酸ナトリウム  
      30g/βアンモニア(28%)    
    3g/ IPH10,5 浴温             45℃なお、本発明は
樹脂封止型半導体装置用リードフレームに限られるもの
ではなく、半導体装置組立ての過程で熱履歴を経る他の
リードフレームにも適用し得るものである。
Example 1 Copper-tin alloy plating bath cyanide bath 35g/1storium stannate 38g/1sodium cyanide 54g/1sodium hydroxide
7.5g/βPH12,6 Bath temperature 65℃ Current density
To 3/dm Example 2 Copper-zinc-tin alloy plating bath Copper cyanide 30g/II Zinc cyanide 27g/It Sodium cyanide 35g/Storium tin oxide
2g/l sodium carbonate
10g/ePH13 Bath temperature 20°C Example 3 Copper-zinc alloy plating bath Copper cyanide 30g/j2 zinc cyanide log/1 Sodium cyanide 60g/j2 Sodium carbonate
30g/β ammonia (28%)
3g/IPH10.5 Bath temperature 45°C Note that the present invention is not limited to lead frames for resin-sealed semiconductor devices, but can also be applied to other lead frames that undergo thermal history during the process of assembling semiconductor devices. It is.

(発明の効果) 以上のように本発明に係るリードフレームによれば、外
部リード部にあらかじめ銅−錫合金(青銅)、銅−亜鉛
−錫合金、あるいは銅−亜鉛合金の銅合金めっき皮膜を
形成したから、半導体装置組立時の熱履歴を経て形成さ
れる金属酸化膜は、弱いフラックスで容易に除去するこ
とが出来た。
(Effects of the Invention) As described above, according to the lead frame of the present invention, the external lead portion is coated with a copper alloy plating film of copper-tin alloy (bronze), copper-zinc-tin alloy, or copper-zinc alloy in advance. Since the metal oxide film was formed through the thermal history during the assembly of the semiconductor device, it was possible to easily remove it with a weak flux.

また、銅−錫合金(青銅)、銅−亜鉛−錫合金、あるい
は銅−亜鉛合金めっき皮膜を形成させることにより、は
んだ付は性が著しく向上させることが出来た。さらに、
これらの皮膜は耐食性においても、リードフレーム材料
(Fe−Ni合金、銅合金など)やニッケルめっき皮膜
に比べて優れていた。
Furthermore, by forming a copper-tin alloy (bronze), copper-zinc-tin alloy, or copper-zinc alloy plating film, the soldering properties could be significantly improved. moreover,
These films were also superior in corrosion resistance to lead frame materials (Fe-Ni alloy, copper alloy, etc.) and nickel plating films.

かくして、半導体装置の信頼性を低下させることなく半
導体装置の組立てが行えるという効果を持つものである
This has the effect that the semiconductor device can be assembled without reducing the reliability of the semiconductor device.

以上本発明につき好適な実施例を挙げて種々説明したが
、本発明はこの実施例に限定されるものではなく、発明
の精神を逸脱しない範囲内で多くの改変を施し、得るの
はもちろんのことである。
Although the present invention has been variously explained above with reference to preferred embodiments, the present invention is not limited to these embodiments, and can of course be modified in many ways without departing from the spirit of the invention. That's true.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はリードフレームの説明図、第2図および第3図
はめっきの種類およびその被着範囲を示す実施例を示す
断面説明図である。 l・・・リードフレーム、 2・・・ステージ部、 3
・・・内部リード部、 4・・・外部リード部、 5・
・・ダムバー、 6・・・外枠、7・・・銅−錫合金(
青銅)めっき皮膜、(銅−亜鉛−錫合金めっき皮膜、銅
−亜鉛合金めっき皮膜) 8・・・貴金属めっき皮膜。
FIG. 1 is an explanatory diagram of a lead frame, and FIGS. 2 and 3 are cross-sectional explanatory diagrams showing an embodiment showing the types of plating and the range to which it is applied. l...Lead frame, 2...Stage section, 3
...Internal lead part, 4...External lead part, 5.
... Dam bar, 6 ... Outer frame, 7 ... Copper-tin alloy (
Bronze) plating film, (copper-zinc-tin alloy plating film, copper-zinc alloy plating film) 8...Precious metal plating film.

Claims (1)

【特許請求の範囲】 1、内部リード部および外部リード部を有するリードフ
レームにおいて、 少なくとも外部リード部に、銅−錫合金、 銅−亜鉛−錫合金、あるいは銅−阿寒合金の銅合金めっ
き皮膜を形成してなるリードフレーム。
[Claims] 1. In a lead frame having an internal lead portion and an external lead portion, at least the external lead portion is coated with a copper alloy plating film of copper-tin alloy, copper-zinc-tin alloy, or copper-Akan alloy. Lead frame made by forming.
JP4779686A 1986-03-05 1986-03-05 Lead frame Pending JPS62204558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4779686A JPS62204558A (en) 1986-03-05 1986-03-05 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4779686A JPS62204558A (en) 1986-03-05 1986-03-05 Lead frame

Publications (1)

Publication Number Publication Date
JPS62204558A true JPS62204558A (en) 1987-09-09

Family

ID=12785331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4779686A Pending JPS62204558A (en) 1986-03-05 1986-03-05 Lead frame

Country Status (1)

Country Link
JP (1) JPS62204558A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4985749A (en) * 1988-03-22 1991-01-15 Bull S.A. Substrate for very large scale integrated circuit and apparatus for selective tinning of the substrate leads
EP0831683A1 (en) * 1996-09-19 1998-03-25 Nortel Networks Corporation Assemblies of substrates and electronic components
JP2016025244A (en) * 2014-07-22 2016-02-08 Shマテリアル株式会社 Lead frame and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4985749A (en) * 1988-03-22 1991-01-15 Bull S.A. Substrate for very large scale integrated circuit and apparatus for selective tinning of the substrate leads
EP0831683A1 (en) * 1996-09-19 1998-03-25 Nortel Networks Corporation Assemblies of substrates and electronic components
JP2016025244A (en) * 2014-07-22 2016-02-08 Shマテリアル株式会社 Lead frame and method of manufacturing the same

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