JPS62203354A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62203354A JPS62203354A JP4590886A JP4590886A JPS62203354A JP S62203354 A JPS62203354 A JP S62203354A JP 4590886 A JP4590886 A JP 4590886A JP 4590886 A JP4590886 A JP 4590886A JP S62203354 A JPS62203354 A JP S62203354A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- semiconductor device
- divided
- metallized
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract description 15
- 239000000919 ceramic Substances 0.000 abstract description 34
- 239000000758 substrate Substances 0.000 abstract description 34
- 229910000679 solder Inorganic materials 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 9
- 230000004907 flux Effects 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000008646 thermal stress Effects 0.000 abstract description 4
- 229910017309 Mo—Mn Inorganic materials 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 abstract 1
- 230000035882 stress Effects 0.000 description 9
- 238000005476 soldering Methods 0.000 description 5
- 229910000831 Steel Inorganic materials 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- PCEXQRKSUSSDFT-UHFFFAOYSA-N [Mn].[Mo] Chemical compound [Mn].[Mo] PCEXQRKSUSSDFT-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000011572 manganese Substances 0.000 description 1
- WYROLENTHWJFLR-ACLDMZEESA-N queuine Chemical compound C1=2C(=O)NC(N)=NC=2NC=C1CN[C@H]1C=C[C@H](O)[C@@H]1O WYROLENTHWJFLR-ACLDMZEESA-N 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は絶縁用セラミックス基板を用いる半導体装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device using an insulating ceramic substrate.
第５図は絶縁用のセラミックス基板を用いり半導体装置
の断面構造を示すものである。図において、７はベース
板、５ａは絶縁用のセラミックス基板で、ベース板７の
上に半田付けされている。FIG. 5 shows a cross-sectional structure of a semiconductor device using an insulating ceramic substrate. In the figure, 7 is a base plate, and 5a is an insulating ceramic substrate, which is soldered onto the base plate 7.
その上部に熱拡散用鋼ブロツク板６が半田付けされてい
る。さらに、そのブロック板６の中央部にはモリブデン
板４を介してシリコンチップｌが高温半田付けされ、一
方の側にはセラミックス基板５ｂを介して電極３が半田
付けされ、他方の側には、同じくセラミックス基板５ｏ
を介して電極３が半田付けちれ、その電極３にシリコン
チップ１が半田付けされている。２はシリコンチップｌ
と電極３、およびシリコ／テンプ１同志を接合するアル
ミワイヤである。なお、上記半田付は部、すなわち半田
接合部は符号８で示しである。A heat diffusion steel block plate 6 is soldered to its upper part. Further, a silicon chip 1 is soldered at high temperature to the center of the block plate 6 via a molybdenum plate 4, an electrode 3 is soldered to one side via a ceramic substrate 5b, and the other side is Similarly ceramic substrate 5o
An electrode 3 is soldered through the electrode 3, and a silicon chip 1 is soldered to the electrode 3. 2 is silicon chip l
This is an aluminum wire that connects the electrode 3 and the silico/temp 1 to each other. Note that the soldering part, that is, the solder joint part is indicated by the reference numeral 8.
第６図は上記セラミックス板５の細部構成を示したもの
である０すなわち、ブロック板６側は、同図（ａｌに示
すように、絶縁沿面距離を取るために全面にはメタライ
ズを行なっていないＱベース板１側は、同図（ＣＩのよ
うに、全面メタライズを行なっている。メタライズ領域
９は、モリブデン−マンガンのそれで、図においては斜
線で示しである０〔発明が解決しようとする問題点〕
このような構造の半導体装置においては、セラミックス
基板５の熱膨張係数が、ベース板７と銅ブロック６のそ
れに比べて小感いために、アセンブリ工程において加熱
嘔れると、セラミックス基板５に引張応力が加わること
になる０すなわち、アセ／ブリ工程においては、セラミ
ックス基板５にベース板７と鋼ブロツク板６を半田付け
した後の工程で熱の加わる工程があるが、この工程でセ
ラミックス基板５に引張応力が加わることになる。FIG. 6 shows the detailed structure of the ceramic plate 5. In other words, the block plate 6 side is not metallized on the entire surface in order to maintain an insulating creepage distance, as shown in FIG. 6 (al). The entire surface of the Q base plate 1 side is metalized as shown in the same figure (CI).The metallized region 9 is made of molybdenum-manganese and is indicated by diagonal lines in the figure. [Point] In a semiconductor device having such a structure, the coefficient of thermal expansion of the ceramic substrate 5 is smaller than that of the base plate 7 and the copper block 6. Therefore, when heated during the assembly process, the ceramic substrate 5 undergoes tensile stress. In other words, in the assembly process, there is a process in which heat is applied after the base plate 7 and steel block plate 6 are soldered to the ceramic substrate 5. tensile stress will be applied to the
ところが、セラミックス基板５の両面は、上述のように
、全面メタライズされているので、上記引張応力の逃げ
場がなく、これがセラミックス基板５の破壊を引き起こ
すことがあった。また、セラミックス基板５の面積が大
きくなるとともに、半田付は時に生ずるフラツクスが抜
けきれず、半田巣が発生しやすかった。However, since both surfaces of the ceramic substrate 5 are completely metalized as described above, there is no place for the tensile stress to escape, which may cause the ceramic substrate 5 to break. Furthermore, as the area of the ceramic substrate 5 becomes larger, flux that sometimes occurs during soldering cannot be removed completely, and solder cavities are likely to occur.
この発明は上記のような問題点を解消するためになされ
たもので、セラミックス基板に加わる熱応力を緩和して
、セラミックス基板の破壊を防止することができるとと
もに、巣の少ない良好な半田接合部を有する半導体装置
を提供することを目的とする。This invention was made in order to solve the above-mentioned problems, and can prevent the destruction of the ceramic substrate by alleviating the thermal stress applied to the ceramic substrate, and also create a good solder joint with few cavities. An object of the present invention is to provide a semiconductor device having the following features.
この発明に係る半導体装置は、セラミックス基板の両面
に熱膨張係数の異なる金属板を半田付けしてなるす／ド
イツチ構造を持つ半導体装置において、前記セラミック
ス基板のメタライズ領域を両面とも複数の領域に分割し
たものである。A semiconductor device according to the present invention is formed by soldering metal plates having different coefficients of thermal expansion to both sides of a ceramic substrate.In a semiconductor device having a German structure, the metallized area of the ceramic substrate is divided into a plurality of areas on both sides. This is what I did.
この発明におけるセラミックス基板は、そのメタライズ
領域が両面とも複数の領域に分割されているから、アセ
ンブリ工程における加熱によって熱応力が加わっても、
これを緩和することができ、したがって、破壊するおそ
れはない。In the ceramic substrate of the present invention, the metallized region is divided into a plurality of regions on both sides, so even if thermal stress is applied due to heating during the assembly process,
This can be mitigated and therefore there is no risk of destruction.
また、上記セラミックス板は、分割されたメタライス領
域の間に非メタライズ領域が半田付は時のフラツクスの
逃げ道として機能するので、フラツクスの抜けが良くな
り、半田巣の発生が少なくなる。Furthermore, in the ceramic plate, the non-metallized areas between the divided metallized areas function as an escape route for flux during soldering, which improves flux escape and reduces the occurrence of solder cavities.
以下この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はセラミックス基板１１のモリブデ／−マンガン
のメタライズ領域を両面とも９つの領域１２に分割した
例であり、第２図はこのセラミックス基板１１を拡大し
て示したもの、すなわち、第１図（ｂｌを拡大したもの
である。図中、斜線部がメタライズ領域１２を示し、こ
の例では両面とも同じパターンで分割されているｏ１３
は各メタライズ領域１２０間の非メタライズ領域である
０半導体装置としての構成は、第５図と同じである。FIG. 1 shows an example in which the molybdenum/-manganese metallized region of a ceramic substrate 11 is divided into nine regions 12 on both sides, and FIG. 2 shows an enlarged view of this ceramic substrate 11, that is, FIG. (This is an enlarged view of bl. In the figure, the shaded area indicates the metallized area 12, and in this example, o13 is divided in the same pattern on both sides.
is a non-metallized region between each metallized region 120. The structure of the semiconductor device is the same as that shown in FIG.
次に、第３図と第４図により作用を説明する。Next, the operation will be explained with reference to FIGS. 3 and 4.
第３図は従来のセラミックス基板５を使用した第５図の
サンドイッチ構造のものがアセンブリ工程で加熱きれた
ときの変形状態を示す。すなわち、実線部が７１０熱前
の状態で破線部が加熱時の変形状態を示す。矢印は伸び
量を概念的に表わしている。FIG. 3 shows the deformed state of the sandwich structure shown in FIG. 5 using the conventional ceramic substrate 5 when it is completely heated in the assembly process. That is, the solid line section shows the state before heating to 710 degrees, and the broken line section shows the deformed state during heating. The arrow conceptually represents the amount of elongation.
これよりセラミックス基板５に引張応力が加わっている
のが理解できる０ここで半田付は部８は破線で示すよう
に変形することで、引張応力を緩和する働きをしている
と考えられるｏしかし、従来のセラミックス基板５は、
両面とも全面メタライズされているので、前述のように
、上記引張応力の逃げ場がなく、なお十分にこれを緩和
することができなかった。From this, it can be understood that tensile stress is applied to the ceramic substrate 5.Here, the soldered portion 8 is deformed as shown by the broken line, and is thought to work to relieve the tensile stress. , the conventional ceramic substrate 5 is
Since both surfaces are fully metallized, there is no place for the tensile stress to escape, as described above, and it has not been possible to sufficiently alleviate this stress.
これに対し、実施例では、メタライズ領域を９つの領域
１２に分割することで、第４図のように、半田付は部８
が小さくなるので、引張応力の緩和性が向上することが
考えられ、その結果としてセラミックス基板１１全体に
がかる引張応力が軽減される。なお、第４図は第３図と
同じ態様で示しである。On the other hand, in the embodiment, by dividing the metallized area into nine areas 12, as shown in FIG.
is reduced, it is thought that the relaxation of tensile stress is improved, and as a result, the tensile stress applied to the entire ceramic substrate 11 is reduced. Note that FIG. 4 is shown in the same manner as FIG. 3.
また、従来のセラミックス基板５の場合は、その面積が
大きくなるに従いメタライス領域９も大きくなるので、
半田付は時にフラツクスが残るｏＪ能性が大きい。しか
し、この実施例によれば、非メタライズ領域１３にフラ
ックスの逃げ道Ｉ４が形成されるので、フラックスの逃
げが良くなり、巣のない良好な半田接合部８が得られる
。In addition, in the case of the conventional ceramic substrate 5, as the area becomes larger, the metal rice region 9 also becomes larger.
Soldering has a high OJ ability, sometimes leaving flux behind. However, according to this embodiment, since the flux escape route I4 is formed in the non-metalized region 13, flux escape is improved and a good solder joint 8 without cavities can be obtained.
なお、上記実施例では、第１図のようにモリブデン−マ
ンガンのメタライズ領域を９つの領域１２に分割したが
、さらに小さくあるいは大きく任意のパターンで分割し
てもよい。また、メタライズ領域１２は直線的な非メタ
ライズ領域１３で分割嘔れているが、曲線的な非メタラ
イズ領域で分割してもよいし、非メタライズ領域の幅は
任意でおる。さらに、実施例では、メタライズ領域を両
面とも同じパターンで複数の領域１２に分割したが、両
面それぞれ異なるパターンで複数の領域に分割してもよ
い。In the above embodiment, the molybdenum-manganese metallized region is divided into nine regions 12 as shown in FIG. 1, but it may be divided into smaller or larger regions in any desired pattern. Furthermore, although the metallized region 12 is divided into linear non-metalized regions 13, it may be divided into curved non-metalized regions, and the width of the non-metalized regions can be set arbitrarily. Further, in the embodiment, the metallized area is divided into a plurality of areas 12 with the same pattern on both sides, but it may be divided into a plurality of areas with different patterns on each side.
以上のように、この発明によれば、セラミックス基板の
メタライズ領域を両面とも複数の領域に分割したから、
アセンブリ工程中にセラミックス基板に加わる熱応力を
緩和してセラミックス基板の破壊を防止することができ
るとともに、巣の少ない良好な半田接合部を有する半導
体装置を得ることができる。As described above, according to the present invention, since the metallized region of the ceramic substrate is divided into a plurality of regions on both sides,
Thermal stress applied to the ceramic substrate during the assembly process can be alleviated to prevent destruction of the ceramic substrate, and a semiconductor device having good solder joints with few cavities can be obtained.
第１図はこの発明の実施例の半導体装置におけるセラき
ツクス基板を示し、同図ｔａｌは正面図、同図（ｂｌは
側面図、同図（ｃｌは背面図、第２図は第１図ｔｂｌの
拡大図、第３図は従来の半導体装置、第４図は実施例の
半導体装置のアセンブリ工程において熱が加わったとき
の変形状態を示す断面図、第５図は従来のセラミックス
基板を用いた半導体装置の断面図、第６図は第５図にお
けるセラミックス基板を示し、同図ｔａ＋は正面図、同
図（ｂｌは側面図、同図（ｃｌは背面図である。
図中、６は鋼ブロツク板、１はベース板、８は半田接合
部、１１はセラ之ツクス基板、１２はメタライズ領域、
＋３Ｖｉ非メタライズ領域である。
なお、各図において、同符号は同一または相当部分を示
す。
何人大岩増雄
第１図
（ａ） （ｂ） （ｃ）
第２図
第３図
第４図
（ａ）
第６図
（ｂ） （ｃ）FIG. 1 shows a ceramic substrate in a semiconductor device according to an embodiment of the present invention, and tal in the same figure is a front view, BL is a side view, CL is a back view, and FIG. 3 is an enlarged view of tbl, FIG. 3 is a conventional semiconductor device, FIG. 4 is a sectional view showing the deformation state when heat is applied in the assembly process of the semiconductor device of the example, and FIG. 5 is a conventional ceramic substrate. FIG. 6 is a cross-sectional view of the semiconductor device shown in FIG. 5, showing the ceramic substrate in FIG. Steel block plate, 1 is a base plate, 8 is a solder joint, 11 is a ceramic substrate, 12 is a metallized area,
+3Vi non-metallized area. In each figure, the same reference numerals indicate the same or corresponding parts. Figure 1 (a) (b) (c) Figure 2 Figure 3 Figure 4 (a) Figure 6 (b) (c)
Claims (3)
属板を半田付けしてなるサンドイッチ構造を持つ半導体
装置において、前記セラミックス基板のメタライズ領域
を両面とも複数の領域に分割したことを特徴とする半導
体装置。(1) A semiconductor device having a sandwich structure in which metal plates having different coefficients of thermal expansion are soldered to both sides of a ceramic substrate, characterized in that the metallized area of the ceramic substrate is divided into a plurality of areas on both sides. Device.
じパターンで複数の領域に分割したことを特徴とする特
許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the metallized region of the ceramic substrate is divided into a plurality of regions with the same pattern on both surfaces.
れ異なるパターンで複数の領域に分割したことを特徴と
する特許請求の範囲第１項記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the metallized region of the ceramic substrate is divided into a plurality of regions with different patterns on each side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4590886A JPS62203354A (en) | 1986-03-03 | 1986-03-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4590886A JPS62203354A (en) | 1986-03-03 | 1986-03-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62203354A true JPS62203354A (en) | 1987-09-08 |
Family
ID=12732342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4590886A Pending JPS62203354A (en) | 1986-03-03 | 1986-03-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62203354A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01106451A (en) * | 1987-10-20 | 1989-04-24 | Hitachi Ltd | semiconductor equipment |
| JPH03276788A (en) * | 1990-03-27 | 1991-12-06 | Mitsubishi Materials Corp | Ceramic substrate for integrated circuit mounting use |
| WO1994025983A1 (en) * | 1993-04-26 | 1994-11-10 | Harris Corporation | Semiconductor chip packaging method and semiconductor chip having interdigitated gate runners with gate bonding pads |
| JP2009212367A (en) * | 2008-03-05 | 2009-09-17 | Stanley Electric Co Ltd | Semiconductor light-emitting device |
-
1986
- 1986-03-03 JP JP4590886A patent/JPS62203354A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01106451A (en) * | 1987-10-20 | 1989-04-24 | Hitachi Ltd | semiconductor equipment |
| JPH03276788A (en) * | 1990-03-27 | 1991-12-06 | Mitsubishi Materials Corp | Ceramic substrate for integrated circuit mounting use |
| WO1994025983A1 (en) * | 1993-04-26 | 1994-11-10 | Harris Corporation | Semiconductor chip packaging method and semiconductor chip having interdigitated gate runners with gate bonding pads |
| JP2009212367A (en) * | 2008-03-05 | 2009-09-17 | Stanley Electric Co Ltd | Semiconductor light-emitting device |
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