JPS62202395A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To attain write inhibition at the designation of a special address without adding a complicated circuit by providing a decoder circuit constituted so as not to output a selection signal to a specific address designation executed when a write prevention signal is inputted from a write prevention signal input terminal. CONSTITUTION:One of word lines W1-Wn is selected by the combination of address signals inputted to address input terminals A0-A1 of a decoder circuit 12 and a selection signal is outputted. A unit memory circuit string of one line connected to the selected word line is selected readably and writably and the exchange of a signal to and from a corresponding bit line is attained. An input/output circuit 3 executes read/write of data between data input/output terminals DIO1-DIOk via bit lines B1-Bm by the designation of an R/W signal. In this case, when an inhibit signal functioning as a write prevention signal is applied to an inhibit signal input terminal INH of the decoder circuit 12, all the word lines are not selected only at the specific address designation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having a mechanism for not selecting a mesori cell when a specific address is specified.

[Conventional technology]

Figure 4 shows a generally known memory circuit (in this example, R
FIG. 2 is a block diagram showing an AM circuit. In Figure 4, s
Ao to A1 are 1-input address input terminals, and W1 to Wn are word lines %BI for selecting unit memory circuit rows in each row.
~B1. l is the bit line that receives the unit memory circuit column and data of each column, R/W is the input terminal of the signal that controls the read/write mode of the RAM circuit, Dlo, ~DIOk
2 is a data input/output terminal that receives data signals between the RAM circuit and the external circuit, and 2 is a decoder circuit that generates a selection signal from one 7-dress input signal to one of the n word lines. . 111~1a□ is one line X m 9111c
The arranged unit memory circuits, 3 is an input/output circuit, which transmits signals from bit lines B, ~BIIl to data input/output terminal 0.
10. Waveform shaping and transmission to ~DIOk, data input/output terminals DIO+~DIOk.

The waveform is shaped and transmitted to the signal hit lines 81 to Bm.

[Problem that the invention seeks to solve]

When configuring a semiconductor integrated circuit device using the conventional RAM circuit as described above, it may be desired to have a configuration in which addressing is disabled only for seven specific addresses under specific conditions. In such cases, conventional RAM circuits detect a specific address in addition to detecting the specific condition, and when both of these conditions are met, a circuit is created that disables reading and writing of the entire RAM. This requires external installation, and the circuitry is generally complex and requires a large amount of chip area.

For example, when using a digital AM circuit as a general-purpose register in a microprocessor LSI, and when a certain general-purpose register is used with writing prohibited when a certain instruction comes, conventionally, that instruction and the register of that instruction are After recognizing the specified address part of A processing routine for this purpose is added to the microprocessor control program. This microprogram is usually stored in a ROM circuit called a micro ROM, which results in an increase in ROM capacity, which in turn leads to an increase in chip size and chip cost.

This invention was made to solve this problem, and it is possible to prohibit KW writing when specifying a specific 7-dress, suppress the increase in microprograms, and realize semiconductor integration that can be made smaller and lower in cost. The purpose is to obtain a circuit device.

[Failure to solve the problem]

The semiconductor integrated circuit device according to the present invention has a write-protection signal input terminal, and responds to a specific 7-dress designation performed when a write-protection signal is input from the write-protection signal input terminal. It is equipped with a decoder circuit configured so as not to output a signal.

[Effect]

In this invention, even if a specific 7-dress designation is made while the decoder circuit Kit write prevention signal is being input, the selection signal is not output.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit device of the present invention. In FIG. 1, the same reference numerals as in FIG. 4 indicate the same parts, 12 is a decoder circuit, and INH is an inhibit signal input terminal which is a write prevention signal input terminal.

Further, FIG. 2 is a diagram showing an example of the configuration of the decoder circuit 12 shown in FIG. 1. In FIG. 2, the same reference numerals as in FIG. 1 indicate the same parts, 4 is an enhancement type N-channel MO8) transistor (hereinafter simply referred to as NMO8T), and 5 is a depletion type N-channel MO8) transistor (hereinafter simply referred to as single KDMOS T). ), 6 is an inverter,
W1-W8 indicate the outputs sent to the word line W1%W after being inverted.

Next, the operation will be explained.

In the semiconductor integrated circuit device shown in FIG.
One of the word lines W1 to Wn is selected from the combination K of address signals input to the address input terminals 2 to A1, and a selection signal is output. and,
One row of unit memory circuit columns connected to the selected word line is selected to be readable and writable, and signals can be exchanged with the corresponding bit lines. The input/output circuit 3 receives the bit line from 8 to 8 according to the R/W signal designation.
- reads and writes data between the data input/output terminals DI01 to DIOk and the unit memory circuit. At this time,
Inhibit signal input terminal INHK of decoder circuit 12
When an enable/hibit signal, which is an infill prevention signal, is applied, all word lines become unselected only in the case of specific addressing.

In the decoder circuit 12 of FIG. 2, each output terminal has three
A two-branch circuit of the stage is connected to the ground terminal, resulting in a cascade of three NMOS T4s connected to the ground terminal, each connected to the power supply terminal by one DMOS T5. In this case, since the gate terminal of the DMOS T 5 is connected to its source terminal, conversely, the source and drain are in a conductive state.

In this state, when three NMOS T 4 become conductive, DMOS T 5 and three NMOS
The potential according to the resistance division ratio of the cascade-connected on-resistance of ST 4 is output (this potential is set to be sufficiently Ill L 1" potential). Otherwise, the output terminal is A 9H" potential is output through the DMOS T5.

On the other hand, a part of the address signal input from the address input/output terminals A0 to Aj is inverted via the inverter 6 and used as an address signal, and the NMOS T 4 in each stage of the two-branch circuit outputs the corresponding address signal or inverted address. Any of the signals is connected, and as a result, for each combination of 7 dress signals, only one output terminal forms a current path with the ground terminal and outputs the IT L I+ potential. .

However, since NMOS T4 is connected in series to one branch of the two-branch circuit, and its gate terminal is connected to the inhibit signal input terminal INH, when the inhibit signal is at 1H'' potential, all 7 The above operation is performed for the combination of , but when the inhibit signal is 1
In the case of the "L" potential, the outputs Wf to W8 do not become the "L" potential, and the word line W is output as a specific address by the combination of address signals.

And when selecting W8, the output W1~
W, becomes @H” level. In other words, none of the word lines are selected. Here, FIG. 3 shows @
H@level is logical value ++11'', 'L level is logical value@
A truth table is illustrated when word lines W1 to Wa corresponding to 0''K are selected.

In addition, in the above example, 1H from DMOS T 51c
Although the case where a "potential" is output has been described, a configuration using a P-channel MO8) transistor may also be used.

Furthermore, although the source of the NMOS T4 corresponding to the trunk of the two-branch circuit is connected to the ground terminal, it may be connected to the chip select signal terminal.

〔Effect of the invention〕

As explained above, this invention has a write prevention signal input terminal, and outputs a selection signal for a specific address designation performed when a write prevention signal is input from this write prevention signal input terminal. Since a decoder circuit configured to prevent this from occurring, it is possible to prohibit KiN input when specifying a specific address without adding a complicated circuit, and this has the effect of making it possible to reduce the size and cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit device of the present invention, FIG. 2 is a diagram showing an embodiment of the configuration of a decoder circuit, FIG. 3 is a truth table, and FIG. 1 is a block diagram showing a conventional memory circuit. In the figure, 1,1 to 111111 are unit memory circuits,
3 is an input/output circuit, 12 is a decoder circuit, and INH is an inhibit signal input terminal. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 INH input C hit signal input Figure 2 Figure 3 Figure 4 Procedure amendment (voluntary)

Claims (1)

[Claims] In a semiconductor integrated circuit device that includes unit memory circuits arranged in a matrix of rows and columns and a decoder circuit that outputs a selection signal in response to address specification and selects a specific row of the unit memory circuit, a write protection signal input terminal is provided. and wherein the decoder circuit is configured so as not to output a selection signal in response to a specific address designation performed when a write protection signal is input from the write protection signal input terminal. Integrated circuit device.