JPS62201860U - - Google Patents
Info
- Publication number
- JPS62201860U JPS62201860U JP8948686U JP8948686U JPS62201860U JP S62201860 U JPS62201860 U JP S62201860U JP 8948686 U JP8948686 U JP 8948686U JP 8948686 U JP8948686 U JP 8948686U JP S62201860 U JPS62201860 U JP S62201860U
- Authority
- JP
- Japan
- Prior art keywords
- program sequence
- stop
- setting means
- address range
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Executing Machine-Instructions (AREA)
- Debugging And Monitoring (AREA)
Description
第１図はこの考案によるプログラム・シーケン
ス・ストツプ装置の一実施例を示す構成図、第２
図は従来のプログラム・シーケンス・ストツプ装
置の一実施例を示す構成図である。
図において、１はストツプ・アドレス範囲設定
スイツチ、２はサブルーチン戻り番地格納レジス
タ、３はレジスタ・ステータス設定スイツチ、４
はプログラム・シーケンス・ストツプオン／オフ
スイツチ、５はプログラム・カウンタ、６は比較
回路、７はシーケンス・ストツプ制御信号発生回
路、８は一致検出回路、９はストツプ・アドレス
設定スイツチである。なお、図中同一あるいは相
当部分には同一符号を付して示してある。
Figure 1 is a block diagram showing an embodiment of the program sequence stop device according to this invention;
The figure is a block diagram showing an embodiment of a conventional program sequence stop device. In the figure, 1 is a stop address range setting switch, 2 is a subroutine return address storage register, 3 is a register status setting switch, and 4 is a register status setting switch.
1 is a program sequence stop on/off switch, 5 is a program counter, 6 is a comparison circuit, 7 is a sequence stop control signal generation circuit, 8 is a coincidence detection circuit, and 9 is a stop address setting switch. It should be noted that the same or corresponding parts in the drawings are designated by the same reference numerals.
Claims (1)
ケンスを停止させることのできるプログラム・シ
ーケンス・ストツプ装置において、プログラム・
シーケンスにおける任意のアドレス範囲を指定す
るストツプ・アドレス範囲設定手段と、任意のサ
ブルーチン戻り番地格納レジスタ状態を指定する
レジスタ・ステータス設定手段とを有し、プログ
ラム・シーケンスが前記ストツプ・アドレス範囲
設定手段で指定された範囲にあり、かつサブルー
チン戻り番地格納レジスタの内容が前記レジスタ
・ステータス設定手段の内容と一致した時に、プ
ログラム・シーケンスを停止するように制御した
ことを特徴としたプログラム・シーケンス・スト
ツプ装置。 A program sequence stop device that can stop a program sequence when certain conditions are met.
It has a stop address range setting means for specifying an arbitrary address range in the sequence, and a register status setting means for specifying the state of an arbitrary subroutine return address storage register, and the program sequence is set by the stop address range setting means. A program sequence stop device characterized in that the program sequence is controlled to be stopped when the content of the subroutine return address storage register matches the content of the register status setting means within a specified range. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8948686U JPS62201860U (en) | 1986-06-12 | 1986-06-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8948686U JPS62201860U (en) | 1986-06-12 | 1986-06-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62201860U true JPS62201860U (en) | 1987-12-23 |
Family
ID=30948510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8948686U Pending JPS62201860U (en) | 1986-06-12 | 1986-06-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62201860U (en) |
-
1986
- 1986-06-12 JP JP8948686U patent/JPS62201860U/ja active Pending
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