JPS6219726A - Color code detecting circuit - Google Patents

Abstract

PURPOSE:To shorten the time for comparing and detecting a prescribed color code by selecting any one of two data buffers by a data buffer selecting means. CONSTITUTION:An interface is formed by a direction control means for controlling a word direction data buffer and a bit direction data buffer respectively in accordance with the reading or writing operation of the contents stored in a storage device and the data buffer selecting means. In addition, a memory array 50 obtained by arranging plural memories M two-dimensionally through the interface, a signal inverting means for inverting output signals of the memories M independently and a logical operation means for executing the wire AND or wired OR of the output signals of the memories M in each bit of a data bus are also arranged. The output signal is specified so as to be inverted every picture of a picture memory, and when a color code to be detected exists, all bits of the outputted piccell is set up to '1' and a prescribed color code out color codes stored in the picture memory is rapidly detected on the basis of word access.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a color code detection circuit that detects a predetermined color code from among various color code signals stored in a storage device.

[Prior Art] In image processing, when performing boundary detection or boundary painting (an operation of painting the inside of a boundary with a predetermined color), it is necessary to detect a color code written in an image memory.

In this case, data is read from the image memory, a color code for each pixel is extracted from the data, and the extracted color code is compared with a desired color code for each pixel.

By the way, regardless of whether the image memory has a word structure or a pixel structure, in order to compare color codes, the color code is extracted for each desired pixel and compared. There is a problem that the comparative detection time of

[Object of the Invention] The present invention has been made by focusing on the above-mentioned conventional problems, and provides a color that can shorten the time to compare and detect a predetermined color code among color codes stored in an image memory. The object of the present invention is to provide a code detection circuit.

[Summary of the Invention] The present invention provides an output signal for each screen of the image memory in order to enable high-speed detection of a predetermined color code among the color codes stored in the image memory by word access. This makes it possible to instruct the inversion of the color code, so that when a color code to be detected exists, all bits of the output pixel become "1".

[Embodiment of the Invention] FIG. 2 is a block diagram showing an example of the memory M used in the present invention.

The memory M includes a row address buffer 11 that holds a row address among address information, a row address decoder 12 that decodes this, a column address buffer 13 that holds a column address among address information, and a column that decodes this address. address decoder 4
and a memory cell array 15 for storing predetermined data. The memory M also includes a word direction data buffer 20, a bit direction data buffer 30, and a memory timing controller 40.

The word direction data buffer 20 serves as an input/output interface for the memory cell array 15 in the word direction, and the bit direction data buffer 30 serves as an input/output interface for the memory cell array 15 in the bit direction. Also.

The word direction data buffer 20 and the bit direction data buffer 30 operate independently of each other.

The memory timing controller 40 generates a row address strobe signal that provides timing to take in a row address, a column address strobe signal that provides timing to take in a column address, a write enable signal that provides timing to write to the memory cell array 15, and a memory timing controller 40. It receives an output enable signal that provides timing for reading data written in the cell array 15, a data buffer selection signal, and an output inversion signal, and outputs a predetermined control signal.

The data buffer selection signal is a signal for selecting one of the word direction data buffer 20 and the bit direction data buffer 30. The output inversion signal is a signal that inverts the output data in the memory M.

FIG. 3 is a circuit diagram showing the main part of the above embodiment in more detail.

The word direction data buffer γ20 includes an input direction buffer 21 and an output direction buffer 22.

It has a buffer 23 for inverting output data. This buffer 23 inverts the - output when the output inversion signal becomes "1". The bit direction data buffer 30 has an input direction buffer 31 and an output direction buffer 32.

The memory timing controller 40 includes an inverter 41
, 42, 43, 49a and NAND circuits 43a, 44,
4.5, 46, 47.49 and ri -
The read/write timing generation circuit 48 is also provided.

Next, the operation of the above embodiment will be explained.

For example, 16-bit address information is divided into a row address and a column address, and these are sent alternately via address lines AO-7. The row address is held in the row address/buffer 11 and then decoded by the decoder 17, and the column address is held in the column address decoder 13 and then decoded by the column address decoder 14. Both of the above addresses are supplied to the memory cell array 15, and writing or reading is performed on the memory cell corresponding to the address.

By the way, data in an image memory is generally accessed in two directions. One direction is a word direction based on word-by-word processing visible from the CPU or display controller, and the other direction is a bit direction based on pixel-by-pixel processing.

Here, when it is desired to access the memory cell array 15 in the word direction, the memory timing controller 40 receives a data buffer selection signal "rl":. This prepares the conditions for the NAND circuits 44 and 45 to open. In this case, in order to write predetermined data into the memory cell array 15, the write enable signal is "0".
" and "l" as the output enable signal.

As a result, the "O" signal passed through the inverter 42 and the NAND circuit 44 turns on the buffer 21, so that word direction data is transferred to the memory cell array 15 via the buffer 21 and the write data line 16. In this case, the output of the inverter 43 becomes "O",
Since the output of the NAND circuit 45 becomes rlJ, the buffer 22 is turned off, and the data on the output data line 17 does not go out of the memory M. '□ In the above case, in order to read predetermined data from the memory cell array 15, "0" is used as the output enable signal.
” and gives “1” as the write enable signal. As a result, the inverter 43 and the AND circuit 43a
Since the signal passing through the and N A' N D circuit 45 turns on the buffer 22 , the data specified by the address at that time is transferred from the memory cell array 15 via the output data line 17 and the buffer 22 . hand,
It is output to the outside of the memory M.

Furthermore, in order to invert and output the data stored in the memory array 15, the output enable signal is set to "0".
” and set the output inversion signal to “1”.
By doing this, buffer 23 instead of buffer 22
Since the output data is output to the outside of the memory M via the inverter, the output data is inverted and output.

However, since the output inversion signal can be output only for word direction data, it becomes valid when the data buffer selection signal is "1".

Furthermore, when it is desired to access the memory cell array 15 in the bit direction, "0" is given to the memory timing controller 40 as a data buffer selection signal. This prepares the conditions for the NAND circuits 46 and 47 to open. In this case, in order to write predetermined data into the memory cell array 15, the write enable signal is "O".
is given, and "1" is given as the output enable signal.

As a result, the signal that has passed through the inverter 42 and the NAND circuit 46 turns on the buffer 31, so that bit direction data is directed to the memory cell array 15 via the buffer 31 and the write data line 16. In this case, the output of the inverter 43 becomes rOJ, and the NAND
Since the output of the circuit 47 becomes "1", the buffer 32 is turned off and the data on the output data line 17 does not go out of the memory M.

In the above case, in order to read predetermined data from the memory cell array 15, the output enable signal is set to “0”.
” is given, and “1” is given as the write enable signal. As a result, the signal passing through the inverter 43 and the NAND circuit 47 turns on the buffer 32, so that the data specified by the address at that time is transferred from the memory cell array 15 to the output data line 17 and the buffer 32. It is output to the outside of the memory M via.

FIG. 1 is a block diagram showing an entire embodiment of the present invention.

The memory array 50 is a two-dimensional array of memories M shown in FIG. In the memory array 50, a horizontal combination of memories M constitutes a word. A vertical combination of memories M constitutes one pixel (one display dot).

Further, the word direction data terminals of the memories M arranged in the same word direction are connected to each other, and this is connected to the data line 51 extending in the vertical direction. Further, the pixel direction data terminals of the memories M arranged in the same pixel direction are connected to each other, and this is connected to the data line 52 extending in the horizontal direction.

Further, the data lines 51 and 52 are connected to each other. In this case, the same bits of the data lines 51 and 52 are connected. As a result, the data line 51
and 52 become the same data bus 53. in this way,
The data bus 53 can be shared because the vertical data line 51 and the horizontal data line 52 are never used at the same time.

Further, a read plane mask register 63 and a read plane gate 64 are provided as word direction read prohibition masking means for prohibiting reading of a predetermined memory M existing in the word direction in the memory array 50. .

Further, among a plurality of memories M arranged in the same horizontal direction, the output enable signal terminals of each memory M are connected to each other, and this connection point is connected to the output terminal of the read plane gate 64. .

Further, a light plane mask register 65 and a light plane gate 66 are provided as word direction write prohibition mask means for masking write prohibition for a predetermined memory M existing in the word direction in the memory array 50.

Also, between multiple memories M arranged in the same horizontal direction,
The write enable signal terminals of each memory M are connected to each other, and this connection point is connected to the output terminal of the light plane gate 66.

An invert plane mask register 67 is provided that instructs to invert the output signal on a predetermined plane in the memory array 50. Also, among multiple memories M arranged in the same horizontal direction.

The output inverted signal terminals of each memory M are connected to each other, and this connection point is connected to the output terminal of the inverted plane mask register 67.

A column address strobe gate 61 and a bit mask register 62 are provided as bit direction prohibition masking means for prohibiting reading or writing of the predetermined memory existing in the bit direction in the memory array.

Then, among the plurality of memories M arranged in the same vertical direction, the column address strobe terminals of each memory M are connected to each other, and this connection point is connected to the column address strobe terminal).
It is connected to the corresponding connection terminal of 61.

Memory controller (or video processor) 70
Output from AO~7. The row address strobe signal and data buffer selection signal are commonly supplied to all memories M in the memory array 50.

Read plane mask register 63. The light plane mask register 65 holds mask information for each plane in the memory array 50 according to instructions from the CPU 80 or the memory controller 70.

The bit mask register 62 controls the memory array 50 according to instructions from the CPU 80 or the memory controller 70.
It holds mask information for each pixel. The output of this bit mask register 62 is supplied to the output enable/write enable gate 61, and is ANDed with the column address strobe signal from the memory controller 70 to become a column address strobe signal for each pixel in the memory array 5°0. It is.

The invert plane mask register 67 is
Alternatively, in response to an instruction from the memory controller 70, inversion instruction information for a predetermined screen in the memory array 50 is held.

Next, the operation of the above embodiment will be explained.

First, a case where the CPU 80 performs word-direction access will be described.

In this case, set the data buffer selection signal to "1"! Select word-direction access by

Set mask data in the light plane mask register 65 according to the color to be written/surface to be used, and set the bit mask register 62 to all rlJ.After this, when memory access is executed, AO to 7, A row address strobe signal, a column address strobe signal, a write enable signal, a top enable signal, and an output inversion signal are output from the memory controller 70 at predetermined timings.

When the CPU 80 performs writing, write data is output from the CPU 80 and written in the word direction/horizontal direction via the data bus 53 and data line 51 in parallel with the operation of the memory controller 70. In this case, each authorized side is written with the same write data. That is, when writing in the word direction, at least one bit of the double-domain mask register 65 is set to "1".
Two or more bits may be set to "1" at the same time, and the same write data is written to the bits set to "1" at the same time.

If any data is set in the bit mask register 62 before the above writing, any bit in the word,
It is possible to write only to any part.

When reading in the word direction, set the read pre to one bit of the mask register 63 to "l".
If so, the read data in the word direction corresponding to the bit set to “1” is transferred to the data bus 5 via the data line 51.
Obtained in 3.

Since the plane mask register 65 for reading data and the plane mask register 63 for reading data are provided separately, it is possible to write to another plane immediately after reading one plane. Processing becomes faster when the plane and the plane to be written are different.

Next, a case where the CPU 80 performs access in the bit direction (pixel direction) will be described.

First, bit direction access is selected by setting the data buffer selection signal to "0". Then, the read plane mask register 63 and the write plane mask register 65 are all set to "L", one bit of the bit mask register 62 is set, and reading or writing is performed via the data line 52 and the data bus 53. In this case, the value of AO to 7 is determined corresponding to the word address where the pixel to be accessed exists, and the value of the bit mask register 62 is determined corresponding to the bit position within that word.

Pixel data, no matter what the pixel length is,
Can be accessed at right-justified bit positions within the data bus.

Therefore, the processing by the CPU 80 is a very simple operation.

In the above embodiment, multiple fields can be accessed simultaneously in the same time as the word access time in a conventional storage device with a word configuration, and pixel access can be performed faster than the pixel access time in a conventional storage device with a pixel configuration. can be done.

Next, a case in which one-color codes are compared will be described.

First, part of the contents of the memory array 50 is shown in FIG. 4(A).
Assume that the situation is as shown in . In this situation, we want to detect a predetermined color code, for example rl Ol 14. This code rlo11J is shown in Figure 4 (A).
This is indicated by the thick line. That is, in FIG. 4(A), signal rl_O11J is present at bit 4 and bit O.

In this case, the complement of the color code signal (a signal obtained by inverting the color code signal) is ro1'oOJ, and this is set in the invert plane mask register 67. The state set in this way is shown in FIG. 4 CB). In other words, all the beams corresponding to plane 3.1.0
l· is "0", and only the bit corresponding to plane 2 is set to "1". Then, only the signal of plane 2 set to "1" is output inverted.

The output inverted signal of the memory M corresponding to the plane set to the output and rlJ becomes "1", while the output enable signal is rQJ, and this rQJ becomes "1" via the inverter 43, Since the data buffer selection signal is rlJ, the AND circuit 43a outputs "1". Then, with the output inverted signal "1",
NAND circuit 49a outputs "0". For this,
Data buffer 23 inverts the output signal.

The output contents for each side of the memory array 50 after output inversion in the above example are shown in FIG. 4(C). In FIG. 4(C), the inverted output signal is shown by a thick line.

In this state, the output of the memory array 50 is wired ANDed with the vertical data line 51, resulting in an 8-bit signal shown in FIG. 4(D). This result appears on data bus 53 as a word output.

Therefore, at a given bit, if even one output corresponding to each plane is "0", the output corresponding to that bit becomes "0", and at a given focus, all outputs corresponding to each plane are rlJ. In some cases, the output corresponding to that bit is rlJ. Therefore, only when the color codes in the pixel direction match, the word output corresponding to the matched bit becomes "l".

Since the output inversion and wired AND are executed in the memory read cycle, the color code can be detected at high speed.

Next, the operation of detecting the presence of a one-color code will be explained.

First, it is assumed that part of the contents of the memory array 50 is in the state shown in FIG. 5 (A). In this state, the presence of any color code is detected.

In FIG. 5(A), color codes exist in bit 4, bit 2, and bit 1, respectively.

In this case, the invert plane mask register 67 is set to invert the output for all planes. That is, rl l 11J is set in the invert plane mask register 67.

The state set in this way is shown in FIG. 5 CB).

The output contents for each side of the memory array 50 after output inversion in the above example are shown in FIG. 5(C).

In this state, the output of the memory array 50 is wired ANDed with the data line 51 in the vertical direction, so that as a result, the eight-hit signal shown in FIG. 5(D) is obtained. This result is output as a word.

Appears on data bus 53.

Therefore, in a given bit, if even one output corresponding to each plane has rQJ, the output corresponding to that bit becomes "O", and in a given bit, all outputs corresponding to each plane become "1". When - the output according to that bit becomes rlJ. For this reason, when any color code exists, the word output corresponding to the existing bit becomes "O". However, in the above example, even if the code ro OOOJ exists, only one color code think that it does not exist.

And, because the above output inversion and wired AND are executed in the memory read cycle.

The presence of a color code can be detected at high speed.

In the above embodiment, the number of planes was four, but
The number of planes may be any number greater than or equal to 2, and
One word may be set to any number of bits. Note that in the memory array 50, the number of bits in the word direction may be greater or less than the number of bits in the bit direction.

[Effects of the Invention] In the present invention, the time for comparing predetermined color codes among the color codes stored in the image memory can be shortened, and the time for detecting the presence of one color code can be shortened. has.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing an example of a memory used in the above embodiment. FIG. 3 is a circuit diagram showing a specific example of the main parts of the memory. FIG. 4 is a diagram illustrating the color code comparison operation in the above embodiment. FIG. 5 is a diagram illustrating the operation of detecting the presence of a color code in the above embodiment. M...Memory. 15...Memory cell array, 20...Data buffer for word direction, 30...Data buffer for bit direction, 40...Memory timing controller, 50...Memory array, 63...Read plane mask Register, 64...
Read plane gate, 65... Light plane mask register. 66...Light plane gate, 67...Invert plane mask register. Figure 2・M ″−＋＋＋−＋−＋＋−−−＋−−−−−1−−−−−
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3 2 1 0 Pit → Procedural Amendment October 1, 1985 Commissioner of the Patent Office Black 1) Mr. Yu Akira, Incident Indication 1985 Patent Application No. 158,592 2) Title of Invention Color Code Detection Circuit 3. Representative of the person making the amendment: Gunji Akira, Department 4, Agent 5, Date of amendment order: Voluntary amendment 7, Subject of amendment 8, Contents of amendment (1) Page 23, line 3 and line 4 of the specification Add the following content between. ``In the above embodiment, a wired ANDL is performed on the data line 51, but instead of this wired AND, other logical operation means may be used. In other words, a wired OR is performed instead of the wired AND. (2) Amend the claims as shown in the attached sheet. 2) Claims (1) In an interface for a storage device that reads or writes data via a data line; a word-oriented data buffer that is a word-oriented input/output interface; and a bit-oriented input/output interface; Furthermore, a bit-direction data buffer that operates independently of the word-direction data buffer, a data buffer selection means for selecting one of the two data buffers, and an operation for reading or writing the storage contents of the storage device. a direction control means for controlling the direction of each of the two data buffers according to the relay; and a signal inverting means for independently inverting the direction of each of the two data buffers; An interface characterized by having: a logical operation means for eared AND or wired OR; (2) In claim 1. Each of the memory arrays is characterized in that word-direction input/output signal lines in the memory array and bit-direction input/output signal lines in the memory array are connected one-to-one in a corresponding order. interface. (3) The interface according to claim 1, wherein the number of bits in the word direction and the number of bits in the bit direction are different. interface. An interface featuring: construction signal inversion means; and;

Claims (3)

[Claims] (1) In a storage device that reads or writes data via a data line; a word-direction data buffer that is a word-direction input/output interface; and a bit-direction input/output interface that is a word-direction data buffer; a bit-direction data buffer that operates independently; a data buffer selection means that selects one of the two data buffers; a memory array comprising a plurality of two-dimensional memories each having a direction control means for controlling each direction; a signal inversion means for inverting a color code signal to be detected for each screen of the image memory; A color code detection circuit comprising: AND means for wired ANDing the output signal of the image memory and the inverted color code signal for each pixel. (2) In claim 1, each of the memory arrays has one input/output signal line in the word direction in the memory array and one input/output signal line in the bit direction in the memory array in a corresponding order. A color code detection circuit characterized by being connected in a pair-to-one manner. (3) The color code detection circuit according to claim 1, wherein the number of bits in the word direction and the number of bits in the bit direction are different.