JPS62196874A - Semiconductor light emitting element and manufacture thereof - Google Patents
Semiconductor light emitting element and manufacture thereofInfo
- Publication number
- JPS62196874A JPS62196874A JP61038232A JP3823286A JPS62196874A JP S62196874 A JPS62196874 A JP S62196874A JP 61038232 A JP61038232 A JP 61038232A JP 3823286 A JP3823286 A JP 3823286A JP S62196874 A JPS62196874 A JP S62196874A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- impurity
- barrier layer
- substrate
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 30
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 12
- 125000005842 heteroatom Chemical group 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 8
- 238000005253 cladding Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Landscapes
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は1例えば0.8μm帯光通信用発光素子やカメ
ラのオートフォーカス用光源等1こ用いられる高出力な
半導体発光素子およびその鯛造方法に関するものである
。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a high-output semiconductor light emitting device used in, for example, a light emitting device for 0.8 μm band optical communication and a light source for autofocus of a camera, and its construction. It is about the method.
狭い指向性を要求され、かつ高出力光源として使用され
る半導体発光素子として第2図に示すようなものがある
。There is a semiconductor light emitting device shown in FIG. 2 that requires narrow directivity and is used as a high output light source.
これは、その中央付近に選択拡散により形成される:a
’!!!領域(p型電流狭窄領域)3を有するn型電流
障壁層2がp型GaAs基板l上に形成され。It is formed near its center by selective diffusion: a
'! ! ! An n-type current barrier layer 2 having a region (p-type current confinement region) 3 is formed on a p-type GaAs substrate l.
かつこの電障壁層2と通電領域3上にGaAjAsダブ
ルヘテロ接合層4が形成されたものである。Moreover, a GaAjAs double heterojunction layer 4 is formed on the electrical barrier layer 2 and the current-carrying region 3.
なお、このダブルヘテロ接合層4は下から順にp型Aj
GaAsクラッド4a、p型AA)aAs層4b、n型
AJGaAsクラッド層4Cの3層を有するものである
。Note that this double heterojunction layer 4 has p-type Aj in order from the bottom.
It has three layers: a GaAs cladding 4a, a p-type AA) aAs layer 4b, and an n-type AJGaAs cladding layer 4C.
そして基板1の底面にはp側オーミック電極5aが形成
されn型A幻aAs /il 4cの上面周辺部にはn
側オーミック電流5bが形成されている。A p-side ohmic electrode 5a is formed on the bottom surface of the substrate 1, and an n-type ohmic electrode 5a is formed on the periphery of the top surface of the n-type A phantom aAs/il 4c.
A side ohmic current 5b is formed.
以上のような発光素子によると、p側電極5aに正の電
圧をn側電極5bに負の電圧を夫々印加することにより
、前述の通電領域3により集束された電流がダブルヘテ
ロ接合層4iこ印加され、狭い指向性の高出力な発光が
得られる。According to the light emitting device as described above, by applying a positive voltage to the p-side electrode 5a and a negative voltage to the n-side electrode 5b, the current focused by the aforementioned current-carrying region 3 is transferred to the double heterojunction layer 4i. high output light with narrow directivity is obtained.
上述のような従来の発光素子の製造工程において、p型
GaAs基板1には不純物Znが、約10”cm−3−
”程度のキャリア濃度でドープされる。In the manufacturing process of the conventional light emitting device as described above, impurity Zn is added to the p-type GaAs substrate 1 at a depth of approximately 10"cm-3-
It is doped with a carrier concentration of about
そして、この基板1上のn型電流障壁層2への。Then, to the n-type current barrier layer 2 on this substrate 1.
選択拡散による通電領域3形成時ζこ、上述の基板1内
の不純物Znがn型障壁層2内へしみ出していく。この
ためn型障壁層2がp型化し消失してしまい、電流狭窄
作用(を流収束作用)が得られない素子(不良品)が製
造されるという問題がある。When the conductive region 3 is formed by selective diffusion, the above-mentioned impurity Zn in the substrate 1 seeps into the n-type barrier layer 2. For this reason, the n-type barrier layer 2 becomes p-type and disappears, resulting in the production of devices (defective products) in which the current confinement effect cannot be obtained.
また、このn型障壁層2が完全に消失しないにしても、
この障壁層2が所望の厚さによりも薄い素子が製造され
る。そしてこのような素子は、動作時iこ急激に特性が
劣化してしまう。Furthermore, even if this n-type barrier layer 2 does not completely disappear,
A device is produced in which this barrier layer 2 is thinner than the desired thickness. The characteristics of such an element deteriorate rapidly during operation.
これは、障壁層2が薄いために、この障壁層2のある部
分でリーク電流が生じることによると考えられる。This is considered to be due to the fact that the barrier layer 2 is thin and a leakage current occurs in a certain portion of the barrier layer 2.
例えば印加電流300mA、 1/2 duty ノ条
件で5時間通電した際この特性劣化の発生した素子は3
oa/。For example, when the current was applied for 5 hours under the conditions of 300 mA and 1/2 duty, the number of elements with this characteristic deterioration was 3.
oa/.
にも達した。It also reached
このような問題の解決策として、障壁層2をあらかじめ
厚く形成しておくということが考えられるが、この場合
、p型電流狭窄層3の形成に際しZn選択拡散の条件を
も強しなければならず、従って基板1からのZnのしみ
出しも増加してしまい根本的な解決策にはならない。One possible solution to this problem is to form the barrier layer 2 thick in advance, but in this case, the conditions for selective Zn diffusion must also be strengthened when forming the p-type current confinement layer 3. Therefore, the seepage of Zn from the substrate 1 also increases, and this is not a fundamental solution.
本発明においては上記従来の問題点を解決するために、
p型基板からの不純物Znのしみ出しが電流障壁層へ到
達できないようなp型のバッファ層を基板と障壁層の間
へ設け、かっこのバッファ層の不純物はp型基板の不純
物よりも拡散係数の小さいものを使用し、このバッファ
層からの不純物のしみ出しをも制御するものである。In the present invention, in order to solve the above conventional problems,
A p-type buffer layer is provided between the substrate and the barrier layer so that the impurity Zn seeping out from the p-type substrate cannot reach the current barrier layer, and the impurities in the parenthetical buffer layer have a higher diffusion coefficient than the impurities in the p-type substrate. This also controls impurity seepage from this buffer layer.
本発明によると、基板と電流障壁層との間に基板の不純
物よりも拡散係数の小さい不純物のドープされたバッフ
ァ層を形成するために、基板からの不純物のしみ出しを
このバッファ層が吸収し。According to the present invention, in order to form a buffer layer doped with an impurity having a lower diffusion coefficient than the impurity of the substrate between the substrate and the current barrier layer, this buffer layer absorbs impurity seepage from the substrate. .
従ってこの不純物のしみ出しによる電流障壁層への悪影
響を回避できる。Therefore, adverse effects on the current barrier layer due to seepage of impurities can be avoided.
本発明の一実施例を第1図を用いて説明する。 An embodiment of the present invention will be described with reference to FIG.
まず最初に製造工程について説明する。First, the manufacturing process will be explained.
(1)不純物Zn(第1の不純物)のドープされたp型
GaAs基板1上にLPE法(液相エピタキシャル法)
により、不純物Ge (第2の不純物)のドープされた
p型GaAsバッファ層6を10μm程度の厚さ1こ形
成する。なおこのGeのキャリア濃度(ドープ量)は、
この素子の動作時(通電時)。(1) LPE method (liquid phase epitaxial method) on p-type GaAs substrate 1 doped with impurity Zn (first impurity)
As a result, a p-type GaAs buffer layer 6 doped with impurity Ge (second impurity) is formed to a thickness of about 10 μm. The carrier concentration (doping amount) of this Ge is
When this element is in operation (when energized).
電圧降下を小さくするために高い程いいが、高濃度すぎ
ると結晶性が悪化する。よって本実施例ζこ詔いては約
2xlO”cm−’i度番こ設定した。The higher the concentration, the better in order to reduce the voltage drop, but if the concentration is too high, crystallinity will deteriorate. Therefore, in this embodiment, the angle was set to about 2xlO"cm-'i degrees.
(2)次に連続してLPE法により、バッファ層6にT
eのドープされたn型GaAs電流障壁層2を5μm種
度の厚さに形成する。(2) Next, continuously apply T to the buffer layer 6 by LPE method.
A doped n-type GaAs current barrier layer 2 is formed to a thickness of 5 μm.
(3)次に、この電流障壁層2に不純物Znの選択拡散
を行なうことによりp型通電領域(電流狭窄領域)3を
形成する。この選択拡散は。(3) Next, a p-type conductive region (current confinement region) 3 is formed by selectively diffusing impurity Zn into this current barrier layer 2. This selective diffusion.
SiN膜(図示せず)を電流障壁層2上に形成し写真蝕
刻法によりSiN膜の中央付近に60〜120μφの開
孔を形成し、このSiN膜のパターンをiスフとしてZ
nを拡散することにより行なわれる。A SiN film (not shown) is formed on the current barrier layer 2, and an opening of 60 to 120 μΦ is formed near the center of the SiN film by photolithography.
This is done by diffusing n.
(4) SiN膜のパターンを除去した後、電流障壁
層2および電流狭窄領域3上にLPB法によりGaAl
Asダブルヘテロ接合層4.すなわち下から順にp型”
o、pt、A’o、st Asクラッド4a、p型Ga
o、@。(4) After removing the SiN film pattern, GaAl is deposited on the current barrier layer 2 and current confinement region 3 by LPB method.
As double heterojunction layer 4. In other words, from the bottom, the p-type
o, pt, A'o, st As clad 4a, p-type Ga
o,@.
AJ、。、 As活性層4b 、 n 型Ga0..
AL(1,3Asクラッド層4Cの3層を形成する。A.J. , As active layer 4b, n-type Ga0. ..
Three layers of AL (1,3As cladding layer 4C) are formed.
(5) 続いてp型GaAs基板1の底面にAuBe
(金ベリリウム)合金の電極(第1オー之ツク電極)
を形成し、n型クラッド層4Cの上面にAuGe (金
ゲルマニウム)合金の電極(第2オーZツク電極)を形
成する。そしてn型クラッド層4C上のAuGe電極の
、前述した電流狭窄領域3の上部に位置する部分は光取
り出し用の開孔が約150μmφの大きさに形成される
。(5) Next, AuBe is deposited on the bottom surface of the p-type GaAs substrate 1.
(gold beryllium) alloy electrode (first open electrode)
An AuGe (gold germanium) alloy electrode (second Au Z electrode) is formed on the upper surface of the n-type cladding layer 4C. Then, in the portion of the AuGe electrode on the n-type cladding layer 4C located above the aforementioned current confinement region 3, an opening for light extraction is formed with a size of about 150 μmφ.
以上の工程により形成された発光素子は600μm角程
度にダイシングされ、 AuGe電極の開孔には大きさ
300μφ前後の透明なガラス球レンズが配設され、透
明樹脂でこの素子上に固着される。The light emitting element formed by the above steps is diced into approximately 600 μm square pieces, and a transparent glass ball lens with a size of approximately 300 μΦ is placed in the opening of the AuGe electrode, and is fixed onto this element with a transparent resin.
このような工程により製造された発光素子は。A light emitting device manufactured by such a process.
基板1からの不純物Znのしみ出しが電流#壁層2まで
到達せずまたバッファNJ6からのしみ出しは非常1こ
少なく、従りて所望の電流障壁層2が確実に形成できる
。実際に製品歩留り(良品収率)はほぼ100 ”Aと
なった。The seepage of impurity Zn from the substrate 1 does not reach the current #wall layer 2, and the seepage from the buffer NJ6 is extremely small, so that the desired current barrier layer 2 can be reliably formed. In fact, the product yield (yield of non-defective products) was approximately 100''A.
そしてこの素子の実使用に当りては、第1オーミツク電
極5aに正の電圧を、第2オーミツク電極Iこ負の電圧
を印加することにより、狭窄領域3により集束された電
流がダブルヘテロ接合層4に印加され高出力な発光が得
られるわけであるが、素子の信頼性試験(印加電流30
0mA、 1/2 dutyの条件で5時間通電)を行
なったところ、光出力の劣化する素子はほとんど無くな
った。In actual use of this device, by applying a positive voltage to the first ohmic electrode 5a and a negative voltage to the second ohmic electrode I, the current focused by the constriction region 3 is transferred to the double heterojunction layer. 4, high-output light emission can be obtained, but the device reliability test (applied current 30
When electricity was applied for 5 hours under the conditions of 0 mA and 1/2 duty, there were almost no elements whose optical output deteriorated.
よって信頼性の高い素子が確実に得られる。Therefore, a highly reliable element can be reliably obtained.
またバッファ層6を形成するための素子性能の劣化はほ
とんど見られず、狭い指向性の高出力な発光が得られる
。In addition, there is almost no deterioration in device performance due to the formation of the buffer layer 6, and high output light emission with narrow directivity can be obtained.
本発明によると、基板からの不純物のしみ出しをバッフ
ァ層により吸収することで、電流障壁層を所望の厚さで
確実に得ることができ、従って製品歩留りが極めて向上
する。また素子自体の信頼性も向上し、特性劣化はほと
んど発生しない。According to the present invention, by absorbing impurity seepage from the substrate by the buffer layer, it is possible to reliably obtain a current barrier layer with a desired thickness, thereby significantly improving product yield. Furthermore, the reliability of the element itself is improved, and characteristic deterioration hardly occurs.
という効果がある。There is an effect.
第1図は本発明の一実施例の発光素子断面図。
第2図は従来の発光素子断面図である。
1・・・p型GaAs系基板
2・・・n型電流障壁層
3・・・p型電流狭窄領域
4・・・AJaAsダブルヘテロ接合層5a、5b・・
・オーミック電極
6・・・バッファ層
第1図
第2図FIG. 1 is a sectional view of a light emitting device according to an embodiment of the present invention. FIG. 2 is a sectional view of a conventional light emitting device. 1... P-type GaAs-based substrate 2... N-type current barrier layer 3... P-type current confinement region 4... AJaAs double heterojunction layer 5a, 5b...
・Ohmic electrode 6...buffer layer Figure 1 Figure 2
Claims (5)
系基板上に、前記第1の不純物よりも拡散係数の小さい
第2の不純物がドープされた第1導電型バッファ層を形
成する工程と、このバッファ層上に第2導電型の電流障
壁層を形成する工程と、この電流障壁層に選択拡散によ
り第1導電型の電流狭窄領域を形成する工程と、この電
流狭窄領域および前記電流障壁層上にGaAlAsダブ
ルヘテロ接合層を形成する工程と、前記基板の底面に第
1のオーミック電極を形成し、前記ダブルヘテロ接合層
の上面に第2のオーミツク電極を形成する工程とを有す
ることを特徴とする半導体発光素子の製造方法。(1) First conductivity type GaAs doped with first impurity
forming a first conductivity type buffer layer doped with a second impurity having a smaller diffusion coefficient than the first impurity on the system substrate; and forming a second conductivity type current barrier layer on the buffer layer. forming a current confinement region of the first conductivity type in the current barrier layer by selective diffusion; forming a GaAlAs double heterojunction layer on the current confinement region and the current barrier layer; A method for manufacturing a semiconductor light emitting device, comprising the steps of forming a first ohmic electrode on the bottom surface of the substrate and forming a second ohmic electrode on the top surface of the double heterojunction layer.
物がGeであることを特徴とする特許請求の範囲第(1
)項記載の半導体発光素子の製造方法。(2) Claim 1, characterized in that the first impurity is Zn and the second impurity is Ge.
) The method for manufacturing a semiconductor light emitting device according to item 1.
約5μmの膜厚に夫々形成することを特徴とする特許請
求の範囲第(1)項記載の半導体発光素子の製造方法。(3) The method for manufacturing a semiconductor light emitting device according to claim (1), wherein the buffer layer is formed to have a thickness of approximately 10 μm, and the current barrier layer is formed to have a thickness of approximately 5 μm.
^3の濃度で前記バッファ層にドープされることを特徴
とする特許請求の範囲第(1)項記載の半導体発光素子
の製造方法。(4) The second impurity is approximately 2×10^1^8cm^-
3. The method of manufacturing a semiconductor light emitting device according to claim 1, wherein the buffer layer is doped with a concentration of ^3.
基板の不純物より拡散係数の小さい不純物を含み、この
基板の一主面に形成される第1導電型のバッファ層と、
このバッファ層上に形成される第2の導電型を有する電
流障壁層と、この障壁層中に形成される電流狭窄領域と
、この電流狭窄領域および前記電流障壁層上に形成され
るGaAlAsダブルヘテロ接合層と、前記基板の他主
面に形成された第1の電極と、前記ダブルヘテロ接合層
上に形成された第2の電極とを有することを特徴とする
半導体発光素子。(5) a GaAs-based substrate having a first conductivity type; a buffer layer of the first conductivity type formed on one principal surface of the substrate;
A current barrier layer having a second conductivity type formed on this buffer layer, a current confinement region formed in this barrier layer, and a GaAlAs double hetero layer formed on this current confinement region and the current barrier layer. A semiconductor light emitting device comprising a bonding layer, a first electrode formed on the other main surface of the substrate, and a second electrode formed on the double heterojunction layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61038232A JPS62196874A (en) | 1986-02-25 | 1986-02-25 | Semiconductor light emitting element and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61038232A JPS62196874A (en) | 1986-02-25 | 1986-02-25 | Semiconductor light emitting element and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62196874A true JPS62196874A (en) | 1987-08-31 |
Family
ID=12519554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61038232A Pending JPS62196874A (en) | 1986-02-25 | 1986-02-25 | Semiconductor light emitting element and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62196874A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5073806A (en) * | 1989-10-17 | 1991-12-17 | Kabushiki Kaisha Toshiba | Semiconductor light emitting element with grooves |
-
1986
- 1986-02-25 JP JP61038232A patent/JPS62196874A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5073806A (en) * | 1989-10-17 | 1991-12-17 | Kabushiki Kaisha Toshiba | Semiconductor light emitting element with grooves |
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