JPS62194650A - Semiconductor device - Google Patents

Abstract

PURPOSE:To remove the deformation of an external electrode with the hysteresis of pressure welding by mounting a first support plate having a thermal expansion coefficieint larger than that of a semiconductor substrate and a second support plate having a thermal expansion coefficient smaller than that of the first support plate and larger than that of the semiconductor substrate and each brazing both the semiconductor substrate and the first support plate and both the first support plate and the second support plate by solder material layers. CONSTITUTION:A support plate is divided into two layers, and consists of a first support plate directly braced to a semiconductor substrate and a second support plate braced to the first support plate. Both the first and second support plates have thermal expansion coefficients larger than the semiconductor substrate, but the thermal expansion coefficient of the first support plate is set at a value larger than the second support plate, and a bimetal effect generated by the difference of the thermal expansion coefficients of the first support plate and the second support plate s cancelled by a bimetal effect generated by the difference of the thermal expansion coefficients of the first support plate and the semiconductor substrate. Accordingly, the warpage of a semiconductor device after brazing is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a semiconductor device, and particularly to a substrate support structure for a large-capacity semiconductor device.

[Conventional technology]

FIG. 6 is a sectional view showing a conventional semiconductor device of this type. In the figure, 1 is a semiconductor substrate having a PN junction, 2 is a support plate that supports this semiconductor substrate 1, and 3 is a support plate that supports the semiconductor substrate 1. A brazing material layer 4 that adheres to the plate 2 is an electrode layer formed on the semiconductor substrate 1.

Generally, when configuring such a semiconductor device, after impurity diffusion is performed on the semiconductor substrate 1 to form a desired PN junction, a brazing material layer 3 is sandwiched between the semiconductor substrate 1 and the support plate 2, and After performing high-temperature treatment in medium, inert gas, or reducing gas and brazing the semiconductor substrate 1 and support plate 2 together with a brazing material layer 3, an electrode layer is formed using a method such as vapor deposition or spacing. form 4. In this case, the above-mentioned high-temperature treatment is carried out at a temperature higher than the melting point of the brazing material layer 3. For example, when kl or A I-S i is used as the brazing material, this temperature is 600 to 650°C, and the brazing is performed at a temperature of 600 to 650°C. Temperature difference between temperature and room temperature and semiconductor substrate1. Due to the difference in thermal expansion coefficients between the support plate 2 and the brazing material layer 3, a triple bimetal effect occurs, and the semiconductor device after brazing at room temperature will be slightly warped.

For example, as the semiconductor substrate 1, silicon having a thickness of 900 μ-
If molybdenum with a thickness of 5ffII11 is used as the support plate 2 and aluminum with a thickness of 20μ■ as the brazing material, and each material is disc-shaped, the relationship between diameter and warpage is calculated as shown in Figure 7. . According to this figure, when the diameter is 1000111, the warpage is 120 μm, which almost matches the actual measurement value.

In large-capacity semiconductor devices, it is common to use a pressure contact structure as a method for taking out electrodes. At this time, the voltage drop due to the electrical contact resistance between the electrodes of the semiconductor device and the external electrode is This is a very important factor in terms of characteristics. In the case of a warped semiconductor device as shown in FIG. 6, the on-state characteristics and thermal resistance largely depend on the pressure applied during press-welding. FIG. 8 is a diagram showing the dependence of forward voltage drop (hereinafter referred to as VFM) on pressure contact force of a conventional high power diode. VFM decreases as the pressure increases, but VFM tends to saturate with pressure when the pressure is 300 kg/c+J or more per unit area.

This pressure contact force dependence becomes even greater in high-speed silicon risks with small cathode electrodes, transistors, gate turn-off silicon risks, etc. For gate turn-off silicon risks of the same diameter, the pressure contact force at which VFM saturation is observed is 6.
00 kg/cTi or more. In order to increase the pressure contact force, it is not only necessary to increase the size of the pressure mechanism for supplying the pressure contact force, but also causes problems such as deformation of the external electrode and the inability to obtain a uniform pressure contact state, resulting in noise. was there.

FIG. 9 is a diagram showing the extent of deformation of the external electrode during press-contact of a conventional high-power diode. FIG. 9(a) shows the initial state of pressure welding, and FIG. 9(b) shows the state when pressure welding is completed.

In the early stage of FIG. 9(a), due to the warpage of the semiconductor device,
Since the central part of the cathode electrode 9 and the outer peripheral part of the anode electrode 10 are pressurized, these parts are deformed, but when the pressure welding is completed, the warpage of the semiconductor device is corrected by the pressure force, so the deformation occurs in the initial state of the pressure welding. The pressing force directly under the external electrode decreases, and the distribution of the pressing force becomes uneven.

[Problem that the invention seeks to solve]

Such non-uniformity in the pressure contact force initially appears as an increase in VFM, but when used for a long period of time, it also causes changes in electrical characteristics over time, which is undesirable.

Furthermore, as mentioned above, since VFM and thermal resistance are highly dependent on pressure contact force, variation in pressure contact force increases the fluctuation range of VFM and thermal resistance, so it is necessary to have a large guard band due to the characteristics of semiconductor devices. There were some problems.

This invention was made to solve the above-mentioned problems, and it is possible to reduce the dependence of the electrical, thermal, and thermal characteristics of a semiconductor device on pressure contact force, and to reduce the deformation of the external electrode due to cracking during pressure contact. The objective is to obtain a highly reliable semiconductor device that can perform

[Means for solving problems]

A semiconductor device according to the present invention includes a semiconductor substrate, a first support plate having a coefficient of thermal expansion larger than that of the semiconductor substrate, and a coefficient of thermal expansion smaller than that of the first support plate and a coefficient of thermal expansion smaller than that of the semiconductor substrate. It has a large second support plate, and the semiconductor substrate and the first support plate, and the first support plate and the second support plate are each brazed with a brazing material layer.

[Effect]

In this invention, the support plate is divided into two layers as described above, the first support plate being directly brazed to the semiconductor substrate, and the second support plate being brazed to the first support plate. The first and second support plates both have a larger coefficient of thermal expansion than the semiconductor substrate, but the first support plate has an even larger coefficient of thermal expansion than the second support plate. This is because the bimetallic effect caused by the difference in coefficient of thermal expansion between the first support plate and the second support plate is canceled by the bimetallic effect caused by the difference in the coefficient of thermal expansion between the first support plate and the semiconductor substrate. This reduces the warpage of the subsequent semiconductor device.

〔Example〕

FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention. In FIG. 1, 1 and 4 are the same as in FIG. 6, 5 is a first support plate whose coefficient of thermal expansion is larger than that of the semiconductor substrate 1, and 6 is a support plate whose coefficient of thermal expansion is larger than that of the semiconductor substrate 1. , a second support plate smaller than the first support plate 5; 7 a brazing material layer for brazing the first support plate 5 and the semiconductor substrate 1; 8 a brazing material layer for brazing the first support plate 5 and the second support plate 5; This is a brazing material layer that is used to braze the supporting plate 6.

The semiconductor substrate 1 is a silicon wafer with a diameter of 100 mm and a thickness of 900 μI, and the first support plate 5 is a silicon wafer with a diameter of 100 mm and a thickness of 10 μI.
0 μm nickel or silver plate, second support plate 6 has a diameter of 1
00 mm, 5 mm thick molybdenum or tungsten plate, brazing metal layer 7 has a diameter of 100 mm and a thickness of 20 μm.
aluminum plate, brazing metal layer 8, diameter 100 rms
, is an aluminum plate with a thickness of 20 μm. The electrode H4 is formed of an aluminum vapor deposited layer with a thickness of 10 μm.

In order to obtain such a semiconductor device, a semiconductor substrate 1.
First support plate 5. Second support plate 6. The brazing filler metal layers 7 and 8 are subjected to ultrasonic degreasing treatment using trichlorethylene, followed by acetone substitution treatment, followed by acid treatment, quenching with high purity water, dehydration treatment with acetone, and drying. After that, 600 ~
Cool after heating to 650°C.

Nickel or silver of the first support plate 5 has a larger coefficient of thermal expansion than silicon of the semiconductor substrate 1, and if molybdenum or tungsten of the second support plate 6 were not present, the silicon substrate 1 and the first support plate made of nickel or silver would be support plate 5
The structure made of the brazing material layer 7 is largely warped as shown in FIG.

Further, in a structure without the silicon substrate 1 and consisting of the first support plate 5, the second support plate 6, and the brazing material layer 8, warping occurs in the opposite direction to that shown in FIG. 2, as shown in FIG. However, the first
As shown in the figure, semiconductor substrate 1. First support plate 5. In the structure consisting of the second support plate 6 and the brazing material layer 7.8, the bimetal effect shown in FIG. 2 and the bimetal effect shown in FIG.

Also, the semiconductor substrate 1, the second support plate 6, the brazing material layer 7,
If the thickness of the first support plate 5 is fixed and the thickness of the first support plate 5 is changed and the warpage after brazing is measured, the amount of warpage and the direction of the warpage can be arbitrarily controlled, as shown in Fig. 4. did it. Therefore, even if the thickness of the semiconductor substrate 1 or the thickness of the second support plate 6 is changed, it is possible to obtain a product without warpage by optimizing the thickness of the first support plate 5. be. Further, the electrode 4 was formed by vapor deposition after brazing. As described above, according to the present invention, by adjusting the thickness of the first support plate 5, despite the large diameter,
A semiconductor device with no warpage or extremely small warpage can be obtained.

FIG. 5 shows the pressure contact force dependence of V FM of the high power diode according to the present invention. As is clear from this figure, the dependence of Vpv on the pressing force was smaller than that of the conventional one shown in FIG. 8, and when the pressing force was increased to 100 kg/ca1 or more, Vp- showed a tendency to saturate.

Although the above embodiment describes a high-power diode, the present invention can be applied to general high-power semiconductor devices in which a semiconductor substrate and a support plate are brazed together, and is particularly applicable to high-speed silicon risks, transistors, When applied to a semiconductor device in which the cathode area is extremely small compared to the anode area, such as a gate turn-off risk, great effects can be obtained.

〔Effect of the invention〕

As explained above, the present invention includes a semiconductor substrate, a first supporting plate having a coefficient of thermal expansion larger than that of the semiconductor substrate, and a coefficient of thermal expansion smaller than that of the first supporting plate and larger than that of the semiconductor substrate. Since the semiconductor substrate and the first support plate and the first support plate and the second support plate are each brazed with a brazing material layer, the semiconductor device has the same diameter. According to the present invention, it is possible to obtain good electrical contact with a smaller pressure contact force than that of the conventional method.

In addition, it is possible to downsize the external pressure mechanism, and since there is no warpage, it is possible to prevent abnormal deformation of the external electric field, which eliminates problems in electrical and thermal characteristics as in conventional examples. This method has the advantage of being able to solve the problem and obtain a highly reliable semiconductor device.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device showing one embodiment of the present invention, and FIG. , FIG. 3 is a cross-sectional view showing the state of warpage in the case of the structure of only the first support plate, the second support plate, and the brazing material layer in this invention, and FIG. 4 is a cross-sectional view showing the warpage state of the first support plate in this invention. FIG. 5 is a diagram showing the warping when the thickness is changed. FIG. 5 is a diagram showing the pressure contact force dependence of V FM of the semiconductor device according to the present invention. FIG. 6 is a cross-sectional view showing the conventional semiconductor device. Figure 8 is a diagram showing the diameter and warpage of a conventional semiconductor device. Figure 8 is a diagram showing the pressure contact force dependence of VFM of a conventional semiconductor device. Figure 9 (a) is a diagram showing the pressure applied to a conventional semiconductor device via an external electrode. FIG. 9(b) is a diagram showing the deformation of the external electrode in the initial state of pressure welding when pressure is applied through the external electrode. FIG. . In the figure, 1 is a semiconductor substrate, 5 is a first support plate, 6 is a second support plate, and 7 and 8 are brazing metal layers. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) Fig. 1 Fig. 3 Fig. 4 Fig. 1 First support pole 5-1 Q θ Fig. 5 Fig. 6 M Fig. 7 Diameter (mm) Pressure force (g/cm2)

Claims (6)

[Claims] (1) a semiconductor substrate having at least one PN junction; a first support plate having a coefficient of thermal expansion larger than that of the semiconductor substrate; and a first support plate having a coefficient of thermal expansion larger than that of the semiconductor substrate; a second support plate having a coefficient of thermal expansion smaller than that of the support plate, and the semiconductor substrate and the first support plate, and the first support plate and the second support plate are each soldered with a brazing material layer. A semiconductor device characterized by the attached. (2) The semiconductor device according to claim (1), wherein the semiconductor substrate is silicon. (3) The semiconductor device according to claim (1), wherein the first support plate is made of nickel. (4) The semiconductor device according to claim (1), wherein the first support plate is made of silver. (5) The semiconductor device according to claim (1), wherein the second support plate is made of molybdenum. (6) The semiconductor device according to claim (1), wherein the second support plate is made of tungsten.