JPS62194544A - Instruction pre-read control system - Google Patents

Abstract

PURPOSE:To perform the branch instruction at a high speed by holding a pre- read instruction and producing a branch address of the branch instruction selected by a decoder to store, to read as necessary and to set the produced address to an address counter. CONSTITUTION:The pre-read instruction read by an address counter 2 is stored in a pre-read memory 3 and also inputted to a decoder 5. The decoder 5 decides only a fact that the input instruction is equal to a branch instruction that has no reference to a general-purpose register which can be changed optionally in a program and calculates a branch address through an address generating circuit 6 to store it in a branch address store memory 4. Then the branch instruction is read out of the memory 3 and interpreted by an instruction execution control part 7 to be branched. Thus the branch address calculated previously is read out of the memory 4 and set to the counter 2. The counter 2 gives an access to the set branch address and therefore fetches the branch address instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction prefetch control method in an electronic computer.

[Conventional technology]

Conventionally, as an example of an instruction prefetch control method, when an instruction code and data necessary for executing the instruction are read into a CPU in a time-sharing manner using a common external data bus, the CPU
Prefetching the next instruction through the external bus in program order while U is executing an instruction that does not require external bus access;
There is a prefetch control method in which instructions are simply stored in registers, buffers, etc.

[Problem that the invention seeks to solve]

In such a conventional instruction prefetch control method, when a branch instruction exists in a program, the CPU decodes the branch instruction using an instruction decoder, and calculates the branch destination address only when the CPU executes the decoded instruction.
Since the instruction code must be newly read from the branch destination address, when executing the branch instruction, there is a drawback that there is almost no saving in instruction execution processing time due to instruction prefetch control.

[Means for solving problems]

The instruction prefetch control method of the present invention sequentially captures prefetched instructions outputted onto a bus and holds them in a storage means, and at the same time as the fetched instructions are input to a decoder that can determine whether the prefetched instructions are branch instructions or not. , the decoder selects a branch instruction that does not refer to a general-purpose register whose value can be arbitrarily changed during programming, and accesses the branch destination address of the selected branch instruction and the operand part of the branch instruction and the program memory. At least one of the address counter values is generated using one of them, the generated branch destination address is stored in a storage means in the same way as a prefetch instruction is stored, and the branch instruction is read from the prefetch instruction and the instruction is executed. When it is decided to branch, the branch destination address generated and stored in advance is read out and stored in an address counter that accesses the program memory.

[Example] 1 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. First, the instructions stored in the program memory are accessed by the address counter 2 and read out onto the bus 1''2.

The read command is stored in the pre-read memory 3 and is also input to the decoder 5f\. The decoder 5 only determines that the input instruction is a branch instruction that does not refer to general-purpose registers that can be arbitrarily changed in the blockrum, and only when it is a branch instruction, the operand of the branch instruction and the address value of the address counter 2 are determined. The branch destination address is calculated by the address counter 6 using at least one of the above, and the branch destination address is stored in the branch destination address storage memory 4.
and stored.

Next, the branch instruction is read from the look-ahead memory 3,
When the instruction is interpreted and executed by the instruction execution control unit 7 and a branch is to be executed, the branch destination address calculated in advance as described above is read from the branch destination address storage memory 4 and is set in the address counter 2.

The address counter 2 inputs the branch destination instruction by accessing the set branch destination address.
・Starts to do things. Therefore, when a branch instruction is interpreted and executed, since the branch destination address has already been calculated, the branch destination address storage memory 4
Therefore, simply transferring the branch destination address to the address counter 2 means that the branch is executed, and the branch process can be performed at high speed as if the branch destination address total time Mi does not exist at all.

1. Effects of the Invention As explained above, the present invention provides an instruction that prefetches an instruction, and at the same time, the prefetched instruction is a branch instruction and does not refer to the general purpose register value, which can be changed arbitrarily in the program, when calculating the branch destination address. After decoding and finding out that it is, immediately calculate the branch destination address,
By generating the branch instruction and storing it in memory, the branch instruction is read out from the read-ahead memory and executed, and when it is decided to execute the branch, the branch destination is simply stored in the memory that was generated and stored in advance. Boolean and child processing can be performed simply by reading and setting and sorting the address counter value that accesses the program memory. In other words, when the branch instruction is interpreted and executed, the time required to calculate the branch destination address is not required, and the branch can be executed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the instruction prefetch control method of the present invention.

Claims (1)

[Claims] a storage means for sequentially capturing and holding prefetched instructions outputted on a bus; a decoder for determining whether the prefetched instruction is a branch instruction; and a branch destination address of the branch instruction selected by the decoder. branch destination address storage means for storing the generated branch destination address in the same manner as when the prefetch instruction is stored; and branch destination address storage means for storing the stored branch destination address as necessary. 1. An instruction prefetch control system comprising means for reading from a branch destination address and setting the branch destination address in an address counter for accessing a program memory.