JPS62191000U

JPS62191000U -

Info

Publication number: JPS62191000U
Application number: JP1986080026U
Authority: JP
Priority date: 1986-05-26
Filing date: 1986-05-26
Publication date: 1987-12-04

Description

[Brief explanation of the drawing]

第１図は本考案のＲＯＭの一実施例のブロツク
図、第２図は第１図のカウンタ回路６のブロツク
図、第３図は従来のＲＯＭのブロツク図である。１……メモリ、２……リセツト信号発生回路、
３……トライステートバツフア、４……レジスタ
、５……比較回路、６……カウンタ回路、７，８
……ナンドゲート、９，１０……フリツプフロツ
プ、１１，１２，１５，１６……アンドゲート、
１３，１４……フリツプフロツプ、Ｂ１……内部
データバス、Ｂ２……外部より入力されたデータ
、Ｓ１……リセツト信号、Ｓ２，Ｓ３，Ｓ６，Ｓ
７……イネーブル信号、Ｓ４……フリツプフロツ
プ９の出力、Ｓ５……フリツプフロツプ１０の出
力、Ｓ９……第１のゲート信号、Ｓ８……第２の
デート信号。 FIG. 1 is a block diagram of an embodiment of the ROM of the present invention, FIG. 2 is a block diagram of the counter circuit 6 of FIG. 1, and FIG. 3 is a block diagram of a conventional ROM. 1...Memory, 2...Reset signal generation circuit,
3... Tri-state buffer, 4... Register, 5... Comparison circuit, 6... Counter circuit, 7, 8
...Nand gate, 9, 10...Flip-flop, 11, 12, 15, 16...And gate,
13, 14...Flip-flop, B1...Internal data bus, B2...Data input from outside, S1...Reset signal, S2, S3, S6, S
7...enable signal, S4...output of flip-flop 9, S5...output of flip-flop 10, S9...first gate signal, S8...second date signal.

Claims

[Claim for Utility Model Registration] A memory from which stored data is read in response to a selection signal and an address signal, a reset signal generation circuit that generates a reset signal when the power is turned on, and an internal data bus when enabled. a tristate buffer that outputs the memory data output to the internal data bus to the outside; a register that is reset by the reset signal and holds the memory data output to the internal data bus; and a register that holds the data of the register and the memory readout. Compare the data output to the internal data bus by the read cycle and find that they do not match, and compare the data output to the internal data bus by the read cycle and the data input from the outside and find that they match. In this case, a comparator circuit that outputs an enable signal, and a counter circuit that outputs a first gate signal only during the first read cycle and a second gate signal only during the second read cycle after inputting the reset signal. , first and second gate circuits that output the enable signal when the first and second gate signals are input, and are set by the enable signals from the first and second gate circuits, respectively, and the reset circuit is set by the enable signal from the first and second gate circuits, respectively. The first and second flip-flops are reset by a signal, and both outputs of the first and second flip-flops are input, and when the first and second flip-flops are in the set state, the tri-state buffer is enabled. A ROM with a read inhibiting function having a third gate circuit.