JPS62190735A - Mounting method for tape carrier type semiconductor element - Google Patents
Mounting method for tape carrier type semiconductor elementInfo
- Publication number
- JPS62190735A JPS62190735A JP3251686A JP3251686A JPS62190735A JP S62190735 A JPS62190735 A JP S62190735A JP 3251686 A JP3251686 A JP 3251686A JP 3251686 A JP3251686 A JP 3251686A JP S62190735 A JPS62190735 A JP S62190735A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- tape carrier
- semiconductor element
- substrate
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明はテープキャリア式半導体素子を基板に実装する
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for mounting a tape carrier type semiconductor device on a substrate.
[従来の技術]
従来、この種の実装方法は第4図に示す様にテープキャ
リア1から半導体素子2を予め切離した後、基板3の接
続パッド31に素子2のリード21を圧着等の方法で接
続することにより行われていた。[Prior Art] Conventionally, this type of mounting method involves, as shown in FIG. 4, cutting the semiconductor element 2 from the tape carrier 1 in advance, and then crimping the leads 21 of the element 2 to the connection pads 31 of the substrate 3. This was done by connecting with.
[発明が解決しようとする問題点]
上述した実装方法はテープキャリア1から予め半導体索
子2は分離されているため、基板3に実装するまでの工
程で外部接続リード21が変形する等のトラブルが生じ
易く、接続リード21と接続パット31の位置合せが困
難となる欠点がある。[Problems to be Solved by the Invention] In the above-described mounting method, since the semiconductor cord 2 is separated from the tape carrier 1 in advance, troubles such as deformation of the external connection leads 21 occur during the process up to mounting on the board 3. This has the drawback that alignment of the connection lead 21 and the connection pad 31 is difficult.
本発明の目的は半導体素子の外部接続リードの変形を防
止する実装方法を提供することにある。An object of the present invention is to provide a mounting method that prevents deformation of external connection leads of a semiconductor element.
[問題点を解決するための手段]
本発明はテープキャリア上に形成された半導体素子の外
部接続リードの一部に切欠きを設け、前記外部接続リー
ドを切欠きの手前位置で基板に圧着して半導体素子を該
基板上に実装し、その後前記切欠き部分で外部接続リー
ドを切断して半導体素子をテープキャリアから切り離す
ことを特徴とするテープキャリア式半導体素子の実装方
法である。[Means for Solving the Problems] The present invention provides a method in which a notch is provided in a part of the external connection lead of a semiconductor element formed on a tape carrier, and the external connection lead is crimped to the substrate at a position in front of the notch. This tape carrier type semiconductor device mounting method is characterized in that the semiconductor device is mounted on the substrate using a tape carrier, and then the external connection leads are cut at the cutout portion to separate the semiconductor device from the tape carrier.
[実施例]
次に本発明の一実施例について図面を参照して説明する
。[Example] Next, an example of the present invention will be described with reference to the drawings.
第3図は本発明の一実施例を示す平面図であり、第3図
に示すようにテープキャリア1上に形成される半導体素
子2は該素子2の外部接続リード21を介して該テープ
キャリア1に支持されている。FIG. 3 is a plan view showing an embodiment of the present invention, and as shown in FIG. 1 is supported.
本発明ではテープキャリア1上の半導体素子2の外部接
続リード21の一部に切欠き22を設けている。In the present invention, a notch 22 is provided in a part of the external connection lead 21 of the semiconductor element 2 on the tape carrier 1.
第1図、第2図に示すように、本発明は切欠き22の手
前位置上の半導体素子2の外部接続リード21に圧着ツ
ール4の外端4aを位置させツール4によりリード21
を基板3上の接続パッド31に圧着し、半導体素子2を
基板3上に実装する。リード21の切欠き22部の手前
位置に圧着ツール4の外端4aを位置させて圧着するこ
とにより、テープキャリア1側に残ったり一部23と圧
着部25の境界に切断容易なり一部破断部24が生成さ
れる。第3図に示す様にテープキャリア1に取り付けた
まま半導体素子2を基板3に実装した後、圧着ツール4
で外部接続リード21と接続パッド31とを圧着したま
ま、テープキャリア1を矢印へ方向に引き上げてり一部
破断部24で外部接続リード21を切断し、テープキャ
リア1から半導体素子2を切り離す。As shown in FIGS. 1 and 2, the present invention involves positioning the outer end 4a of the crimping tool 4 on the external connection lead 21 of the semiconductor element 2 on the front side of the notch 22, and using the tool 4 to connect the lead 21.
is pressed onto the connection pads 31 on the substrate 3, and the semiconductor element 2 is mounted on the substrate 3. By positioning the outer end 4a of the crimping tool 4 at a position in front of the notch 22 of the lead 21 and crimping, the tape remains on the tape carrier 1 side, or is easily cut at the boundary between the part 23 and the crimping part 25, resulting in a partial breakage. 24 is generated. As shown in FIG. 3, after mounting the semiconductor element 2 on the substrate 3 while still attached to the tape carrier 1,
While the external connection leads 21 and connection pads 31 are still crimped, the tape carrier 1 is pulled up in the direction of the arrow, the external connection leads 21 are cut at the partially broken portion 24, and the semiconductor element 2 is separated from the tape carrier 1.
[発明の効果]
以上説明した様に本発明によれば、半導体素子の外部接
続リードに切欠きを設け、半導体素子をテープキャリア
のまま基板に実装した後、切欠き部分でリードを切断し
て半導体素子をテープキャリアから切り離すため、半導
体素子を単体で取扱う必要がなくなり、製造工程が簡素
化され、且つ歩留りを向上できる。またテープキャリア
のまま基板上に位置合せできるので、リード変形等のト
ラブルが激減し、組立精度が良くなり、製造工程の自動
化を容易に実現できる効果を有するものである。[Effects of the Invention] As explained above, according to the present invention, a notch is provided in the external connection lead of a semiconductor element, and after the semiconductor element is mounted on a board as a tape carrier, the lead is cut at the notch part. Since the semiconductor element is separated from the tape carrier, there is no need to handle the semiconductor element alone, which simplifies the manufacturing process and improves yield. Furthermore, since the tape carrier can be positioned on the substrate as it is, troubles such as lead deformation are drastically reduced, assembly accuracy is improved, and manufacturing process automation can be easily realized.
第1図及び第2図は本発明による実装方法を示す説明図
、第3図は本発明に係る半導体素子の一例を示す平面図
、第4図は従来の実装方法を示す説明図である。
1・・・テープキャリア、 2・・・半導体素子。
3・・・基板、 4・・・圧着ツール。
21、23・・・半導体の外部接続リード。
22・・・切欠き。
24・・・外部接続リードの破断部。
25・・・圧着部1 and 2 are explanatory diagrams showing a mounting method according to the present invention, FIG. 3 is a plan view showing an example of a semiconductor element according to the present invention, and FIG. 4 is an explanatory diagram showing a conventional mounting method. 1...Tape carrier, 2...Semiconductor element. 3... Board, 4... Crimping tool. 21, 23... Semiconductor external connection leads. 22...notch. 24...Broken part of external connection lead. 25...Crimp part
Claims (1)
接続リードの一部に切欠きを設け、前記外部接続リード
を切欠きの手前位置で基板に圧着して半導体素子を該基
板上に実装し、その後前記切欠き部分で外部接続リード
を切断して半導体素子をテープキャリアから切り離すこ
とを特徴とするテープキャリア式半導体素子の実装方法
。(1) A notch is provided in a part of the external connection lead of the semiconductor element formed on the tape carrier, and the external connection lead is crimped to the substrate at a position in front of the notch to mount the semiconductor element on the substrate. . A method for mounting a semiconductor device on a tape carrier, characterized in that the semiconductor device is separated from the tape carrier by cutting the external connection lead at the cutout portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3251686A JPS62190735A (en) | 1986-02-17 | 1986-02-17 | Mounting method for tape carrier type semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3251686A JPS62190735A (en) | 1986-02-17 | 1986-02-17 | Mounting method for tape carrier type semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62190735A true JPS62190735A (en) | 1987-08-20 |
Family
ID=12361133
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3251686A Pending JPS62190735A (en) | 1986-02-17 | 1986-02-17 | Mounting method for tape carrier type semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62190735A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04251947A (en) * | 1991-01-09 | 1992-09-08 | Nec Corp | Tab-integrated circuit |
JPH05226408A (en) * | 1992-02-17 | 1993-09-03 | Nec Corp | Tab integrated circuit |
-
1986
- 1986-02-17 JP JP3251686A patent/JPS62190735A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04251947A (en) * | 1991-01-09 | 1992-09-08 | Nec Corp | Tab-integrated circuit |
JPH05226408A (en) * | 1992-02-17 | 1993-09-03 | Nec Corp | Tab integrated circuit |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS62190735A (en) | Mounting method for tape carrier type semiconductor element | |
JPH08148623A (en) | Semiconductor device | |
JP2768111B2 (en) | TAB-Method of Manufacturing Integrated Circuit and TAB Tape for the Method | |
JP2751104B2 (en) | Method for manufacturing lead frame for semiconductor device | |
KR200153438Y1 (en) | Chip scale package with tap tape | |
JP2731584B2 (en) | Lead frame and method of manufacturing electronic component package using the same | |
JP3157249B2 (en) | Semiconductor device package and mounting method | |
JPS63204735A (en) | Package structure for semiconductor device | |
JPH0637573Y2 (en) | Board-in connector structure for shielded wires | |
JP2846095B2 (en) | Method for manufacturing semiconductor device | |
KR930005495B1 (en) | Lead frame and manufacturing thereof | |
JPH03149893A (en) | Semiconductor device | |
JPS5832264Y2 (en) | Lead frame holder | |
JPH05291739A (en) | Connecting terminal and connecting method for device using same | |
JPH0731551Y2 (en) | Bonding structure of circuit block and electrode plate | |
JPH092410A (en) | Carriage device for electronic parts, and manufacture of electronic parts therewith | |
JPH0446453B2 (en) | ||
EP0901164A2 (en) | Integrated circuit packaging method, packaging apparatus, and package | |
JP2842854B2 (en) | Method for manufacturing semiconductor device | |
JPH03129869A (en) | Lead frame | |
JPH01248655A (en) | Manufacture of lead frame for semiconductor device | |
JPS6017934A (en) | Semiconductor device | |
JPH06224351A (en) | Apparatus and method for trimming and forming lead of semiconductor device | |
JPS62213212A (en) | Chip inductor | |
JPH06204392A (en) | Ic package |