JPS6218839A - Power line carrier system transmission and reception circuit - Google Patents

Abstract

PURPOSE:To decide the kind of a signal by the mode decision means of a reception part by superposing a carrier in positive half periods, negative half periods, and the entire period of an AC power source and superposing no carrier in the whole period by the mode switching means of a transmission part, and outputting four kinds of signal through an electric power line. CONSTITUTION:When the movable contact 3e of a switch 3 is connected to the 1st fixed contact 3a, the other input terminal of the 1st AND gate circuit 4 goes up to 'H' at the transmission part and a carrier is outputted by the 1st AND gate circuit 4 in positive half periods of the power source in synchronism with the 1st gate signal G. This carrier is applied to the electric power line 7 through an OR circuit 6 and a coupling circuit 8 and superposed upon a source voltage as shown in a figure 3. (Positive half period superposition mode). Further, a mode switching means 4 is provided which switches selectively four transmission modes meaning four different contents, i.e. negative half period superposing mode in which a signal is outputted by the being superposed in a negative half period of the AC power source, a full-wave superposition mode in which the signal wave is outputted by being superposed upon the whole wave of the AC power source, and a mode in which no signal is superposed in addition to said mode. A reception part is provided with a mode decision means which discriminates said transmission modes.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a power line carrier type transmitting/receiving circuit that is improved to be able to accurately transmit four types of signals with different contents, that is, a signal wave is superimposed on a power line from a transmitter. This relates to a transmitting/receiving circuit that transmits the received data to a receiving section.

[Prior art]

Transmitting/receiving circuits that transmit and receive signal waves via power lines laid between the transmitting section and the receiving section do not require the installation of transmission lines for signal wave transmission, so they have traditionally been used to transmit analog signals such as voice. It is widely used for communication.

However, power lines were not originally installed to transmit signal waves, and their quality as signal transmission lines is by no means good. In addition, power lines include fluorescent lights, motors,
Since various devices using switching elements such as Cyrisk are connected, noise is mixed in, making it unsuitable for transmitting digital signals. In particular, the noise generated by Cyrisk (so-called Cyrisk noise) has a large level and a sharp rise, and therefore contains many frequency components, making it difficult to remove with a filter.

If such sirisk noise mixes into the signal, the pulse width of the digital signal may become shorter, or false pulses may occur between the pulses, making it impossible to decipher the information in the signal. Data and control signals could not be accurately transmitted using digital signals unless the conditions were very good.

In order to eliminate such inability to decipher due to noise, the time of the rHJ level or rLJ level of the signal input to the receiver is measured by a control device such as a microcomputer,
Some devices are designed to determine that a signal has been correctly decoded if it is within a predetermined error range (for example, ±30%).

However, this method has the disadvantage that if the central part of the waveform is missing due to noise, it is determined that the decoding has not been done correctly.

[Purpose of the invention]

The present invention has been made in consideration of the above-mentioned problems, and is not affected by noise that occurs in an extremely short period of time such as syrisk noise, and can generate four types of different content using a very simple circuit. The object of the present invention is to provide a power line carrier type transmitting/receiving circuit that is capable of transmitting and receiving signals.

[Structure of the invention]

A power line carrier type transmitting/receiving circuit according to the present invention superimposes a signal wave on a power line from a transmitting section and transmits it to a receiving section, and the transmitting section superimposes a signal wave on a positive half cycle of an AC power source. positive half-cycle superposition mode that outputs a signal wave on the negative half-cycle of the AC power supply, negative half-cycle superposition mode that superimposes a signal wave on the negative half-cycle of the AC power supply, and full-wave superposition mode that outputs the signal wave superimposed on the full wave of the AC power supply. mode and a mode in which no signal is superimposed, which means four different transmission modes, are provided, and the receiving section is provided with mode discrimination means for discriminating the above-mentioned transmission mode. The present invention is characterized in that it is configured to discriminate four types of signals that differ depending on the mode.

In order to simplify the circuit configuration, it is advantageous for the mode determining means of the receiving circuit to be composed of an integrating means for integrating the received signal and a comparing means for comparing the integration result with a reference voltage.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

The transmitter shown in FIG. 1 (1) includes a carrier oscillator 1 that generates a carrier to be superimposed on a power supply, and two gate signals G and -d whose phases are inverted to each other by controlling the timing at which this carrier is superimposed on the power supply. - gate signal forming circuit 2 that generates - from AC 100 ports, a switch 3 that switches the carrier superimposition state on the power supply into four types, two AND gate circuits 4 and 5, and the outputs of both AND gate circuits 4 and 5. , and a coupling circuit 8 that transmits the carrier output from the OR circuit 6 to a power line 7.

The carrier oscillator 1 has an accurate frequency (generally 100
A device that emits a frequency of about 400 KHz may be used.

The gate signal forming circuit 2 outputs a first gate signal G [see FIG. 3 (2)] which alternately switches between rHJ and "L" in synchronization with the power supply voltage shown in FIG. 3 (1). The gate signal is supplied to the first AND gate circuit 4, and the second gate signal whose phase is reversed by 180 degrees is supplied to the second AND gate circuit 5.

The switch 3 has four fixed contacts 3a to 3d and one movable contact 3e, the first fixed contact 3a directly and the third fixed contact 3C via a forward connection diode 9. It is commonly coupled to one input terminal of the first AND gate circuit 4. In addition, the second fixed contact 3b directly
The third fixed contacts 3c are commonly connected to one input end of each second AND gate circuit 5 via another forward-connected diode 10. The fourth fixed contact 4d is not connected to any of the AND gate circuits 4 and 5 and is grounded. Note that each of the fixed contacts 3a to 3d is grounded via grounding resistors 112 to Ild so as to maintain a predetermined voltage when the fixed contacts 3a to 3d are connected to the movable contact 3e.

The carrier oscillator 1 has the other input terminal of a first AND gate circuit 4 which is manually opened by inputting a first gate signal G, and a second AND gate circuit which is opened by inputting a second gate signal G. and the other input terminal of 5. Note that the coupling circuit 8 is coupled to the power line 7 via a capacitor 12.

On the other hand, as shown in FIG. 1 (2), the receiving section receives two gate signals synchronized with the power supply voltage and a reset signal R that becomes rHJ at the zero cross point of the power supply from the power line 7, and whose phases are reversed to each other. A signal forming circuit 21 that generates G.
A phase locking circuit (PLL) 25 is provided. The output terminal of this PLL 25 is connected to an integrating circuit 27 made up of a capacitor via a diode 26, and further connected to a comparing circuit 28 which inputs the output of this integrating circuit 27 to its positive phase input terminal. A reference voltage at a predetermined level is input from a reference voltage setting circuit 29 to the negative phase input terminal of this comparison circuit 28 . This reference voltage is set, for example, to turn on when the output voltage of the integrating circuit 27 is constant and exceeds a level. In addition, the capacity of the integrating circuit 27 is the same as that of a PLL in which carriers are continuously input for about 20% of a half cycle of the power supply.
The amount of electricity output by 25 may be sufficient. Further, in order to reset the integrating circuit 27 every half cycle of the power supply, a reset circuit 30 is provided which receives the reset signal R and shorts both ends of the integrating circuit 27. The output terminal of the comparison circuit 28 is connected to one input terminal of each of the two AND circuits 31 and 32, and the first gate signal G is connected to the other input terminal of the first AND circuit 31, and the first gate signal G is connected to the second input terminal. AND circuit 32
A second gate signal 100 is input to the other input terminal of the gate.

The output end of the first AND circuit 31 has a retrigger type first one-shot multi-by-break (OMV) 33 that is triggered by the rising edge of a pulse, and a second retrigger type one-shot multi-by-break (OMV) 33 that is triggered by the rising edge of the pulse. They are individually and directly connected to the shot multi-high break (OMV) 35 and the third input terminal of the second output AND circuit 36 . The normal output terminal Q of the first OMV 33 is connected to one input terminal of the first output AND circuit 34, and the inverted output terminal is connected to the first input terminal of the third output AND circuit 37. be done. Further, the normal rotation output terminal Q of the second OMV 35 is connected to the first input terminal of the second output AND circuit 36.

The output terminal of the second AND circuit 32 is connected to the other input terminal of the first output AND circuit 34, a third one-shot multi-by-break (OMV) 38 of a retrigger type that is triggered at the rising edge of a pulse, 3 output AND circuit 3
7 and is directly and individually connected to a fourth one-shot multi-by-break (OMV) 39 of the retrigger type that is triggered on the rising edge of the pulse. The inverted output terminal -d- of the third OMV 38 is connected to the second input terminal of the second output AND circuit 36, and the normal output terminal Q of the fourth OMV 39 is connected to the third output AND circuit 37. It is connected to the third input terminal. The first to third output AND circuits 34, 36, and 37 have output terminals 40, 41, and 37, respectively.
It has 42.

In the above configuration, in the transmitting section of FIG. 1(1), when the movable contact 3e of the switch 3 is connected to the first fixed contact 3a, the other input terminal of the first AND gate circuit 4
Therefore, carriers are output from the first AND gate circuit 4 in the positive half cycle of the power supply in synchronization with the first gate signal G. This carrier is applied to the power line 7 via the OR circuit 6 and the coupling circuit 8, and is superimposed on the power supply voltage as shown in FIG. 2 (3) (positive half cycle superimposition mode).

When the movable contact 3e of the switch 3 is connected to the second fixed contact 3b, the other input terminal of the second AND gate circuit 5 becomes r.
HJ, and the carrier is output from the second AND gate circuit 5 in the negative half cycle of the power supply in synchronization with the second gate signal 100, and as shown in FIG. 2 (4), the carrier is output in the negative half cycle of the power supply. The superimposed power supply voltage is transmitted via the power line 7 (negative half cycle superimposition mode).

When the movable contact 3e of the switch 3 is connected to the third fixed contact 3C, the other input terminals of the first and second AND gate circuits 4 and 5 become rHJ, and the positive voltage of the power supply is connected from the first AND gate circuit 4. A carrier is output during a half period of , and a carrier is output from the second AND gate circuit 5 during a negative half period of the power supply. The outputs of both AND gate circuits 4 and 5 are input to the OR circuit 6, and continuous carriers are output from the OR circuit 6 over the entire cycle of the power supply, as shown in FIG.
), the power supply voltage on which carriers are superimposed over all cycles is transmitted via the power Ss7 (full cycle superimposition mode).

When the movable contact 3e of the switch 3 is connected to the fourth fixed contact 3d, the other input terminals of the AND gate circuits 4 and 5 become Il], so that the entire Carriers are not superimposed over the period (non-superimposition mode)
.

In the receiving section of FIG. 1 (2), which receives four types of signals that differ depending on the carrier superimposition state, the carrier signal is big-amplified from the power line 7 by the coupling circuit 22 and the low-frequency signal component is removed by the capacitor 23. ,PLL25
The presence or absence of the carrier is detected by the PLL 25. That is, when a carrier is input, the PLL 25
The output becomes "H" over a predetermined capture range, and the presence of a carrier is detected. for example,
When carriers are superimposed on the positive half cycle of the power supply as shown in Figure 3 (1), the output of the PLL 25 is as shown in Figure 3 (2).
), the PLL 25 output is "H" during the positive half cycle of the power supply and rLJ during the negative half cycle. Since the output of the PLL 25 divided by the reset signal R, that is, the data length, is a half cycle of the power supply, by making the capture range of the PLL 25 very small and appropriately setting the cutoff frequency of the capacitor 23, it is possible to Mixed noise can be sufficiently reduced or removed.

The output of the PLL 25 is as shown in FIG. 3 (4),
It is integrated by the successive integration circuit 27 during the positive half period of the power supply,
When this integrated amount exceeds the integrated amount of the output of the PLL 25 corresponding to the carrier for a period of about 20% of the half cycle of the power supply, the output of the PLL 25 is transmitted to the comparator circuit 28, and a comparison is performed as shown in FIG. 3 (5). The circuit 28 becomes H. The integrating circuit 27 synchronizes with the zero cross point of the power supply and outputs rH every half cycle.
The reset signal R [FIG. 3 (3)] that becomes J is short-circuited by the reset circuit 30 that manually inputs it, and each time the input of the output of the comparator circuit 28 partially becomes rLJ, and the input of the output of the comparator circuit 28 becomes rLJ again.
When the integrated amount of the output of the PLL 25 corresponding to the carrier for a period of about 20% of the half cycle of the 7 power supply is exceeded, the output of the comparison circuit 28 becomes rHJ.

When a carrier is superimposed on the positive half cycle of the power supply, the output of the comparison circuit 28 is, for example, from the zero cross point at the start of the positive half cycle of the power supply, as shown in FIG. 3 (5). It becomes rHJ at the time of 20% delay, and becomes a pulse that becomes "L" at the zero cross point at the end of the positive half cycle of the power supply. The output of the first AND circuit 31 becomes I'l'' in synchronization with this pulse, but the output of the second AND circuit 32 remains rLJ during the entire cycle of the power supply.

When carriers are superimposed on the negative half cycle of the power supply, the output of the comparator circuit 28 becomes rHJ at a point delayed by, for example, 20% of the half cycle from the zero cross point at the start of the negative half cycle of the power supply, The pulse becomes rI-J at the zero crossing point at the end of the negative half period of . Therefore, the output of the second AND circuit 32 becomes rHJ in synchronization with this pulse, but the output of the first AND circuit 31 remains "L" throughout the entire cycle of the power supply.

When a carrier is superimposed on the entire cycle of the power supply, the above pulse is output from the first AND circuit 31 during the positive half cycle of the power supply, and the pulse is output from the second AND circuit 32 during the negative half cycle of the power supply.
The above pulse will be output from.

When a carrier is superimposed on the positive half cycle of the power supply, the output of the second AND circuit 32 overlaps with the entire cycle of the power supply rL
J, the first and third output AND circuits 3
Each output of 4.37 is rLJ during the entire cycle of the power supply. On the other hand, the output Q of the second OMV 35, which inputs the output of the first AND circuit 31, switches to "H" at the rising edge of the first pulse output from the first AND circuit 31, and Since the inverted output Q of the OMV 38 is "■" over the entire frequency of the power supply, the output of the second output AND circuit 36 becomes rHJ in synchronization with the pulse output from the first AND circuit 31.

In this way, only the output of the second output AND circuit 36 is "
r('', it is determined that the carrier superimposition state is a positive half-cycle superimposition mode in which carriers are superimposed on a positive half-cycle.

When a carrier is superimposed on the negative half cycle of the power supply, the output of the first AND circuit 31 to which the first gate signal is input becomes "L" throughout the entire cycle of the power supply, and the first ○MV
The output of the normal rotation output terminal Q of 33 stays in the entire cycle of the power supply rL
J, the output of the first output AND circuit 34 is r
Becomes LJ.

Further, since the output Q of the second MV 35 similarly becomes rLJ over the entire cycle of the power supply, the output of the second output AND circuit 36 also becomes rLJ. In contrast, the first OMV
330 inverted output becomes r HJ during the entire cycle of the power supply, and the output Q of the fourth OMV39 is output from the second AND circuit 32.
The output -d- of the third output AND circuit 37 becomes rHJ in synchronization with the pulse output from the second AND circuit 32, since it becomes rHJ after the rise of the first pulse output from the second AND circuit 32.

In this way, only the output of the third output AND circuit 37 is r
By being HJ, it is determined that the carrier superimposition state on the power supply is a negative half cycle superimposition mode in which carriers are superimposed on a negative half cycle.

When the carrier is superimposed on the power supply in the full cycle superimposition mode over all cycles, the inverted output amount of the first OMV 33 is switched to "L" at the rise of the first pulse output from the first AND circuit 31. . Therefore, the output of the third output AND circuit 37 becomes rLJ. Also, the third
Since the output amount of the OMV 38 is switched to rLJ at the rising edge of the first pulse output from the second AND circuit 32, the output of the second output AND circuit 36 also becomes rLJ. On the other hand, the normal rotation output Q of the first OMV 33 is r
Since it can be switched to HJ, the first output AND circuit 3
The output of 4 is connected to the second AND circuit 32 within the negative half period of the power supply.
It becomes rHJ in synchronization with the output of.

In this way, only the output of the first output AND circuit 34 is r
By being HJ, it can be determined that the carrier superimposition state on the power supply is a full cycle superimposition mode in which carriers are superimposed on all cycles.

When the carrier superimposition state on the power supply is a non-superimposition mode in which carriers are not superimposed over the entire cycle, the first O
Since the normal rotation output Q of MV33 becomes rLJ, the output of the first output AND circuit 34 becomes "L", and the output of the second OMV3 becomes "L".
Since the output of 5 becomes rLJ, the second output AND circuit 3
The output of 6 becomes rLJ, and the output of 4th OMV39 becomes r
Since it becomes L'J, the output of the third output AND circuit 37 also becomes "L".

In this way, when the outputs of all the output AND circuits become rLJ, it can be determined that the carrier superimposition state is the non-superimposition mode.

The output obtained at each output terminal 40 to 41 in this way is
For example, the output of the output terminal 41 can be used as a forward rotation drive command for a motor (not shown), the output of the output terminal 42 can be used as a reverse rotation drive command of the motor, and the output of the output terminal 40 can be used as a stop command of the motor.

〔Effect of the invention〕

As described above, the power line carrier type transmitting/receiving circuit of the present invention superimposes a carrier on a positive half cycle, a negative half cycle, or a full cycle of an AC power source, or superimposes a carrier on a full cycle using the mode switching means of the transmitter. By not doing so, four types of signals are outputted via the power line, and the type of the signal can be determined by the mode determining means of the receiving section. Therefore,
It has a very simple configuration that does not use complex filter circuits or microcomputers, so even if the center of the signal is missing due to noise, it can correctly process the signal as long as the signal loss is less than 80%. It has the advantage of being able to transmit and receive four types of signals via a power line with almost no influence of noise.

[Brief explanation of the drawing]

FIG. 1 (1) is a circuit diagram of a main part of a transmitter according to an embodiment of the present invention, FIG. 1 (2) is a circuit diagram of a main part of a receiver according to an embodiment of the present invention, and FIG. 1) is a waveform diagram of the power supply, Figure 2 (2) is a waveform diagram of gate signal G, and Figures 2 (3) to 2 (6) are positive half cycle superimposition mode, negative half cycle superimposition mode, and full cycle mode, respectively. FIG. 3 (1) is a waveform diagram of the transmitter output signal in the period superimposition mode and non-superimposition mode. FIG. 3 (1) is a waveform diagram of the receiver input signal in the positive half cycle superimposition mode. FIG. , Figure 3 (3) is a waveform diagram of the reset signal,
FIG. 3 (4) is a waveform diagram of the output of the integrating circuit in the positive half cycle superimposition mode showing the relationship with the reference voltage, and FIG. 3 (5) is a waveform diagram of the output of the comparator circuit in the positive half cycle superimposition mode. 1 is a carrier oscillator, 2 is a gate signal forming circuit, 3 is a switch, 4 is a first AND gate circuit, 5 is a second AND gate circuit, 6 is an OR circuit, 7 is a power line, 8 is a coupling circuit, 9. 1o is a forward connection diode, 1la to 11d are each grounding resistor, 21 is a signal forming circuit, 22 is a coupling circuit, 23
is a capacitor, 24 is an amplifier circuit, 25 is a phase locking circuit, 26 is a diode, 27 is an integration circuit, 28 is a comparison circuit, 29 is a reference voltage setting circuit, 30 is a seven node circuit,
31 is the first AND circuit, 32 is the second AND) circuit,
33 is a first one-shot multi-by break, 34 is a first output AND circuit, 35 is a second one-shot multi-high break, 36 is a second output AND circuit, 3
7 is the third output AND circuit, 38 is the third one-shot multi-by-break, and 39 is the fourth one-shore circuit.
Multi-high flakes, 40 to 42 are respective output ends. Figure 2 Figure 3 J (1S)

Claims (1)

[Claims] 1. A signal wave is superimposed on a power line from a transmitter and transmitted to a receiver, and the signal wave is superimposed on a positive half cycle of an AC power source and output to the transmitter. A positive half-cycle superimposition mode, a negative half-cycle superimposition mode that superimposes a signal wave on the negative half cycle of the AC power supply and outputs it, and a full-wave superposition mode that superimposes the signal wave on the full wave of the AC power supply and outputs it. A mode switching means is provided for selectively switching between a transmission mode meaning four different contents including a mode in which no signal waves are superimposed, and a mode discrimination means for discriminating the above transmission mode is provided in the receiving section. A power line carrier transmitting/receiving circuit characterized in that it is configured to discriminate between four different types of signals. 2. The mode determining means of the receiving circuit is comprised of an integrating means for integrating the received signal and a comparing means for comparing the integration result with a reference voltage.
The power line carrier type transmitting/receiving circuit described in .