JPS62183176A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the electrical connection between metallic electrodes with excellent heat resistance and conductivity and semiconductor regions by a method wherein compound layers with energy gap shorter than that of compound substrate are laid between semiconductor regions on the surface of compound substrate and electrodes connected to the semiconductor regions. CONSTITUTION:n<+> type conductive layers 5 comprising compound of e.g. Ga, In, As and Sb epitaxially grown on the surface of an n<+> type semiconductor region 4 as source.drain region are buffer layers to ohmic connect electrodes 6 comprising Al layers connected to the surface of conductive layers 5 to n<+> type semiconductor region 4. The thickness of conductive layers 5-1-5n is around 1 - several 10nm and the lower the layer, the more Ga and As are contained and the less In and Sb are contained while the higher the layer, the compounds are contained vice versa. The level of energy barrier at the junction of regions 4 and conductive layers 5 as well as that between the conductive layer 5n and the Al layer electrodes 6 are not exceeding around 0.1eV while the miss alignment of grids between the conductive layer 5-1 and the conductive layer 5n and the level of energy barrier are respectively not exceeding around 1% and 0.1eV. Through these procedures, effective level of energy barrier between the electrodes 6 and the semiconductor regions 4 is lowered by laying the conductive layers 51-5n between the electrodes 6 and the semiconductor regions 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device using a compound substrate.

[Conventional technology]

MESFET (Metal Sem1conduct)
For example, technology related to FET or FET).

Published by Nikkei McGraw-Hill 1 Nikkei Electronics, 19
It is described in the January 14, 1985 issue, pages 213-239.

The present inventor studied an electrode connected to a semiconductor element using a gallium arsenide (GaAs) substrate. Although the following is not a publicly known technique, it is a technique studied by the present inventor, and its outline is as follows.

MESFET, heterojunction FET by heterojunction with GaAlAs, heterojunction bipolar transistor,
In a semiconductor device using a GaAs substrate, such as a light emitting element, a light receiving element, or an optical integrated circuit in which an optical element and an electric element are mixed, an aluminum layer cannot be used for the electrode connected to the source and drain. This is because an ohmic connection cannot be obtained with an electrode made of an aluminum layer because the Schottky barrier bite between the source/drain substrate and the electrode is large. Therefore, in order to obtain an ohmic connection between the source and the drain, an alloy layer containing gold (Au) and germanium (Ge) as main components is often used for the electrode connected to the source and drain.

[Problem that the invention seeks to solve]

As a result of studying an electrode whose main components are gold and germanium, the inventor found that because the melting point of this electrode is as low as about 400°C, it is easily deformed by the heat applied when forming the interlayer insulating film, the final protective film, etc. I found out that it can be put away.

An object of the present invention is to provide a technique for electrically connecting an electrode made of a metal with good heat resistance and conductivity to a semiconductor region.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a compound layer having an energy gap smaller than the energy gap of the compound substrate is provided between a semiconductor region on the surface of the compound substrate and an electrode connected to the semiconductor region, and the electrode is connected to this compound layer.

[Effect]

According to the above-mentioned means, the energy gap between the semi-insulating substrate and the electrode connected thereto is reduced, so that the electrode is made of a metal that has better heat resistance and better conductivity than, for example, an alloy of Au and Ge. It can be used.

〔Example〕

FIG. 1 is a plan view of a MESFET according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line A-A in FIG.
FIG. 3 is an enlarged view of the portion surrounded by the dotted line in FIG. 2. In addition, Figure 1 shows #! of MESFET. In order to make it easier to see the
An interlayer insulating film is not shown.

In FIGS. 1 to 3, reference numeral 1 denotes a semi-insulating substrate made of a compound of gallium (Ga) and arsenic (As).

MESFET has a gate electrode 2 made of a tungsten silicide layer deposited on the surface of a substrate 1, and a channel region provided under the gate electrode 2 on the surface of the substrate 1! Type 1 half region 3. It consists of n" type semiconductor regions 4 which are source and drain regions provided on the surface of both sides of the gate electrode 2 of the substrate 1. On the upper surface of the rl" type semiconductor regions 4 which are the source and drain regions, epitaxial growth is performed. For example, an rI4 type conductive layer 5 made of a compound of gallium (Ga), indium (In), arsenic (As), and antimony (Sb) is provided. This n
The 9-type conductor f6JPJ5 is a buffer layer for ohmically connecting the conductor [i6 made of an aluminum layer connected to the upper surface thereof and the rl'l' conductor region 4, which is a source and train region.

As shown in FIG. 3, the rl'' type conductive layer 5 is constructed by laminating a plurality of layers from the bottom, that is, a conductive layer 51, a conductive layer 52, . . . a conductive layer 5n-□, and a conductive layer 5n. The thickness of each of the conductive layers 52, 52.5t+-t, and 5n is about 1 to several tens of nanometers.

The n''' type conductive layer 1, the n'' type conductive layer 52,...
・The composition of the n4 type conductive layer 5 H+ and the rr type conductive layer 5 is as follows:
I% XGa+-x Asv Sb+-v (0≦
X≦1, O≦Y≦1). Here, X and Y each indicate the composition ratio of each element in the quaternary mixed crystal. bottom layer r
L' type lead 11! An example of the composition of the layer 51 is x=y=
o.

It is 5. That is, Ino * os Gao *
, 5Aso, gs Sbomas. The composition of the second n-type conductive layer 5□ from the bottom is 1, for example, X=Y=
0゜1, that is, I n Oa-s G a o *
sAso*9Sbo, +. The composition of the five r1+ type conductive layers 2-1 is, for example, X=Y=0.90.
That is, In om G.

Gao, +oABo-tosbo, so.The composition of the uppermost rl' type conductive layer 5 is, for example, X=Y=1. That is, it is InSb. In this way, the lower the Q
It contains a large amount of a and As, and a small amount of In and sb. The upper layer contains less Ga and As (and contains more In and sb).

n゛゛semiconductor region 4 and the rl' type conductive layer (X=Y
=0.05), the mismatch in crystal lattice constant is about 1%. Since the thickness of the conductive layer 51 is as thin as 1 to several tens of nanometers, good epitaxial growth is possible even with a lattice mismatch of about 1%. Further, the n゛゛semiconductor region 4 and the n
The energy barrier height of the junction of the ゛-type electromechanical layer is Q,
It is about 1 eV or less. 11° type conductive layer5. (X=Y=
0.05) and n4 type conductive layer 52 (X=Y=0.1
) is about 1%, and the energy barrier height is about 0.1 eV. II' type conductive conductive layer 5-+(
X=Y=0.9) and r1°1° type conductivity% (X=Y=1)
The lattice mismatch between them is about 1%, and the height of the energy barrier is about 0.18V or less. The height of the energy barrier between the conductive layer 51 and the aluminum layer ff1ti6 is about 0°1 eV or less. As described above, the height of the energy barrier between adjacent layers is small, about 0.18 V or less, and can be easily overcome by the energy possessed by carriers at room temperature. Here, if the electrode 6 made of an aluminum layer is directly connected to the n" type semiconductor region 4, the height of the energy barrier between them is about 0.7 eV. In other words, the electric current wA6 is directly connected to the n0 type semiconductor region 4. If the connection is made to the region 4, ohmic connection cannot be obtained.However, as mentioned above, the n° type conductive layer 515□...5
As shown in FIGS. 4 and 5, by intervening 9-1 and 5, electric t! The height of the effective energy barrier between i6 and n' semiconductor region 4 is reduced. here.

Figure 4 shows the energy band structure when the r1° conductor region 4 and the electrode pM6 are directly connected, and Figure 5 shows the energy band structure when the electrode 6 is connected to the rl'' type semiconductor region 4 via the n' type conductive layer 5. The energy band structure of the case is schematically shown in FIGS. 4 and 5.

Ec is the bottom of the conduction band of the ri" type GaAs layer 4, Ev is the top of the valence band of n"1 GaAs4, and E+-
is the Fermi level of the metal of electrode 6, φ. 1 and φ112 are the heights of energy barriers between the electrode metal and the interface of the semiconductor 4 or 6, respectively.

Note that x and y are not limited to the above values. The lower layers, such as the n4-type conductive layers 51 and 52, have more Ga and As, and the upper layers, such as the n4-type conductive layers 5%-1, 51, have more I.
Increase n and sb.

It is sufficient that the difference in crystal lattice between adjacent layers such as those between the cross-shaped conductive layer 5 and 52 is about 1% or less, which satisfies conditions that enable good epitaxial growth. Further, although 5% of the uppermost conductive layer does not contain Ga or As, it may contain Ga and As as long as it can form an ohmic connection with the electrode 6. Furthermore, the number of laminated layers of the conductive layer 5 can be varied in various ways.

As mentioned above, the n4 type conductive layer 51.5□...5, -l
, 5%, it is possible to ohmically connect the electrode 6 made of the aluminum layer to the n4 type semiconductor region 4 which is the source and drain region.

Although not shown in FIGS. 1 to 3, the electrode 6 made of an aluminum layer will not be melted or deformed by the heat applied during the formation of a protective film or the like covering the electrode 6. That is, by using an aluminum layer for the electrode 6, the reliability of the electrode 6 can be improved. Further, the electrode 6 made of an aluminum layer can be formed at a lower cost than the case where the electrode 6 is formed from an alloy of gold (Au) and germanium (Ge). Furthermore, gold (A
To form the electrode 6 with an alloy of u) and germanium (Ge), it must be formed by lift-off, but the aluminum layer can be patterned by etching.

Each of the conductive layers 5I, 5□...5-, -(', 56 can be formed by, for example, MBE (molecular beam epitaxy) method.
, 52...51-1.56, the gate electrode 2 is covered with an insulating film 7 made of silicon oxide film or the like in advance
It is good if it is covered with 1°.In addition, conductive 55t, 5
2...5%-+, an interval approximately enough for mask alignment is provided between 5% and the gate electrode 2. In this implementation area, the conductive i2 is layer 5, that is, the conductive layers 54, 52...5-L-1,
Each of the 5% is formed into a similar rectangular shape, but the pattern is arbitrary. Furthermore, in this example, as shown in FIG. 1, the electrode 6 was formed smaller than the conductive layer 5 by the mask alignment margin, but the electrode 6 was formed larger than the conductive layer 5 so that the periphery of the electrode 6 It may be arranged to reach the upper surface of the semiconductor region 4.

Note that the electrode 6 is not limited to an aluminum layer, but may also be formed of a film of a high melting point metal such as Ti, W, Ta, or Mo, an alloy film thereof, or a silicide film thereof. Along with this.

Gate electrode 2 and electrode 6 can be formed in the same process.

Further, conductive layer 5. In other words, by making the buffer layer n' type, the MESFET shown in FIGS.
As shown in FIG. 6, the n4 type semiconductor region 4 of
It may also be an n-type semiconductor region 3.

That is, the n-type semiconductor region 3 may be formed from the surface of the substrate 1 to which the n-type semiconductor region 5 is connected to the surface to which the gate electrode 2 is connected. Note that FIG. 6 is a sectional view of a MESFET showing a modification of this embodiment.

Furthermore, when the semiconductor region 3 of the ME S FET shown in FIGS. 1 to 3 is a p-type semiconductor region, and the semiconductor region 4 is a p゛゛ semiconductor region, the conductive layer 5 (buffer layer) is doped to 24-type. This allows ohmic connection. This also applies to the MESFET shown in FIG. By the way, A is generally used as an ohmic electrode.
UZn or AuBe is used.

When the substrate 1 is made of InP instead of As.

By making the conductive layer 5 (buffer layer) InPxSb+-X or InAgxPt-x, ohmic connection can be achieved.

When the substrate l is GaP, the conductive layer 5 (buffer layer) G
ax I n+ +X Pv Sb+-v or Qa
By setting x I nl -x ASy Pr-v, ohmic connection can be established.

Next, FIG. 7 shows an example in which the n4 type conductive layer 5 shown in FIGS. 1 to 3 is applied to a heterojunction FET.

In FIG. 7, l is a semi-insulating GaAs substrate. 8 is a non-doped GaAs layer, 9 is an n-type GaAl
It is an As layer. 10 is an n-type GaA layer which is an i-type GaAs layer.
It is connected to the upper surface of the lAs layer 9. This n-type Ga A
n shown in Figures 1 to 3 on the top surface of s 7110.
"" type conductive conductive layer 5, that is, the buffer layer and Iy! A 09 type conductive layer 5 having a U-like composition is connected. An effective buffer layer between the electrode 6 made of an aluminum layer and the n-type GaAIAs layer 9 is composed of n°-type conductive MS and n4-type Ga
This is an As layer 10.

In addition, the rl type conductive fi layer 5 (
The buffer layer) can also be applied to a heterojunction bipolar transistor, as shown in FIG. In FIG. 8, 1 is a semi-insulating GaAs substrate, 11
12 is a collector region made of n-type GaAs, and 12 is a p-type GaAs collector region.
Base region made of AlAs, 14 is n-type Ga A
The emitter region consists of s. N4 type conductor 1 on the upper surface exposed from the base region 12 of the collector region 11! J!
5 (buffer layer), and an electrode 6 made of an aluminum layer is connected to the surface of this n''' type conductive layer 5. The composition of the rl'' type conductive layer 5 is shown in FIGS. 1 to 3. This is similar to the n'''''' wire N15 shown.

P'''''aAs 13 is connected to the upper surface of the base region 12 exposed from the emitter region 14, and a p4 type conductor ff11a5 (buffer M) is connected to this upper surface. The composition of the P conductive layer 5 is that of the P0 type conductive layer 5 shown in FIGS. 1 to 3. An electrode 6 made of an aluminum layer is connected to the upper surface of the P11 type conductor 5. That is, the effective buffer layer between the electrode 6 and the base region 12 is the p' type GaA layer 13 and the PI type conductive layer 5.

A p° type layer conductor layer 5 (buffer layer) is connected to the upper surface of the emitter region 14, and an electrode 6 made of the p+ type layer conductor layer 5 and an aluminum layer is connected thereto.

The n-type electroconductive layer 5 (buffer layer) shown in FIGS. 1 to 3 can also be applied to a laser device as shown in FIG. 9. In FIG. 9, reference numeral 6 denotes an electrode made of an aluminum layer, and is connected to the n° type buffer layer 16. The composition of the rl' type buffer layer 16 is similar to that shown in FIGS. 1 to 3. n1 type buffer layer 1
The surface opposite to the side to which the electrode 6 of 6 is connected is an n-type Q
It is connected to the aA s board 17. 18 is n-type Ga
A I A s layer.

19 is a p-type Ga As layer, 20 is a P-type Ga As layer
The IAs layer 21 is p-type GaAsT! It is j. n
A laser beam is generated at the interface between the type Ga A IAs MI 18 and the p-type GaAs layer 19. 22 is P4
type buffer layer, connected to P4 type GaAsff21, P9 type buffer layer 7 M 22 and p'' Ga A s
An electrode 6 made of an aluminum layer is connected to the surface of the MIF 21 opposite to the bonding surface. P4 type buffer layer 22
has the same composition as the n-type conductive layer 5 shown in FIGS. 1 to 3, and is made into a 20-type conductive layer.

According to the new technology disclosed in this application, the following effects can be obtained.

(1) A conductive layer made of a compound having an energy gap smaller than the energy gap of the substrate is interposed between the semiconductor region on the surface of the compound substrate and the W1 pole made of an aluminum layer or the like connected to this semiconductor region. As a result, the substantial energy gap between the semiconductor region and the electrode becomes smaller, so that a good ohmic connection between the semiconductor region and the electrode can be achieved.

(2) According to (1) above, it is possible to use a metal with good heat resistance such as an aluminum layer for the electrode to be connected to the semiconductor region, so that the electrode may be melted or deformed due to heat during the formation of the protective film, etc. It is possible to prevent this and improve the reliability of the electrode.

The present invention has been specifically explained above using examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, the conductive layers 51.52...5--r, 5. ?
− for each of GaX I n r −x As (
It may also be a compound layer represented by 0≦X≦1).

That is, sb in the above embodiment may be replaced with As. In this case, the conductive layer 5n, which is the uppermost buffer layer, is a compound layer containing only In and As.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, since the energy gap between the semi-insulating substrate and the electrode connected thereto becomes small, a metal having better heat resistance and better conductivity than, for example, an alloy of Au and Go can be used for the electrode.

[Brief explanation of drawings]

FIG. 1 is a plan view of a field effect transistor. The second is a sectional view taken along line A--A in FIG. 1, and FIG. 3 is an enlarged view of the portion surrounded by the dotted line in FIG. 4 and 5 are energy band diagrams; FIG. 6 is a sectional view of a MESFET with n-type source and drain regions; and FIG. 7 is a sectional view of a heterojunction transistor. FIG. 8 is a sectional view of a heterojunction bipolar transistor, and FIG. 9 is a perspective view of a laser element. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Gate electrode, 3, 4...Semiconductor region, 5.5A, 5B, 5n-+, 5n, 10.
13゜16.22... Conductive layer (buffer layer), 6...
・Electrode (aluminum 1m>, 7...insulating film, 8・
...Non-doped GaAs region, 9-n type GaAl
As region, 11...n type collector, 12...P type base, 14...n type emitter, 17...n type Ga
A s substrate, 18...n type Ga A I A s
layer, 19-p-type GaAs layer, 20'''p-type GaA
IAs layer, 21...PI type GaAs layer. Figure 1 Figure 2 Figure 3 S/ Whistle 4 Figure/+' Figure 5 c 5 4 Figure 6 Figure

Claims (1)

[Claims] 1. A compound layer having an energy gap smaller than the energy gap of the compound semiconductor substrate is provided between a semiconductor region on the surface of the compound semiconductor substrate and an electrode connected to the upper surface of the semiconductor region. A semiconductor device characterized by: 2. The compound layer between the semiconductor region and the electrode is composed of a plurality of layers, and the plurality of compound layers contain the same element as any of the elements constituting the compound semiconductor substrate. A semiconductor device according to claim 1. 3. The electrode is made of titanium, molybdenum, tungsten,
Claim 1, characterized in that the electrode is made of a high melting point metal such as tental, a silicide of the high melting point metal, or a metal with good heat resistance such as an aluminum layer.
1. Semiconductor device described in Section 1.