JPS62179043A - Transmission control unit - Google Patents
Transmission control unitInfo
- Publication number
- JPS62179043A JPS62179043A JP2163686A JP2163686A JPS62179043A JP S62179043 A JPS62179043 A JP S62179043A JP 2163686 A JP2163686 A JP 2163686A JP 2163686 A JP2163686 A JP 2163686A JP S62179043 A JPS62179043 A JP S62179043A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- transmission
- circuit
- time
- reception
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Information Transfer Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、伝送制御装置、特にバス方式による信号伝送
路に接続された伝送制御装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a transmission control device, and particularly to a transmission control device connected to a signal transmission path using a bus system.
〔従来の技術）
従来の伝送制御装置に備えられた送信回路及び受信回路
は各々の専用の信号伝送路に接続されることで送信回路
からの送信信号は受信回路に影習を与えることはなかっ
た。[Prior art] The transmitting circuit and receiving circuit provided in a conventional transmission control device are connected to their own dedicated signal transmission paths, so that the transmitted signal from the transmitting circuit does not affect the receiving circuit. Ta.
しかし、バス方式による信号伝送路を用いた方式では送
信回路及び受信回路は共通の信号伝送路に接続され、送
信回路から出力された送信信号はそのまま、自分、の受
信回路へ入力されることになり、伝送制御回路では、送
信回路の処理と自分の出した送信信号による受信回路の
制御をしなければならず、制御効率の低下を及ぼす欠点
があった。However, in a method using a bus-based signal transmission path, the transmitting circuit and the receiving circuit are connected to a common signal transmission path, and the transmitted signal output from the transmitting circuit is inputted as is to its own receiving circuit. Therefore, the transmission control circuit has to process the transmitting circuit and control the receiving circuit using the transmitting signal it outputs, which has the disadvantage of reducing control efficiency.
また、信号伝送路長が長くなることにより、送出した送
信信号が信号伝送路の端から反射して、その反射信号が
時間延長を伴なって自分の伝送制御回路の受信回路に入
力されると云った反射信号による誤動作を起こす欠点が
あった。In addition, as the length of the signal transmission path increases, the transmitted signal is reflected from the end of the signal transmission path, and the reflected signal is input into the receiving circuit of the own transmission control circuit with an extended time. This has the drawback of causing malfunctions due to the reflected signals mentioned above.
〔目 的］
本発明は以上の点に鑑みてなされたもので、自装置から
送出した信号による自装置への肥りを除去し、安定した
信号伝送を可能とする伝送制御装置を提供することを目
的とする。[Objective] The present invention has been made in view of the above points, and an object thereof is to provide a transmission control device that eliminates the burden on the own device due to signals sent from the own device and enables stable signal transmission. purpose.
以下、本発明を好ましい実施例を用いて説明する。 The present invention will be explained below using preferred examples.
第１図は本発明による伝送制御装置の一実施例の概略ブ
ロック図である。FIG. 1 is a schematic block diagram of an embodiment of a transmission control device according to the present invention.
第１図において、１は伝送制御回路、２は送信回路、３
は受信回路、４は送信許可信号発生回路、５は時間信号
発生回路、６は送信用ゲー１−１７はトライバ（増巾器
）、８は受信用ケート、９はレシーバ（増巾器）″、１
０は伝送路である。In FIG. 1, 1 is a transmission control circuit, 2 is a transmission circuit, and 3 is a transmission control circuit.
4 is a reception circuit, 4 is a transmission permission signal generation circuit, 5 is a time signal generation circuit, 6 is a transmission gate 1-17 is a driver (amplifier), 8 is a reception gate, 9 is a receiver (amplifier)'' ,1
0 is the transmission path.
伝送制御回路１から、送信開始信号１１が送信信号発生
回路４に送られると、送信許可信号発生回路４は送信許
可信号１２を発生する。送信許可信号１２は送信回路２
を動作可能状態にする。送信回路２は伝送制御回路１か
らの他装置へ伝送路１０を介して送信すべきデータ信号
１３を受け、伝送路１０による伝送に適した伝送信号１
４に変換して送信用ゲート６及びドライバ７を介して伝
送路１０に送出する。When the transmission start signal 11 is sent from the transmission control circuit 1 to the transmission signal generation circuit 4, the transmission permission signal generation circuit 4 generates a transmission permission signal 12. The transmission permission signal 12 is sent to the transmission circuit 2
make it operational. A transmission circuit 2 receives a data signal 13 to be transmitted from the transmission control circuit 1 to another device via a transmission line 10, and transmits a transmission signal 1 suitable for transmission via the transmission line 10.
4 and sent to the transmission line 10 via the transmission gate 6 and driver 7.
送信許可信号発生回路４からの送信許可信号１２により
送信ゲート６はイネーブル状態にされており、これによ
り、送信回路２の伝送信号１４が１−ライハフへ伝達さ
れる。The transmission gate 6 is enabled by the transmission permission signal 12 from the transmission permission signal generation circuit 4, so that the transmission signal 14 of the transmission circuit 2 is transmitted to the 1-life.
また、送信許可信号１２は受信用ゲート８にも送られ、
受信用ゲート８を禁止状態にすることで、トライバ９か
らの受信信号１５の受信回路３への入力を禁止する。こ
れにより、データの送信中に送信回路２から出力された
伝送信号１４が、受信回路３に入力されるのが禁止され
る。The transmission permission signal 12 is also sent to the receiving gate 8,
By setting the reception gate 8 to a prohibited state, input of the reception signal 15 from the driver 9 to the reception circuit 3 is prohibited. As a result, the transmission signal 14 output from the transmitting circuit 2 during data transmission is prohibited from being input to the receiving circuit 3.
さらに、送信許可信号１２は所定時間計時動作するタイ
マ回路を有した時間信号発生回路５に接続されており、
時間信号発生回路５は送信許可信号１２の終了時から一
定時間の時間信号１６を発生する。Further, the transmission permission signal 12 is connected to a time signal generation circuit 5 having a timer circuit that operates to measure a predetermined period of time.
The time signal generating circuit 5 generates a time signal 16 for a certain period of time from the end of the transmission permission signal 12.
時間信号１６は受信用ゲート８に送られ、前述した送信
許可信号１２により受信信号１５の受信回路３への入力
を禁止すると同様に、送信許可信号１２に連続して時間
信号１６により受信信号１５が受信回路３へ入力するこ
とを禁止する。これにより、自装置の送出信号の反射波
の受信を防止でき、反射波による影うを除去できる。The time signal 16 is sent to the reception gate 8, and in the same way that the above-mentioned transmission permission signal 12 prohibits input of the reception signal 15 to the reception circuit 3, the reception signal 15 is is prohibited from being input to the receiving circuit 3. This makes it possible to prevent reception of reflected waves of signals transmitted by the own device, and to eliminate shadows caused by reflected waves.
以上に述べた様に、送信状態を表わす送信許可信号に加
えて連続した禁止信号の発生により受信信号の受信回路
への入力を一定時間禁止することで、バス方式における
反射信号が受信回路へ及ぼす悪影響及び誤動作を防止す
ることができる。As mentioned above, by inhibiting the input of the received signal to the receiving circuit for a certain period of time by generating a continuous prohibition signal in addition to the transmission permission signal that indicates the transmission state, reflected signals in the bus system can be prevented from being input to the receiving circuit. Adverse effects and malfunctions can be prevented.
以上説明した様に、本発明によると、信号送出中及び信
号送出から一定時間は、受信回路への信号入力を禁止す
るので、自装置の送出した信号による不都合を除去し、
良好な信号送出を可能とするものである。As explained above, according to the present invention, since signal input to the receiving circuit is prohibited during signal transmission and for a certain period of time after signal transmission, the inconvenience caused by the signal transmitted by the own device is eliminated.
This enables good signal transmission.
第１図は本発明を適用した伝送制御装置の一実施例を示
す図であり、ｌは伝送制御回路、２は送信回路、３は受
信回路、４は送信許可信号発生回路、５は時間信号発生
回路、６は送信用ゲート、７はドライバ（増１］器）、
８は受信用ゲート、９はレシーバ（増巾器）、１０は伝
送路である。FIG. 1 is a diagram showing an embodiment of a transmission control device to which the present invention is applied, where l is a transmission control circuit, 2 is a transmission circuit, 3 is a reception circuit, 4 is a transmission permission signal generation circuit, and 5 is a time signal. Generation circuit, 6 is a transmission gate, 7 is a driver (amplifier 1),
8 is a receiving gate, 9 is a receiver (amplifier), and 10 is a transmission line.
Claims (1)
路を備えた伝送制御装置において、送信回路から信号の
送出中は受信回路への信号入力を禁止するとともに、該
送信回路からの信号の送出が終了した後の一定時間中も
該受信回路への信号入力を禁止することを特徴とする伝
送制御装置。In a transmission control device equipped with a transmitting circuit and a receiving circuit connected to a signal transmission path using a bus method, inputting signals to the receiving circuit is prohibited while signals are being sent from the transmitting circuit, and the sending of signals from the transmitting circuit is prohibited. A transmission control device characterized in that signal input to the receiving circuit is prohibited for a certain period of time after the end of the transmission.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2163686A JPS62179043A (en) | 1986-02-03 | 1986-02-03 | Transmission control unit |
| US07/009,464 US4839908A (en) | 1986-02-03 | 1987-01-28 | Transmission control apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2163686A JPS62179043A (en) | 1986-02-03 | 1986-02-03 | Transmission control unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62179043A true JPS62179043A (en) | 1987-08-06 |
Family
ID=12060555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2163686A Pending JPS62179043A (en) | 1986-02-03 | 1986-02-03 | Transmission control unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62179043A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007072684A1 (en) * | 2005-12-22 | 2007-06-28 | Matsushita Electric Industrial Co., Ltd. | Interface circuit |
-
1986
- 1986-02-03 JP JP2163686A patent/JPS62179043A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007072684A1 (en) * | 2005-12-22 | 2007-06-28 | Matsushita Electric Industrial Co., Ltd. | Interface circuit |
| JPWO2007072684A1 (en) * | 2005-12-22 | 2009-05-28 | パナソニック株式会社 | Interface circuit |
| JP4728352B2 (en) * | 2005-12-22 | 2011-07-20 | パナソニック株式会社 | Interface circuit |
| US8027389B2 (en) | 2005-12-22 | 2011-09-27 | Panasonic Corporation | Interface circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR930010931A (en) | Active sound player and control unit for controlling it | |
| JPS6412426B2 (en) | ||
| JPS62179043A (en) | Transmission control unit | |
| JPS58201440A (en) | Loop mode transmission system | |
| JP2767990B2 (en) | Microprocessor control method | |
| JPS6479850A (en) | Effective using method for bus | |
| JPS59220835A (en) | Audio response unit | |
| JPS6336177B2 (en) | ||
| JPH0342757B2 (en) | ||
| JP3085403B2 (en) | Programmable controller | |
| JPS59111445A (en) | Data transmission system | |
| JP2762653B2 (en) | Automatic phase adjustment method in wireless calling system | |
| JPH01149635A (en) | Data transmitting system | |
| JPS6328376B2 (en) | ||
| JPS57123750A (en) | Signal transmitting and receiving device | |
| JPH03159428A (en) | Communication control equipment | |
| JPS6037876A (en) | Control signal detecting system in facsimile | |
| JPH0295055A (en) | Data line loopback system | |
| JPH02125539A (en) | Drop insert system | |
| JPS61223963A (en) | Connection circuit between master and slave device | |
| JPS62107553A (en) | Address machine number setting control method | |
| JPS599737A (en) | Controlling circuit for use of bus | |
| JPH0368422B2 (en) | ||
| JPS5875230A (en) | Input and output control circuit | |
| JPS62285554A (en) | Transmitter |