JPS62178168A - Low input-voltage converter - Google Patents

Abstract

PURPOSE:To enable oscillation operation from supply voltage of several mV at a minimum by using an FET at an intermediate operating point, which is not at ON and OFF on non-bias state, and a transformer having a large turn ratio. CONSTITUTION:When a resistance value between a drain and a source in an N channel MOSFET 1 at an intermediate operating point, which is not at ON and OFF on non-bias state, alters, currents between power supplies 5, 6 change, and voltage is generated in a primary coil 2. The voltage is amplified in proportional to the larger turn ratio of the primary coil 2 and a secondary coil 3, and applied between a gate and the source in the MOSFET 1. When the turn ratio of the primary coil 2 and the secondary coil 3 are brought to approximately 1:200, a device is oscillated at 5mV supply voltage. The voltage of the secondary coil 3 is rectified and smoothed by a rectifier 7 and a capacitor 8, and applied to load 11.

Description

[Detailed Description of the Invention] (A) Industrial Application Field This invention is useful for extracting a voltage that allows normal semiconductor circuits to operate from a power source with low electromotive force, and for obtaining a signal from a current detector in which voltage drop should be avoided as much as possible. Insulating and transmitting, etc.
The present invention relates to a solid-state converter that converts extremely low voltage into a form that can be easily used as a power source or signal.

(a) Conventional technology When boosting or insulating from a DC power supply, a 1.U oscillator is usually used. However, in the conventional solid-state circuit system, 0.
It does not work with only voltages below 3V. This is a minimum of 0.3■ between the base and emitter even for germanium transistors.
This is because a higher voltage is required, which is approximately 0.55 V or higher for silicon transistors. Furthermore, even if FETs are used, conventional circuit systems will not operate at low voltages because the amplification level will be low.

(1) Problems to be Solved by the Invention The object of the present invention is to take out high voltage from a power supply of 0.3 V or less, which does not work with ordinary semiconductors, and to transmit it in an insulated manner.

(1) Means for solving the problem In the present invention, the FET is at an intermediate operating point that is neither ON nor OFF when there is no bias, and the turns ratio of the negative coil and the secondary coil is set to a large value of 1:10 or more. By using a transformer, oscillation operation can be performed from a power supply voltage of at least several millivolts.

(e) Effect FIG. 1 is an example of a booster circuit using the present invention.

When the resistance value between the drain and source of the N-channel MOSFET I changes, the current between the power supplies 5 and 6 changes, and a voltage is generated in the negative coil 2. This voltage is amplified in proportion to the turns ratio of the secondary coil 2 and the secondary coil 3.
It is applied between the gate and source of E T I. M OS
Since the gate input impedance of FET is capacitive, using a large turns ratio does not directly result in losses.

Also, since the gate has no rectifying effect, no other parts are required. Select the most suitable element for MOSFET1, and set the turns ratio to l.
: If it is about 4-200, it will oscillate at a power supply voltage of 5 mV. If the power supply voltage is increased, the voltage generated in the secondary coil 3 will also increase proportionally, and the operable range is until the gate breakdown voltage is reached.

In Fig. 1, the series voltage of the primary coil and secondary coil is connected to the rectifier 7.
It is rectified and returned to DC voltage. In this circuit, the input voltage is 0. IV, when the load resistance is InkΩ, an efficiency of 50% or more is obtained.

FIG. 2 shows a circuit intended for insulation. In this case, the problem is not the conversion efficiency or boost ratio, but the linearity of the turnout. The power supply terminals 5-6 operate as input terminals for DC signal voltage. Linearity between this voltage and the voltage generated in the tertiary coil 4 is within 0.1% when the input voltage is 10 mV or more.

Figure 3 shows an isolated voltage boosting circuit, and the operation is shown in Figure 1.
It is the same as that of

FIG. 4 shows a push-up circuit with a push-pull configuration, in which both the secondary coil and the secondary coil are connected to the drain of the MOS FE'1'. As a result, the operating point shifts in the positive direction by the amount of the power supply voltage, and the ON resistance decreases, but the linearity deteriorates.

Push-pull operation can handle more power.

FIG. 5 shows a circuit using a JFET instead of a MOSFET, and a resistor 13 for limiting gate current and a capacitor 14 for bypassing an AC signal are added. J.F.E.
When i' is used, it is advantageous that the ON resistance is low at low voltage, but it is difficult to increase the efficiency because it cannot completely turn OFF. Furthermore, even if the gate voltage amplitude becomes large, the ON resistance does not decrease much, so the range of applications is limited compared to MOSFETs. In this case, it is also possible to use the resistor 13 as a load resistor, and it can be configured with the least number of parts. The capacitor 14 operates for smoothing.

[Brief explanation of drawings]

Figure 1 is a booster circuit, Figure 2 is an isolated circuit, Figure 3 is an isolated booster circuit, Figure 4 is a push-pull configuration booster circuit, Figure 5 is a JP
The oscillation circuit part using ET is shown. 1 is FE'l', 2 is primary coil, 3 is secondary coil, 4
is the tertiary coil, 5 is the positive power supply terminal, 6 is the negative power supply terminal, 7 is the rectifier, 8 is the smoothing capacitor, 9 is the positive output terminal, 10 is the negative output terminal, 11 is the load, 12 is the AC output terminal, 13 is the Resistor for gate current limit, ■4 is bypass capacitor. Patent applicant Nakano iE Kuchikuchi 1
Figure 2 Figure 5

Claims (1)

[Claims] A converter that boosts or isolates a DC voltage of 0.3V or less by using a transformer with a large turns ratio and a FET that is conductive when no bias is applied.