JPS62177798A - semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce a steady power consumption by allowing an activation circuit equipped with a fuse not to supply a current to a ROM storing the address of a defective cell when an auxiliary cell is not used. CONSTITUTION:Unless a cell is a memory cell array is not replaced with the auxiliary cell, and has no defect to disconnect all fuses F0-F9 in an address storing ROM1 for a defective cell, the fuse F of the activation circuit 2 remains disconnected. In that state, the node N1 of the circuit 2 becomes H, and transistors Q12 and Q11 are turned on and off, respectively, bring a node N2 to L. Thus a transistor Q13 is turned off, and no current is supplied to the ROM1 through the transistor Q13, whereby a steady power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device having spare cells, and particularly to a ROM for storing defective addresses thereof.

C. Prior Art] A memory that has redundant spare cells in addition to the regular cell array and replaces any defective cells that have caused a hardware failure in the cell array with the spare cells can greatly improve manufacturing yields. can. Although the yield improves as the process matures, it is usually poor in the early stages, and the effect of redressing this problem with spare cells is significant. Most spare cells have one to two lines each in the word line and column line directions, but some have as many as four to eight spare cells each. The larger the number of built-in spare cells, the greater the number of defective cells that can be repaired and the higher the yield, but this increases complexity and wastes a normal memory chip, so it is normal to have a small number of spare cells. .

To use the spare cell, it is necessary to store the address of the defective bit, and a ROM (read-only memory) as shown in FIG. 4 is used for this purpose. This ROM consists of a fuse F made of polycrystalline silicon or the like and a load transistor Q connected in series between the power supplies Vcc and Vss in the number of address bits multiplied by the number of spare cells. Each bit of the address is designed to represent 1 or 0. In the memory of [IM Biff], the address of the defective cell is A o = A 9 of 10 in both rows and columns.
Since it is expressed in bits, the ROM for one spare cell is A
.

It consists of 10 elements: fuse Fo=F9 for ~A9, load 1-transistor Qo=Q9, and if two spare cells are provided each in the word line and column line directions, four groups of such ROMs are provided.

[Problem that the invention seeks to solve]

By the way, as memory manufacturing technology matures, the rate of non-defective products increases, resulting in unused spare cells and defective address memory ROs.
M increases. The defective address storage ROM in FIG.
If you do not want to memorize the defective address, all fuses Fo=
Since F9 remains connected, such a chip has the disadvantage that more constant DC current flows than a chip using a spare cell.

In order to improve this point, the present invention attempts to prevent direct current from flowing into the ROM for storing defective addresses in a chip that does not use spare cells.

[Means for solving problems]

The present invention provides a semiconductor device (Q device) which includes a spare cell in addition to a memory cell array and uses the spare cell to replace a defective cell in the cell array. It is equipped with a ROM and a fuse that is cut or uncut depending on whether the spare cell is used or not, and supplies read current to the ROM using the spare cell, and supplies read current to the ROM not using the spare cell. The device is characterized in that it includes an activation circuit that does not supply power.

[Effect]

A fuse-cut ROM that stores the address of a defective cell.
The defective cell address is obtained at the wafer probe test stage, and the fuse is selectively cut (defective address writing) using this address, but this only occurs when there is a defective cell on the chip, and when there is no defective cell. RO in chips
No M write is performed and all fuses in the ROM remain unbroken. Therefore, the ROM is in a state where a read current flows through all bits, but the current does not flow unless the activation circuit that supplies the read current to the ROM supplies the read current. This is determined by the use of spare cells/
The circuit configuration is such that a read current to the ROM is supplied only when the fuse is written to be unused, and the use of a spare cell is written to the fuse, specifically, when the fuse is disconnected. In this way, the steady current consumption of a chip that does not use spare cells is lower than that of a chip that uses spare cells, making it possible to make a memory suitable for applications where a small steady current is desired.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which symbol 2 represents a ROM for storing a defective address similar to that shown in FIG. 4, and 2 represents an activation circuit for supplying a read current thereto.

The activation circuit 2 includes an activation fuse F, and a depletion type load MOS transistor QIO is connected in series with the activation fuse F to form a 1-bit fuse-cut type ROM. This has the same configuration as each bit in ROMI, and if fuse F is not disconnected, node N1 is at H (high) level, close to Vcc level, but if fuse F is disconnected, node N1 is close to Vss level. Shikuro)
become the level. The depletion type load MO3) transistor Qll and the enhancement type drive MOS transistor Q12 constitute an EZD type inverter that inverts the level of the node N5. Q13 is an enhancement type MOS transistor for output connected as a source follower.
Drives the line l corresponding to the power line Vcc of ROMI. That is, in the conventional circuit of FIG. 4, the ROM is directly connected to Vcc, but in FIG. 1, it is connected via the transistor Q13.

When writing a defective address to ROMI, the fuse Fo=Fs is selectively cut with a laser, or a high voltage is applied to the pad P, and the cutting transistor Qo',...
... is installed and turned on, causing an overcurrent to flow through the fuse and blowing it out. The same applies to the fuse F in the two examples of activation circuits, and if it is to be blown by overcurrent, a transistor QIO for cutting is provided. In any case, when the activation fuse F is cut, node N1 goes high and node N2 goes high.
Then, the source N3 of the transistor Q13 is connected to Vcc-
A voltage vth is generated (vth is the enhancement type MO3I-Landisk threshold), which is applied to ROMI through line β, causing a read current to flow to the unfused bit in ROMI. As a result, a binary 10-bit defective cell address Ao''Aq written in advance is output to each connection point between the fuse and the load transistor.Although not shown, the same applies to other defective addresses.

If the activation fuse F is not cut, the transistor QI3 will be cut off because the node N1 is at H1 and the node N2 is at L, and the line 13 will not become a current supply line to ROMI. Therefore, no current flows through the ROMI, and if the spare cell is not used, the ROMI does not consume any current and is the same as if it were not present.

Note that although current (current for one bit of ROMI) flows through the activation fuse F, since this prevents current from flowing to ROM1, the current reduction effect is large. That is, 1
Even when an M-bit memory (RAM) has two spare cells, a ROM of 20 pins in total, 10 bits in the row direction and 10 bits in the column direction, is required to store the defective address. Therefore, if the activation circuit 2 is shared, the DC current flowing through the defective address memory IQ system when the spare cell is not used will be reduced to 1/2.
It can be reduced to 20. This is a case where activation circuit 1 is shared by multiple cells (each defective cell address), but activation circuit 2
1/1 even if it is provided individually for each defective cell address without being shared.
Since the current consumption can be reduced to 0, the effect of reducing current consumption is sufficient.

FIG. 2 is a circuit diagram showing another embodiment of the present invention, in which the node N
The difference from FIG. 1 is that transistors Q14 to QI6 for clamping MO3) are used. These transistors are diode-connected and clamp the H level of node N2 to 3 V th (as Vss-OV). In this way, the potential of node N3 when transistor QI3 is on becomes 2 V th, which is lower by vth due to node N2.
Reduces ROM current consumption and also reduces ROMI fuse Fo-
The voltage applied after cutting F9 is reduced, making it difficult for resupply to occur due to melting of the cutting point.

The activation circuit 2 of the present invention has an n-channel M through which a special current flows.
CMOS with lower constant current consumption than OS memory
It is more effective in type memory. Figure 3 is C
This is a circuit diagram of the main part of activation circuit 2 suitable for MOS, Qp, Q
n is an MO3I-transistor of each p and n channel constituting a CMOS inverter. Node N1. N2 is the first
2. Corresponding to that of FIG.

When the activation circuit 2 is provided, activated ones (use of spare cells) and non-activated ones are stationary (standby).
Although the current will be different, there are memory applications that require a small standby current and others that do not place importance on it, so it is best to be able to use it according to the application.

By the way, there is a distinction between products that use spare cells and those that do not.

〔Effect of the invention〕

As described above, according to the present invention, an activation circuit is provided to supply a read current to a ROM that records (and Q) a defective address in a memory having a spare cell, and the fuse in the activation circuit is cut. Since the read current is supplied to the chip in which the fuse remains, the read current is not supplied to the chip in which the fuse remains, which has the advantage of reducing the steady current consumption of the chip that does not supply the read current, that is, the chip that does not have a defective cell.

[Brief explanation of drawings]

A circuit diagram showing each embodiment of the present invention in FIGS. 1 and 2,
FIG. 3 is a circuit diagram of a main part showing a modification of the present invention, and FIG. 4 is a circuit diagram of a conventional ROM for storing defective addresses. In the figure, 1 is a ROM for storing defective addresses, Fo to F9 are address setting fuses, 2 is an activation circuit, and F and its activation fuse.

Claims (1)

[Claims] In a semiconductor memory device that includes a spare cell in addition to a memory cell array, and is used by replacing a defective cell in the cell array with the spare cell, a fuse-cutting ROM that stores an address of the defective cell, and a ROM for storing the address of the spare cell are provided. An activation circuit is provided with a fuse that is cut or uncut depending on whether it is used or not, and supplies a read current to a ROM using a spare cell, and does not supply a read current to a ROM that does not use a spare cell. A semiconductor memory device comprising: