JPS62176157A - Integrated electronic device and manufacture of the same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing integrated circuits. More specifically, this invention is a complementary engraving vrkW1 compound semiconductor (0M
Regarding the design of O8).

BACKGROUND OF THE INVENTION Current methods of manufacturing integrated circuits, in which components are formed in a semiconductor substrate horizontally along the surface of a semiconductor substrate, have the disadvantage of reducing the dimensions of the devices thus formed. We are approaching a limit that is difficult to overcome. Photolithography methods are limited by the fringing effect of ultraviolet light.
Closely spaced horizontal field effect transistors are increasingly prone to latch-up. It is therefore an object of the present invention to provide a method to avoid such problems.

One solution developed for discrete field effect transistors is to use a vertical tfA structure. An example is 1
8M Technical Disclosure, Volume 22, Volume 8B
(January 1980 issue), a paper by Earl Channell entitled “Vertical FET Random Access Using Deep Trench Isolation”
679,663, filed December 7, 1984. However, conventional methods for manufacturing vertical transistors are applicable only to one transistor of one selected conductivity type. For this reason, it is difficult, if not impossible, to use OMO3, which has low power consumption and a small logic parallel arrangement q method, using conventional vertical transistor manufacturing methods.

Means and actions for resolving problems One embodiment of the invention includes a vertical inverter.

A layer of P-type material is formed on the surface of the N-type substrate, followed by an N-type layer, a P-layer, an N-type layer, and a P-type layer. (Of course, it is within the scope of this invention to use different doping types.) Trenches are then etched along one side of the stack thus formed to form connectors to the central P+ and N+5. Another trench is formed where the gate insulator and goo 1- are to be formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed. Another embodiment of the invention is a logic NOR gate circuit using the interconnect points available in the vertical inverters described above.

EXAMPLE FIG. 1A is a simplified side view showing the initial processing steps for manufacturing an electronic device. Epitaxial layers 2 to 6 are manufactured on the surface of the substrate 1 using, for example, a molecular beam epitaxial method. Using such a method, a very sharp transition between N-type and P-type doping materials can be created. For example, using current methods, P-type layer 2
may be approximately 2,000 to 5,000 thick;
The thickness of the N layer 3 may be between 1,000 and 2,000. The thickness of the P layer 4 may be from 1.000PJ to 2.000PJ, and the thickness of the N layer 5 may be from 2.000 to 5.0PJ.
00 people, and the thickness of the P+10 layer is approximately 1,000 to 2,000 people. Of course, it is within the scope of this invention to make each layer thinner or thicker than this. The thickness of these layers determines, among other things, the channel length of the transistor.

In this example, the channel length of the N-channel transistor is determined by the thickness of layer 2, and in this example, the channel length of the P-channel transistor is determined by the thickness of layer 5.
determined by the thickness of

On the surface of the P layer 6, a mask layer 7 is formed of a suitable masking material and patterned using commonly known photolithography methods. Mask layer 7 is used during the etching process to produce the trenches, as shown in FIG.

Trench 8 is manufactured with two purposes in mind. 1
The second purpose is to create an interconnect layer between vertical inverters, as will be explained in more detail below. The second purpose is to provide isolation between vertical inverters made as described below.

Masking the separation region 20 (shown in plan view in FIG. 2),
A region completely filled with silicon dioxide is created in the trench 8. As shown in FIG. 1C, a silicon dioxide layer 9 is deposited on the surface of the structure of FIG. 1B using, for example, chemical vapor deposition.
form. Etch back the silicon dioxide layer 9,
Silicon dioxide isolation regions 20 (FIG. 2) are provided which fill trenches 8 in areas where particular vertical inverters are to be electrically isolated from each other. In other areas of the integrated circuit, silicon dioxide layer 9 is etched back. , a plug 10 of silicon dioxide is provided as shown in FIG. However, the tungsten in layer 11 may be replaced by other conductive materials.An advantageous property of the material that replaces tungsten is that it is conformal, meaning that the surface shape of the underlying layer is the same as the surface shape of the upper layer. This property avoids voids between the deposited material and the surface it is deposited on, which is a particular problem when depositing wrenches. After this, the masking layer 7 is removed and a masking layer 13 is formed on the surface of the structure of FIG. 1D.

Mask layer 13 is used to mask the etching process used to create trench 14, as shown in FIG. 1E.

After this, the structure shown in FIG. 1E is subjected to a thermal oxidation process, and the structure shown in FIG.
A silicon dioxide layer 15 is formed as shown in the figure. This step should be done to ensure adequate gate insulation for the vertical inverter (but not to over-diffusion into the dopant 1 into layers 2-6, destroying the clarity of the vertical transistors). Do not pay attention (lJ must. After this, n
A tungsten gate 16 is formed in trench 14 using the trench fill and etch back method described for layer 9 in layer 1 . Appropriate interconnections are then made on the surface of the structure of FIG. 1F, as shown in FIG. 1G.

Tungsten gate 16 serves as input and output connection 17i8, as shown in FIG. 1G. A positive voltage is applied to the P upper layer 6 and a ground voltage is applied to the substrate 1 to form a vertical complementary carved metal amalgamated semiconductor inverter. a P+ layer 6 in which a P-channel transistor acts as a source;
It is formed by a P soil layer 4 acting as a drain and a N layer 5 serving as a channel region. The gate of the P-channel A7 channel transistor is formed by a tungsten gate 16. N-channel A7 channel transistor with N+ layer 3 acting as train and N layer 3 acting as source.
It is formed by a daughter substrate 1 and a P layer 2 which becomes a channel region. The gate of the N-channel transistor is formed by a tungsten gate 16.

The dimensions of the tungsten gate 16 and the lateral constraints on the stack of transistors formed by layers 2-6 and interconnect region 11 are imposed by the photolithography method used to fabricate this embodiment of the invention. . Second
The figure is a top view showing the arrangement of vertical inverters within an inverter chain. The current method (i.e. the minimum shape is 1
If you use a photoengraving method (which can produce micron size),
The entire vertical inverter has a width of about 3 microns when viewed in the horizontal direction of Figure 1G, and a thickness of about 1 micron in the direction perpendicular to the plane of the drawing;
An additional thickness of 1 micron of ll region 20 is added. Therefore, the entire CMOS inverter is constructed within an area of approximately 6 square microns, as shown in FIG. Furthermore, since the inverter is constructed with a five-layer stack between the positive voltage source and ground, and there are no intervening junctions between the N-tank and P-tank, this inverter has little latch-up problems. Who? Latch-up occurs when a four-layer PNPN (or NPNP) stack forming a silicon-controlled rectifier is turned on between a voltage source terminal and ground.

In this example, there is a stack of 5 layers between the voltage source and ground (
Since there are six layers (including the substrate), this problem can be completely avoided.

FIG. 2 is a plan view of a structure made using the steps of FIGS. 1A-1G.

FIG. 3 is a circuit diagram of a logic NOR gate formed using three vertical inverters formed as shown in FIG. 1G. Input signal A is applied to the gate of inverter 31. The source of the 1) channel transistor of the inverter 31 is connected to the output conductor of the inpark 33. The output lead of inverter 31 generates signal 01JT. Input signal B is from Goo 1 to Impark 32 and Impark 33.
is applied to The output conductor of the inverter 32 is also a signal OUT.
will occur. The source of the P-channel transistor of inverter 32 remains open, and the source of the P-channel transistor of inverter 33 is a positive voltage source.

, is connected to. The sources of the N-channel transistors of inverters 31, 32, and 33 are connected to ground.

When a logic 1 (approximately 5 volts) signal is applied as input signal A, the N-channel transistor of inverter 31 conducts and signal 01JT is pulled to ground potential. When a logic 1 human power signal is applied as input signal B at this time,
The N-channel device of inverter 32 is turned on and the N-channel device of inverter 33 is turned on. Since the N-channel transistor of inverter 33 is on, the ground voltage is applied to the source of the P-channel transistor of inverter 31. However, inverter 31
The P-channel transistor of is off, so that
The output signal generated from inverter 33 does not affect signal OUT. After this, input signal A is set to logic O (approximately O volts)
, the N-channel transistor of inverter 31 is turned off and the P-channel transistor of inverter 31 is turned on, so that the output signal generated from inverter 33 becomes signal OUT.

In this case (input signal A is logic O1, input signal B is logic 1)
, both inverter 32 and inverter 33 have signal 0t
As a JT, it generates a logic O output signal. Input signal A
When is a logic 1 and input signal B is a logic O, the N-channel transistor of inverter 31 is on and the P-channel transistors of inverters 32 and 33 are on. Since the N-channel transistor of inverter 31 is on, the logic O output signal is the signal 0tJT.
is applied as . Since the P-channel transistor of inverter 32 has its source open, inverter 32 produces no output signal for signal OUT. Since the P-channel transistor of inverter 33 is on, a logic one output signal is produced from the output lead of inverter 33. However, since the P-channel transistor of inverter 31 is off, the output signal of inverter 33 has no effect on signal OUT. When both input signal A and input signal B are logic O, the P-channel transistor of inverter 31.32.33 is on. Since the source of the P-channel transistor of inverter 32 is open, inverter 32 has no effect on signal 0tJT. Since the P-channel transistor of inverter 33 is on, the output signal of inverter 33 is a logic 1, which causes inverter 31
applied to the source. Since the P-channel transistor of inverter 31 is on, the output signal of inverter 33 is applied as signal 0tJT. Thus, circuit 30 acts as a logic NOR gate.

Figure 3B uses the same basic design as the NOR gate 30 (Figure 3A), but with the addition of an inverter 34,35 so that the operation of the gate can add an input signal C. It is a circuit diagram of the human Kanoa gate 30A. In this way, a NOR gate can be created using any number of input signals.

The additional input signal requires two extra inverters, one of which has a P-channel transistor at V. , and the output conductor, and the N-channel transistor of the other inverter must be connected in parallel between the output conductor and ground.

Figure 4 shows the Noah system constructed using the structure shown in Figure 1G.
3 is a plan view of the gate 30. FIG. The tungsten region 16 is
Note that it is not only the gate of the inverter 31 , 32 , 33 , but also the connection between the surface of the integrated circuit and the buried output conductor 11 .

FIG. 5A is a circuit diagram of a logic NAND gate formed using three vertical inverters formed as shown in FIG. 1G. An input signal is applied to the gate of inverter 51. The source of the N-channel transistor of inverter 51 is connected to the output lead of inverter 53. The output conductor of inverter 51 generates the signal OUT. Input signal B is applied to the gates of inverter 52 and inverter 53. The output lead of inverter 52 also produces a signal OUT. The source of the N-channel transistor of inverter 52 remains open, and the source of the N-channel transistor of inverter 53 is connected to ground. The sources of the P-channel transistors of the inverters 51, 52, and 53 are positive voltage sources. connected to.

When a logic O (approximately O volts) signal is applied to the input signal, the P-channel transistor of inverter 51 conducts and the signal OUT is approximately 5 volts (logic O) V.

pulled to 0. At this time, when a logic O input signal is applied as input signal B, the P-channel device of inverter 52 is on, and the P-channel device of inverter 53 is on.

Since the P-channel transistor of inverter 53 is on, potential ■Do is applied to the source of the N-channel transistor of inverter 51.

However, the N-channel transistor of inverter 51 is off, so the output signal generated from inverter 53 has no effect on signal OUT.

After this, when input signal A is changed to logic 1, inverter 5
1 P-channel transistor is turned off,
The N-channel transistor of inverter 51 is turned on, so that the output signal generated by inverter 53 becomes signal OUT. In this case (input signal A is logic 1 and input signal B is logic O), both inverter 52 and inverter 53 produce a logic 1 output signal as signal OUT. When input signal A is a logic O and input signal B is a logic 1, the P-channel transistor of inverter 51 is on and the N-channel transistor of inverter 52.53 is on. Since the P-channel transistor of inverter 51 is on,
A logic 1 output signal is applied as signal 0tJT. Since the source of the N-channel transistor of inverter 52 is circuited, inverter 52 does not produce any output signal for signal OUT. Since the N-channel transistor of inverter 53 is on, inverter 5
A logic O output signal is generated from output lead 3. However, since the N-channel transistor of inverter 51 is off, the output signal of inverter 53 has no effect on signal OUT.

If both input signal A and input signal B are logic 1,
The N-channel transistors of inverters 51, 52, 53 are on. Since the source of the N-channel transistor of inverter 52 is open, inverter 5
2 has no effect on the signal OUT. Inverter 53ON
Since the channel transistor is on, the output signal of inverter 53, which is a logic one, is applied to the source of inverter 51. Since the N-channel transistor of inverter 51 is on, the output signal of inverter 53 is applied as signal 0tJT. The circuit thus acts as a logic NAND gate.

Figure 5B uses the same basic design as the NOR gate 50 (Figure 5A), but with the addition of an inverter 54.
It is a circuit diagram of the human Kanoa gate 50A. In this way, a NOR gate can be created using any number of input signals. The additional input signal requires two extra inverters, with the P-channel transistor of one transistor connected in parallel between ■oo and the output conductor, and the N-channel transistor of the other inverter connected between the output conductor and Must be connected in series between earth.

Although specific embodiments of the invention have been described, this should not be construed as limiting the scope of the invention. From this description of the invention, other embodiments of the invention will be readily apparent to those skilled in the art. The invention is limited only by the scope of the claims that follow.

The present invention provides an extremely compact vertical inverter that occupies minimal surface area on an integrated circuit. Additionally, the present invention provides a vertical inverter that is substantially free of the load-up problems encountered with currently known methods.

In connection with the above description, the following sections are further disclosed.

(1) A substrate having a first conductivity type and a second conductivity type formed on the surface of the substrate. a first channel layer having an H type; and the first channel layer formed on the surface of the first channel layer.
a first drain layer of the '4 conductivity type, a second drain layer of the second conductivity type formed on the surface of the first train layer, and a second drain layer of the second conductivity type formed on the surface of the second drain layer. The first
a second channel A7 channel layer of a conductivity type, a source layer of the second conductivity type formed on a surface of the second channel layer, the first and second channel layers, the first and second channel layers; Second
a conductive gate disposed vertically adjacent to and insulated from each layer with an edge perpendicular to the plane of the drain layer and the source layer, and connected to the first and second drain layers; An integrated electronic device having a conductive region.

(2) In the integrated electronic device described in paragraph (1),
The first four conductivity types are P type, and the second conductivity type is N type.
An integrated electronic device that is in the form of

(3) In the integrated electronic device described in paragraph (1),
An integrated electronic device in which a supply voltage is applied to the source layer and a reference voltage is applied to the substrate.

(4) In the integrated electronic device described in paragraph (3),
An integrated electronic device in which an input signal is applied to the gate and an output signal is generated at the conductive region.

(5) a plurality of integrated electronic devices formed in a substrate of a first conductivity type, each device having a first channel of a second conductivity type formed in a surface of the substrate; a layer, and the first groove formed on the surface of the first channel layer.
a first drain layer having a conductivity type, a second train layer having the second conductivity type formed on the surface of the first drain layer, and a second train layer having the second conductivity type formed on the surface of the second drain layer. a second channel layer having the first conductivity type; a source layer of the second conductivity type formed on the surface of the second channel layer; 1st
and a conductive gate disposed vertically adjacent to the second drain layer and the source layer with an edge perpendicular to the plane thereof and insulated from each of the layers, and connected to the first and second train layers. a conductive region, the conductive region comprising:
In a selected cell, a plurality of integrated electronic devices are connected to the conductive gates of adjacent cells.

(6) In the plurality of integrated electronic devices described in paragraph (5), the plurality of integrated electronic devices in which the first quadriconductivity type is P type and the second conductivity type is N type. Device.

(7) A plurality of integrated electronic devices according to paragraph (5), wherein a supply voltage is applied to the source layer and a reference voltage is applied to the substrate.

(8) A plurality of integrated electronic devices according to paragraph (7), wherein an input signal is applied to the gate and an output signal is generated at the conductive region.

(9) a crystalline silicon plug having a first conductivity type, a first channel layer of crystalline silicon having a second conductivity type formed on the surface of the substrate, and the first channel A7 channel layer; a first drain layer of crystalline silicon having the first conductivity type; and a second drain layer of crystalline silicon having the second conductivity type formed on the surface of the first drain layer. a second channel layer of crystalline silicon having the first conductivity type formed on the surface of the second drain layer; and a second channel layer of crystalline silicon formed on the surface of the second channel layer. a source layer of crystalline silicon having a conductivity type, and adjacent to the first and second channel layers, the first and second drain layers, and the source layer, with edges perpendicular to the plane thereof. An integrated electronic device having a tungsten gate disposed and insulated from each of the layers and a tungsten region connected to the first and second drain layers.

(10) The integrated electronic device according to item (9), wherein the first conductivity type is P type and the second conductivity type is N type.

(11) In a method of forming an integrated electronic device, a substrate having a first conductivity type is formed, a first channel layer having a second conductivity type is formed on a surface of the substrate, and a first channel layer having a second conductivity type is formed on a surface of the substrate. forming a first drain layer having the first conductivity type on the surface of the channel layer; forming a second drain layer having the second conductivity type on the surface of the first drain layer; forming a second channel layer having the first conductivity type on the surface of the second drain layer; forming a source layer having the second conductivity type on the surface of the second channel layer; a conductive gate 1 disposed perpendicularly in contact with the first and second channel layers, the first and second drain layers, and the source layer with edges perpendicular to the plane thereof, and insulated from each layer; forming a conductive region connected to the first and second train layers.

(12) In a method of forming an integrated electronic device, a substrate of crystalline silicon having a first conductivity type is formed, and a first channel layer of crystalline silicon having a second conductivity type is formed on the temporary surface. A first drain layer of crystalline silicon having the first conductivity type is epitaxially deposited on the surface of the substrate, and a first drain layer of crystalline silicon having the second conductivity type is epitaxially deposited on the surface of the substrate. 1 epitaxially depositing a second drain layer of silicon, and epitaxially depositing a second channel layer of crystalline silicon of the first conductivity type on the surface of the substrate, 1'+Q
epitaxially depositing a source layer of crystalline silicon having the second conductivity type on the surface of the substrate, passing through the first and second channel layers, the first and second train layers and the source layer; etching a first cavity down to the substrate; oxidizing the walls of the first cavity; depositing a conductive material within the first cavity; and etching a second cavity through the second drain layer and the source layer to the substrate, etching the second cavity above the top surface of the first channel layer and above the first channel layer. filling the remainder of the second void with an insulating material to a level below the second layer;
and filling the remainder of the second void with an insulating material to a level higher than a top surface of the drain layer and lower than the second channel layer.

(13) The method described in item (12), wherein the conductive material is selected from the group consisting of polycrystalline silicon, tungsten, and titanium silicide.

(14) a first inverter having an input conductor connected to the first input node, a first power conductor, a second power conductor connected to the first potential, and an output conductor connected to the output node; ,
a second inverter having an input conductor connected to a second input node, an unconnected first power conductor, a second power conductor connected to the first potential, and an output conductor connected to an output node; and a second input conductor connected to the second input node.
a first power conductor connected to an electrical potential, a second power conductor connected to the first electrical potential, and a third power conductor having an output conductor connected to the first power conductor of the first inverter. A logic gate with an inverter.

(15) In the logic gate described in item (14), the inverter is formed on a substrate having a first conductivity type, and the inverter is formed on a substrate having a second conductivity type formed on the surface of the bulb. a first channel layer having the first conductivity type, a first drain layer formed on the surface of the first channel layer waiting for the first conductivity type, and a second drain layer formed on the surface of the first drain layer. a second train layer having an fJ conductivity type, a second channel layer having the first J conductivity type formed on a surface of the second drain layer, and a second channel layer formed on a surface of the second channel layer. adjacent to the source layer having the second conductivity type, the first and second channel layers, the first and second drain layers and the source layer, and having an edge perpendicular to the plane thereof. A logic gate comprising a conductive gate I~ disposed vertically and insulated from each of the layers, and a conductive region connected to the first and second train layers.

[Brief explanation of drawings]

Figures 1A through 1G are simplified side views that do not show the processing steps required to manufacture one electronic device, and Figure 2 shows a configuration in which adjacent vertical inverters are included in the inverter chain. 18 to 1G, FIGS. 3A and 3B are circuit diagrams of the Noah game 1 according to the embodiment of the present invention, and FIG. 4 is a plan view of the embodiment shown in FIG. 3A. The plan view of the illustrated circuit, FIGS. 5A and 5B, is another embodiment of the present invention! i
FIG. 1 is a circuit diagram of an example Nando game 1-. Explanation of main symbols 1: Substrates 2 to 6: Epitaxial layer 11: Tungsten layer 16: Tungsten gate

Claims (1)

[Claims] (1) A substrate having a first conductivity type, a first channel layer having a second conductivity type formed on the surface of the substrate, and the first channel layer formed on the surface of the first channel layer. a first drain layer of the conductivity type, a second drain layer of the second conductivity type formed on the surface of the first drain layer, and a second drain layer of the second conductivity type formed on the surface of the second drain layer. a second channel layer of a first conductivity type, a source layer of the second conductivity type formed on the surface of the second channel layer, the first and second channel layers, the first and second channel layers; a conductive gate disposed vertically adjacent to and insulated from each of the layers with edges perpendicular to the planes of the second drain layer and the source layer; and a conductive gate that is insulated from each of the layers; an integrated electronic device having a conductive region connected to the integrated electronic device; (2) In a method of forming an integrated electronic device, a substrate having a first conductivity type is formed, a first channel layer having a second conductivity type is formed on a surface of the substrate, and a first channel layer having a second conductivity type is formed on a surface of the substrate; A first drain layer having the first conductivity type is formed on the surface of the channel layer, and a second drain layer having the second conductivity type is formed on the surface of the first drain layer.
forming a drain layer, forming a second channel layer having the first conductivity type on the surface of the second drain layer, and forming a second channel layer having the second conductivity type on the surface of the second channel layer; forming a source layer, disposed vertically adjacent to the first and second channel layers, the first and second drain layers, and the source layer with edges perpendicular to the plane thereof; A method comprising forming an insulated conductive gate and forming a conductive region connected to the first and second drain layers.