JPS62174668A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To reduce delay caused by the load of an FF circuit by connecting a gate circuit which controls the output of a master latch circuit and a slave latch circuit which is used only during a test to different output terminals of the master latch circuit respectively. CONSTITUTION:One input terminal of a gate 1 is connected to the output terminal Q of the master latch circuit LAT1 and the data input terminal D of the slave latch circuit LAT2 is connected to the output terminal Q. Further, one input terminal of a gate 3 is connected to the output terminal Q of the circuit LAT2 and a control signal and its inverted signal are inputted to other-terminal sides of the gates 1 and 3 respectively to control the output state of data. Thus, the gate 1 and circuit LAT2 are connected dispersedly to the terminals Q and Q of the circuit LAT1, so the side of the terminal Q of the circuit LAT1 drives only the gate 1 in normal operation. Consequently, the load on the output terminal Q is reduced and the delay due to the load is reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a signal control technology and a technology that is particularly effective when applied to control the data output of a flip-flop circuit. This invention relates to a technique that is effective for use in flip-flop circuits forming a diagnostic circuit provided in the western part of an LSI for diagnosing a circuit (circuit).

[Prior Art] There is a method of diagnosing a large-scale integrated circuit by dividing it into small-scale combinational circuits using internal flip-flop circuits. The above invention discloses that a master-slave type flip-flop circuit is used as the flip-flop circuit used in this method. If this master-slave type flip-flop is configured so that it passes through both the master latch circuit and the slave latch circuit even during normal operation, the data propagation speed will be slow.

Therefore, a circuit as shown in FIG. 3 has been proposed.

The circuit shown in the figure consists of a master side latch circuit LATI, a slave side latch circuit LAT2, and gates 1 to 3 forming a control circuit.

In the above circuit, data is passed through the slave latch circuit only during a test when the test control pin is set to "0", thereby preventing racing.

[Problem to be solved by the invention] However, the test control pin is tt I I+ (
During normal operation), the data is input from the data input pin to the master latch circuit LATI, and the latched data is output to the data output pin via the gate 1 without passing through the slave latch circuit LAT2. Therefore, the delay during normal operation is reduced. However, in the case of Fig. 3, in addition to gate 1, the slave latch plane LAT2, which is not used during normal operation, is always connected as a load to the output terminal Q of master latch circuit LAT2, and the delay due to the load during normal operation is sufficient. It cannot be said that it has been reduced.

An object of the present invention is to reduce the delay caused by the load during normal operation of a flip-flop circuit that constitutes a diagnostic circuit provided inside an LSI (Large Scale Integrated Circuit).

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a gate circuit that controls the output of the master latch circuit and a slave latch circuit that is used only during testing are connected to different output terminals of the master latch circuit.

[Operation] According to the above means, the slave latch circuit is not connected as a load to the first output terminal of the master latch circuit that outputs data during normal operation, and the normal operation load of the flip-flop circuit that constitutes the diagnostic circuit is connected to the first output terminal of the master latch circuit that outputs data during normal operation. is reduced,
As a result, the above objective of shortening the delay time is achieved.

[Example] FIG. 1 shows a schematic configuration of a logic LSI such as a gate array to which the present invention is applied. In the figure, although not particularly limited, each circuit surrounded by a chain double-dashed line A is made of single crystal silicon. It is formed on a single semiconductor chip such as a substrate.

It is more efficient to diagnose a logic LSI by dividing it into small-scale combinational circuits. Therefore, in this embodiment, as shown by the two-dot chain lines B and C, the combination surrounded by the flip-flop FFI and the flip-flop FF2 is used. Diagnosis is performed for each block of the circuit 11 and the combinational circuit 12 surrounded by the flip-flops FF3 and FF4. [Combination circuit] 3°14 is similarly diagnosed. Each of the flip-flops FFI to FF4 is a master-slave type flip-flop consisting of a master latch circuit and a slave latch circuit.

Individual combinational circuits 11, 12 . The diagnosis of ... is carried out as follows. First, a test pattern is scanned into the flip-flops FFI and FF3 on the input side of the combinational circuit. Next, the output side flip-flop FF2. FF
4 clock CLK is sent and data is taken in. Then, the output side flip-flop FF2. The data taken in from the FF4 is outputted from the scan out pin and compared with the data obtained in advance.

By performing such processing on all test patterns for all combinational circuits divided into small scales, it becomes possible to diagnose the logic LSI.

Further, in the above embodiment, in order to be able to diagnose each combinational circuit, an address is allocated to each combinational circuit in advance, and the address is decoded by the scan operation circuit 20 to specify a desired combinational circuit. It is now possible to diagnose.

FIG. 2 shows master-slave type flip-flop circuits FFI, FF2 . . . . is a circuit diagram showing the configuration of.

The flip-flop circuit FF in the same figure is a master latch circuit LATI, a slave latch circuit LAT2, and a master latch circuit LATI depending on the level of the test control pin.
It is composed of gate circuits 1 to 3 for controlling the output of TI and slave latch circuit LAT2.

One input terminal of the gate 1 is connected to the first output terminal Q of the master latch circuit LAT1, and the input terminal of the slave latch circuit LAT2 is connected to the second output terminal Q. Furthermore, one input terminal of the gate 3 is connected to the output terminal Q of the slave latch circuit LAT2.
A test control signal and its inverted signal are input to the other input terminals of gates 1 and 3, and the output state of data is controlled.

The flip-flop circuit FF fixes the test control pin to 1'1n during normal operation of the LSI. Then, gate 1 is opened, and the data input from the data input pin to the latch circuit LATI is sent out to the data output pin through the gate and supplied to the subsequent combinational circuit (see FIG. 1).

That is, since the data does not pass through the slave latch circuit LAT2, the data transmission delay time is shortened accordingly.

In addition, the flip-flop circuit FF fixes the test control pin to "0", and in this state clock CL
Test data is taken into the master latch circuit LAT1 at KI, and is transferred from the output terminal Q of the master latch circuit LAT1 to the slave latch circuit LAT2 in synchronization with the clock pulse CLK2. As a result, the test data becomes "0".

II I IF is scanned into the slave latch circuit LAT2. The output of the slave branch circuit LAT2 is output to the data output pin through the gate 3 which is opened by the signal of the test control pin.

In this embodiment, the gate 1 connected to the output terminal Q of the master latch circuit LATI and the slave latch circuit LA
T2 is connected to the output terminals Q and Q of the master latch circuit LATI in a distributed manner. Therefore, during normal operation, the first output terminal Q side of the master latch circuit LAT1 only needs to drive the gate 1. As a result, the load on the first output terminal is reduced and the delay due to the load is reduced.

[Effects of the Invention] A master latch circuit that outputs data during normal operation by connecting a gate circuit that controls the output of the master latch circuit and a slave latch circuit that is used only during testing to different output terminals of the master latch circuit. Since the slave latch circuit is not connected as a load to the first output terminal of the first output terminal, the delay due to the load during normal operation can be shortened.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

In the above explanation, the invention made by the present inventor was mainly applied to a flip-flop circuit constituting a diagnostic circuit provided inside an LSI for diagnosing an LSI, which is the field of application in which the invention was made by the present inventor. The present invention is not limited thereto, and can be applied to general circuits having master-slave flip-flops, for example.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a logic LSI such as a gate array to which the present invention is applied, and FIG. 2 is a master-slave type flip-flop circuit FFI in FIG.
A circuit diagram showing the structure of FF2... FIG. 3 is a circuit diagram showing the structure of a master-slave type flip-flop circuit proposed by the applicant prior to the present invention. 1 to 3...Gate circuit, LATI...Master latch circuit, LAT2...Slave latch circuit. FFI to FF4...Master-slave type flip-flop circuit, 11 to 14...Combination circuit, 20...
・Scan operation circuit.

Claims (1)

[Claims] 1. A flip-flop circuit with a master-slave configuration, consisting of a master latch circuit, a slave latch circuit, and gate means for controlling the output thereof, and capable of directly outputting data from the first output terminal of the master latch circuit to the data output terminal. The flip-flop circuit is characterized in that an input terminal of the slave latch circuit is connected to a second output terminal of the master latch circuit.