JPS62166558A - trimming circuit - Google Patents

Abstract

PURPOSE:To prevent a fuse from being blown except a desire at power source energizing and interrupting time by connecting a resistor which does not cause a parasitic diode between a trimming terminal and an MOS transistor to prevent a semiconductor integrated circuit from latching up and to stably melt the fuse. CONSTITUTION:When the mean blowing voltage of a fuse 11 is 8V and 10V at the maximum, a voltage applied to a trimming terminal 8 normally becomes 10V. The positive power source terminal 3 of a semiconductor integrated circuit frequently becomes approx. 5V by improving integration. Since a parasitic diode 23 represented by a P-channel MOS transistor 7 is also connected with a P-channel MOS transistor 5 at this time, the voltage of 10V applied to the terminal 8 is applied through a resistor 14 and a parasitic diode of the transistor 5 to the terminal 3, and also applied simultaneously between the fuse 11 and a second ground terminal 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a trimming circuit for semiconductor integrated circuits, and more particularly to a trimming circuit adjusted using a fuse.

[Conventional technology]

In semiconductor integrated circuits, in order to achieve a reference voltage, etc. N times, multiple sets of high resistance elements and fuses, such as M (JS transistors) operated as a constant source, are prepared, and x pressure is applied from the trimming terminal. By selectively cutting the fuse, the potential level at the connection point between the fuse and the high-resistance element is changed.

There is a method of trimming the reference voltage. FIG. 2 is an example of a circuit used for such trimming. P
Channel M (The source of the JS transistor 7 is connected to the positive power supply terminal 3, the gate potential is connected to the constant current source 24 and the gate electrode and drain electrode of the P channel MOS transistor 4, and the drain electrode is connected to the first terminal of the fuse 13. and the trimming terminal 1oVC are connected, and the second terminal of the fuse is connected to the second grounding terminal 2.The constant current source 24 and the P-channel MOS transistor 4 constitute a reference voltage source, and the voltage of this reference voltage source is By applying voltage to the electrode, P-channel MOS transistor 7 operates as a high resistance element.

With such a configuration, the connection point between the drain electrode of the P-channel MOS transistor 7 and the first terminal of the fuse 13 before the fuse 13 is cut is such that the resistance value of the fuse is equal to the conduction resistance value of the P-channel MOS transistor 7. Since it is small compared to , it is judged to be a low logic level.

10,000, after fuse 13 is cut, P channel MO
The connection point is pulled up to the voltage value of the positive power supply terminal 3 via the drain electrode and source electrode of the eight transistors.

Therefore, the connection point is determined to be at a high logic level.

It is common to use such a trimming circuit sound to selectively cut fuses and trim to a desired value during wafer inspection of semiconductor integrated circuits.

[Problem that the invention seeks to solve]

In the conventional trimming circuit described above, a parasitic diode exists between the drain electrode of the P-channel MOS transistor and the substrate, which are directly connected to the trimming terminal, and this is caused by the presence of a parasitic diode between the drain electrode of the P-channel MO8 transistor and the positive power supply terminal. It exists between

Due to the existence of this parasitic diode, the trimming voltage that can be applied to the trimming terminal when cutting the fuse is limited to the sum of the voltage value of the positive power supply terminal and the uniform voltage of the parasitic diode. In addition, the presence of this parasitic diode not only makes it difficult to apply a trimming voltage, but also causes a drawback tV, which causes a current to flow into the substrate when the fuse is cut, resulting in a latch-up trigger current.

[Means for solving problems]

The trimming circuit of the present invention connects the source electrode of the M2S transistor to the first electrode, connects the gate electrode to a reference voltage source, and connects the drain electrode to the first terminal of the resistor.
The second terminal of the resistor is connected to the first terminal and the trimming terminal of the fuse, and the second terminal of the fuse is connected to a second power source.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory diagram of an equivalent circuit of a trimming circuit according to a first embodiment of the present invention. The example of WJl is shown as an equivalent circuit diagram equivalent to 3V as a trimming circuit.
The operation of the trimming circuit itself will be explained using one bit.

P-channel MO8 transistors 4 and 5 connected to the positive power supply terminal 3 form a current mirror circuit.
The reference voltage of the gate electrode of the channel MOS transistor 5 is a reference voltage of a P channel M (consisting of a J8 transistor 4 and a current source 24) whose gate electrode and drain electrode are connected between the positive power supply terminal 3 and the first ground terminal 1. The drain electrode of P-channel MOS transistor 5 is connected to trimming terminal 8 and the input of inverter 17 and the first terminal of fuse 11 via resistor 14 .

A second terminal of fuse 11 is connected to second ground terminal 2 . The first grounding terminal l and the second grounding terminal 2 are normally connected to the same ground, but in order to prevent the fuse 11 from being disconnected when the semiconductor integrated circuit is powered on, the first grounding terminal l and the second grounding terminal 2 are connected to the same ground.
It is preferable to connect a resistor t'' between the first ground terminal 1 and the second ground terminal 2, and to use the first ground terminal 1 as the ground terminal of the semiconductor integrated circuit.

In FIG. 1, consider cutting 11 feet of fuse. Currently, the cutting voltage of fuse 11 is 8V on average.

If the maximum voltage is 10V, the voltage applied to the trimming terminal 8 will normally be 10V. On the other hand, as the degree of integration increases, the positive power supply terminal 3 of a semiconductor integrated circuit is often around 5.

At this time, since the parasitic diode 23 shown as a representative of the P-channel MO8 transistor in FIG. It is applied between the positive power supply terminal 3 through the parasitic diode (not shown) of the P-channel MO8 transistor 5, and at the same time, it is applied between the fuse 11- and the second ground terminal 2. Become. Here, if the resistor 14 is formed using a P-swelled diffusion layer, a parasitic diode will occur in the resistor, so a resistor made of polycrystalline silicon is most suitable. The resistance value of the resistor 14 must be determined by limiting the current flowing into the positive power supply terminal 3 through the resistor 14 and a parasitic diode (not shown). For example, if a current of 1 mAcD1it can be tolerated, the resistance value of the resistor 14 can be designed to be about 5Ω.

When the inverter 17 connects a resistor between the first ground terminal 1 and the second ground terminal, the trimming terminal 80
It is provided to adjust the level to 1, which is higher than the ground potential when the fuse 11 is not cut. The trimming result is output to the output 20 of the inverter 17.

Figure 1 shows a 3-bit embodiment, with trimming terminals 8,
Apply trimming voltage to fuses 9 and 10,
．． 12 and 13, and inverter 17.
．． The outputs 20° of 18 and 19 will output the trimming results from 21 and 22.

FIG. 3 is an explanatory diagram of an equivalent circuit of a trimming circuit according to a second embodiment of the present invention. Note that the same numbers are used for the same parts as in FIG.

In the second embodiment, the trimming circuit is shown in 1 bit and 1 bit, and as a concrete application, several bits are prepared for the fuse part of the trimming circuit, but since the operation can be explained even with 1 bit, it is omitted. did.

In the second embodiment, a human power protection circuit 31t-
This is what was inserted. This input protection circuit consists of a resistor,
Various types are possible, such as one in which a resistor and a diode are connected, but any of them may be used. However, it is preferable to use a circuit that prevents the input protection circuit 31 from becoming low impedance when the full trimming voltage is applied from the trimming terminal 10.

By fully inserting such input protection circuit 31, it is possible to prevent the input of inverter 19 from being destroyed by noise generated from a test machine during wafer inspection of semiconductor integrated circuits.

〔Effect of the invention〕

As explained above, the present invention, as a trimming circuit for a semiconductor integrated circuit, connects all the resistors between the trimming terminal and the MOS transistor so that no parasitic diode occurs, thereby preventing the semiconductor integrated circuit from becoming a latch amplifier. Moreover, there is an effect that fuses can be cut stably and that fuses other than desired are not cut when power is turned on and off.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of an equivalent circuit of the first embodiment of the present invention;
The figure shows an explanatory diagram of an equivalent circuit of a conventional trimming circuit, and FIG. 3 shows an explanatory diagram of an equivalent circuit of a second embodiment of the present invention. 1...First grounding terminal, 2...Second grounding terminal, 3...Positive trace terminal, 8,9.10...
...Trimming terminal, 4, 5, 6.7...
P-type MOS transistor, 11, 12, 13...
・Fuse, 14, 15° 16...Polycrystalline silicon resistor, 17, 18, 19...Inverter, 20, 21.22...Trimming output, 23
... Parasitic diode, 24...mark,' current source,
31...Manpower protection circuit. Agent Patent Attorney Uchihara t −”'−゛・
L'- Ki 1 Figure 3

Claims (1)

[Claims] The source electrode of the MOS transistor is connected to a first power supply, the gate electrode is connected to a reference voltage source, the drain electrode is connected to a first terminal of a resistor, and the second terminal of the resistor is connected to a first terminal of a fuse and a trimming terminal. and the second fuse
A trimming circuit characterized in that a terminal is connected to a second power source.