JPS6216595A - Manufacture of printed circuit board - Google Patents
Manufacture of printed circuit boardInfo
- Publication number
- JPS6216595A JPS6216595A JP15660785A JP15660785A JPS6216595A JP S6216595 A JPS6216595 A JP S6216595A JP 15660785 A JP15660785 A JP 15660785A JP 15660785 A JP15660785 A JP 15660785A JP S6216595 A JPS6216595 A JP S6216595A
- Authority
- JP
- Japan
- Prior art keywords
- plating layer
- copper plating
- printed circuit
- pattern
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概要〕
プリント基板の製造方法の改良であって、パターン形成
のために、無電解銅メッキ層および電解銅メッキ層(通
常この両者を積層したものをパネル銅メッキ層と称する
)上に形成したレジストパターンを除去後、このレジス
トパターン下のパネル銅メッキ層、並びに銅箔をエツチ
ング除去する工程に先立って、パターン銅メツキ層上に
形成された半田メッキ層を溶融する。そしてこの熔融し
た半田メッキ層でその下に形成されているパターン鋼メ
ッキ層の側面を被覆して、プリント基板の導体層パター
ンとなる半田メッキ層下のパターン鋼メッキ層がサイド
エッチされないようにする。[Detailed Description of the Invention] [Summary] This is an improvement in the manufacturing method of a printed circuit board, in which an electroless copper plating layer and an electrolytic copper plating layer (usually a laminated layer of both) are used as a panel copper plating layer for pattern formation. After removing the resist pattern formed on the patterned copper plating layer, the solder plating layer formed on the patterned copper plating layer is melted prior to the step of etching away the panel copper plating layer and copper foil under this resist pattern. . This molten solder plating layer then covers the side surfaces of the patterned steel plating layer formed below to prevent side etching of the patterned steel plating layer below the solder plating layer, which will become the conductor layer pattern of the printed circuit board. .
そして形成されるパターンが所定の寸法より細くならな
いようにしたプリント基板の製造方法。And a method for manufacturing a printed circuit board in which the formed pattern is prevented from becoming thinner than a predetermined size.
本発明はプリント基板の製造方法の改良に係り、特にパ
ターン形成のために用いたレジストパターンを除去後、
このレジストパターン下の不要なパネル銅メッキ層及び
銅箔をエツチング除去する工程で、パターン形成のため
の半田メッキ層下のパターン銅メッキ層がエツチングさ
れないようにして、形成されるパターンが所定の寸法よ
り細く成らないようにしたプリント基板の製造方法に関
する。The present invention relates to an improvement in a method for manufacturing a printed circuit board, and in particular, after removing a resist pattern used for pattern formation,
In this process of etching away the unnecessary panel copper plating layer and copper foil under the resist pattern, the pattern copper plating layer under the solder plating layer for pattern formation is not etched, and the pattern to be formed has a predetermined size. This invention relates to a method of manufacturing a printed circuit board that does not become thinner.
IC,LSI等の電子部品を搭載し、電子回路を形成す
るプリント基板は多くの電子機器の製造に用いられてい
る。Printed circuit boards on which electronic components such as ICs and LSIs are mounted to form electronic circuits are used in the manufacture of many electronic devices.
このようなプリント基板は、形成される電子回路が所定
の電気特性を有するために、回路パターンを形成する半
田メッキ層等の導電体層が所定の設計寸法に形成されて
いることが要望されている。In order for the formed electronic circuit to have predetermined electrical characteristics, such printed circuit boards are required to have conductive layers such as solder plating layers that form the circuit pattern formed to predetermined design dimensions. There is.
このようなプリント基板のうち、多層積層プリント基板
の従来の製造方法について説明する。Among such printed circuit boards, a conventional method for manufacturing a multilayer laminated printed circuit board will be described.
第3図に示すように、加圧装置の金型(図示せず)内に
銅箔IA、プリプレグと称する半硬化性の樹脂よりなる
接着シート2A、ガラスエポキシ樹脂板3の両面に導電
体層で回路パターン4を形成した中間層5を積層し、更
にこの上に接着シー1−2Bおよび銅箔1Bを順次積層
後、この金型を加熱加圧して、中間層5の回路パターン
4が樹脂に埋設された積層プリント基板6を形成する。As shown in FIG. 3, a copper foil IA is placed in a mold (not shown) of a pressurizing device, an adhesive sheet 2A made of a semi-hardening resin called prepreg, and a conductive layer on both sides of a glass epoxy resin plate 3. After laminating the intermediate layer 5 on which the circuit pattern 4 was formed, and further laminating the adhesive sheet 1-2B and the copper foil 1B on top of this in sequence, the mold was heated and pressurized so that the circuit pattern 4 of the intermediate layer 5 was made of resin. A laminated printed circuit board 6 embedded in the substrate is formed.
更に第4図に示すようにこれら中間層5の回路パターン
4と表面の銅箔IA、 1Bに形成するパターンとを接
続するため、および電子部品を接続設置するための導通
孔7を開口形成する。Furthermore, as shown in FIG. 4, conductive holes 7 are formed for connecting the circuit patterns 4 of the intermediate layer 5 and the patterns formed on the surface copper foils IA and 1B, and for connecting and installing electronic components. .
次いで第5図に示すように、プリント基板6の両面およ
び導通孔7の内壁に無電解銅メッキ層8を形成する。こ
の無電解銅メッキは樹脂の表面にも銅を被着することが
できる。Next, as shown in FIG. 5, electroless copper plating layers 8 are formed on both surfaces of the printed circuit board 6 and on the inner walls of the conductive holes 7. This electroless copper plating can also deposit copper on the surface of the resin.
更に無電解銅メッキ層8上に電解銅メッキ層9を形成す
る。Further, an electrolytic copper plating layer 9 is formed on the electroless copper plating layer 8.
次いで第6図に示すように電解銅メッキ層9を形成した
プリント基板の両面にフィルム状のホトレジスト膜(図
示せず)を貼着し、このホトレジスト膜に所定のパター
ンのマスクを用いて露光した後、レジスト除去材で非露
光部を除去して所定のレジストパターンIOをプリント
基板の両面に形成する。Next, as shown in FIG. 6, a film-like photoresist film (not shown) was attached to both sides of the printed circuit board on which the electrolytic copper plating layer 9 was formed, and this photoresist film was exposed to light using a mask with a predetermined pattern. Thereafter, the non-exposed portions are removed using a resist removal material to form predetermined resist patterns IO on both sides of the printed circuit board.
更に第7図に示すように、このレジストパターン10を
マスクにしてパターン銅メッキを実施し、パターン銅メ
ッキ層11を前記した導通孔7の内壁、およびプリント
基板両面のレジストパターンlO形成箇所以外の領域に
被着させ、更にパターン銅メツキ層ll上に半田メッキ
層12を電解メッキ法により形成する。Further, as shown in FIG. 7, patterned copper plating is carried out using this resist pattern 10 as a mask, and patterned copper plating layer 11 is applied to the inner wall of the conductive hole 7 and the areas other than the resist pattern 1O formation locations on both sides of the printed circuit board. Further, a solder plating layer 12 is formed on the patterned copper plating layer 11 by electrolytic plating.
更に第8図に示すようにレジストパターン10をレジス
ト除去液を用いて除去する。Furthermore, as shown in FIG. 8, the resist pattern 10 is removed using a resist removing liquid.
更に第9図に示すように、この半田メッキ層12をマス
クとして、銅は溶解するが半田は溶解しないエツチング
液を用いてレジストパターン10が形成されていた箇所
の下の部分の電解銅メッキ層9、無電解銅メッキ層8並
びに銅箔1Bをエツチング除去する。Furthermore, as shown in FIG. 9, using this solder plating layer 12 as a mask, the electrolytic copper plating layer is removed under the area where the resist pattern 10 was formed using an etching solution that dissolves copper but not the solder. 9. Etch and remove the electroless copper plating layer 8 and the copper foil 1B.
更に前記した半田メッキ層12を一旦溶融して固化させ
る。この工程はプリント基板に部品を搭載し、半田付け
する時に半田の上がり性を良くするためのヒユージング
工程である。Further, the solder plating layer 12 described above is once melted and solidified. This process is a fusing process to improve solder flow when components are mounted on a printed circuit board and soldered.
(発明が解決しようとする問題点〕
然し、上記した銅は溶解するが、半田は溶解しないエツ
チング液を用いて、レジストパターン1゜の下に形成さ
れていた電解銅メッキ層9、無電解銅メッキ層8並びに
銅箔1Bをエツチングする際に、半田メッキ層12の下
にエツチング液がまわりこんで入り込む。そのため、第
10図に示すように半田メッキ層12の下のパターン銅
メッキ層11、並びにその下の電解銅メッキ層9、無電
解銅メッキ層8及び銅箔1Bが側面よりエツチングされ
るサイドエツチングの現象が発生し、そのため、形成さ
れるパターンが所定の寸法より細く形成されるような問
題点を生じる。(Problems to be Solved by the Invention) However, using an etching solution that dissolves the copper but does not dissolve the solder, the electrolytic copper plating layer 9 formed under the resist pattern 1° and the electroless copper When etching the plating layer 8 and the copper foil 1B, the etching solution wraps around and enters under the solder plating layer 12. Therefore, as shown in FIG. In addition, a phenomenon of side etching occurs in which the electrolytic copper plating layer 9, the electroless copper plating layer 8, and the copper foil 1B underneath are etched from the side surfaces, and as a result, the formed pattern becomes thinner than the predetermined size. This causes many problems.
更に半田メッキ層12が両側に張り出すオーバーハング
現象が発生し、後の工程でこの張り出した半田が脱落し
て回路がショートする現象が発生する。Furthermore, an overhang phenomenon occurs in which the solder plating layer 12 protrudes on both sides, and in a later process, the overhanging solder falls off, resulting in a circuit short circuit.
更にパターン銅メツキ層ll上に異物等が付着してその
部分が半田メッキされない時には、この部分よりエツチ
ングされてパターン形成層13に欠け、ピンホール等の
パターン欠落が生じる問題がある。Further, when foreign matter or the like adheres to the patterned copper plating layer 11 and that part is not solder plated, there is a problem that this part is etched away and the pattern forming layer 13 is chipped, resulting in pattern defects such as pinholes.
本発明は上記した問題点を解決するもので、除去したレ
ジストパターン10の下の電解銅メッキ層9、無電解銅
メッキ層8および銅箔1Bを、パターン銅メツキ層11
上に形成されている半田メッキ層12をマスクとしてエ
ツチング除去するのに先立って、第2図に示すように半
田メッキ層12を溶融処理する工程を付与し、その後、
この熔融処理した半田メッキ層12をマスクとして電解
銅メッキ層9、電解銅メッキ層8、銅箔1Bをエツチン
グ除去する。The present invention solves the above-mentioned problems, and removes the electrolytic copper plating layer 9, electroless copper plating layer 8 and copper foil 1B under the removed resist pattern 10 from the patterned copper plating layer 11.
Prior to etching and removing the solder plated layer 12 formed thereon as a mask, a step of melting the solder plated layer 12 is applied as shown in FIG. 2, and then,
Using the melted solder plating layer 12 as a mask, the electrolytic copper plating layer 9, the electrolytic copper plating layer 8, and the copper foil 1B are removed by etching.
本発明の方法によれば、半田メッキ層12が熔融処理さ
れているので、この溶融した半田メッキ層12がパター
ン形成層13を形成するパターン銅メッキ層IIの側面
に付着されるため、エツチング液がパターン形成層13
の側面より入り込んでもパターン銅メッキ層11がエツ
チングされることが無くなり、形成されるパターン形成
層13が設計寸法より細くなる不都合が除去できる。According to the method of the present invention, since the solder plated layer 12 is melt-treated, the molten solder plated layer 12 is attached to the side surface of the patterned copper plated layer II forming the pattern forming layer 13. is the pattern forming layer 13
The patterned copper plating layer 11 will not be etched even if the patterned copper plating layer 11 is penetrated from the side surface, and the disadvantage that the formed pattern forming layer 13 will be thinner than the designed dimension can be eliminated.
以下、本発明の一実施例につき図面を用いながら詳細に
説明する。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
まず第1図に示すように銅箔1Bが形成されている基板
6上に前記した無電解銅メッキ層8、および電解銅メッ
キ層9を形成し、更に基板6上に所定パターンのレジス
トパターン10を形成後、このレジストパターン10を
マスクとして、パターン銅メッキ層11、半田メッキ層
12を順次形成した後、前記レジストパターン10を除
去する。ここまでの工程は従来の工程と同一である。次
いで本発明のパターン銅メツキ層11上の半田メッキ層
12を溶融する工程を付与する。First, as shown in FIG. 1, the electroless copper plating layer 8 and the electrolytic copper plating layer 9 described above are formed on the substrate 6 on which the copper foil 1B is formed, and then a resist pattern 10 of a predetermined pattern is formed on the substrate 6. After forming, using this resist pattern 10 as a mask, a patterned copper plating layer 11 and a solder plating layer 12 are sequentially formed, and then the resist pattern 10 is removed. The steps up to this point are the same as the conventional steps. Next, a step of melting the solder plating layer 12 on the patterned copper plating layer 11 of the present invention is applied.
この工程は前記レジストパターンlOを除去した□プリ
ント基板6を230℃前後の温度に加熱した加熱炉内を
通過させることで容易に実施できる□。This step can be easily carried out by passing the □ printed circuit board 6 from which the resist pattern 10 has been removed through a heating furnace heated to a temperature of around 230°C.
すると第1図に示すように溶融した半田メッキ層12は
パターン銅メッキ層11の側面を被覆する。Then, as shown in FIG. 1, the melted solder plating layer 12 covers the side surfaces of the patterned copper plating layer 11.
更に第2図に示すように、この溶融した半田メッキ層1
2をマスクとしてレジストパターン10の下部領域に形
成されていた電解銅メッキ層9、無電解銅メンキ層8#
よび銅箔1Bを半田を熔融せずに銅のみ溶融するエツチ
ング液を用いて除去する。Furthermore, as shown in FIG. 2, this melted solder plating layer 1
2 as a mask, the electrolytic copper plating layer 9 and the electroless copper coating layer 8# were formed in the lower region of the resist pattern 10.
Then, the copper foil 1B is removed using an etching solution that melts only the copper without melting the solder.
このようにすれば、プリント基板の回路パターンを形成
するパターン銅メッキ層11がサイドエッチされること
が無くなり、回路パターンが設計寸法より細くなって形
成されることが無くなり、高信頼度のプリント基板が得
られる。In this way, the patterned copper plating layer 11 that forms the circuit pattern of the printed circuit board will not be side-etched, and the circuit pattern will not be formed thinner than the designed dimension, resulting in a highly reliable printed circuit board. is obtained.
また半田メッキ層12がパターン銅メッキ層11の側面
側より張り出して、オーバーハング状の一田メツキ層が
形成され、この半田メッキ層が基板上に落下して回路パ
ターンがショートする事故も防げる。Furthermore, the solder plating layer 12 protrudes from the side surface of the patterned copper plating layer 11 to form an overhanging single plating layer, and it is also possible to prevent the solder plating layer from falling onto the board and causing a short circuit in the circuit pattern.
また従来の方法では、パターン銅メッキ層11上に異物
が付着し、この異物によって銅メツキ層11上に半田メ
ッキ層12が被着しない時には、この半田メッキ層12
をマスクとして基板上の電解銅メッキ層9をエツチング
する際に、パターン銅メッキ層11が一部エッチングさ
れてパターン欠落を生じるが、本発明の方法によれば、
半田メッキされない箇所にも溶融した半田が流れ込んで
付着するので、そのような事故も無くなる。Further, in the conventional method, when foreign matter adheres to the patterned copper plating layer 11 and the solder plating layer 12 does not adhere to the copper plating layer 11 due to the foreign matter, the solder plating layer 12
When etching the electrolytic copper plating layer 9 on the substrate using as a mask, part of the patterned copper plating layer 11 is etched, resulting in pattern loss, but according to the method of the present invention,
Since molten solder flows into and adheres to areas that are not solder plated, such accidents are eliminated.
以上述べたように本発明のプリント基板の製造方法によ
れば、パターンが設計寸法より細くなったり、パターン
のオーバーハング現象や、パターンの欠落がが無くなり
、高信頼度のプリント基板が得られる効果がある。As described above, according to the printed circuit board manufacturing method of the present invention, there is no pattern becoming thinner than the design dimension, pattern overhang phenomenon, or pattern missing, and a highly reliable printed circuit board can be obtained. There is.
第1図より第2図までは、本発明のプリント基板の製造
方法を工程順に示す断面図、
第3図より第9図までは、従来のプリント基板の製造方
法を工程順に示す断面図、
第10図は従来の方法で形成したプリント基板の不都合
な状態を示す断面図である。
図に於いて、
1Bは銅箔、4は回路パターン、6はプリント基板、8
は無電解銅メッキ層、9は電解銅メッキ層、10はレジ
ストパターン、11はパターン銅メッキ層、12は半田
メッキ層、13はパターン形成層を示す。
X 1 g
第 2 図
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ネ【Gり118図
7+q工、f、fI礼図
第 9111 to 2 are cross-sectional views showing the method for manufacturing a printed circuit board according to the present invention in the order of steps; FIGS. 3 to 9 are cross-sectional views showing the conventional method for manufacturing a printed circuit board in the order of steps; FIG. 10 is a sectional view showing an unfavorable state of a printed circuit board formed by a conventional method. In the figure, 1B is copper foil, 4 is a circuit pattern, 6 is a printed circuit board, and 8
9 is an electroless copper plating layer, 9 is an electrolytic copper plating layer, 10 is a resist pattern, 11 is a patterned copper plating layer, 12 is a solder plating layer, and 13 is a pattern forming layer. X 1 g 2nd figure fL Weihe Naki Kenyu 36+: box ti$mu tea 4th 2nd 5th meat suction wheel. y4 & transfer λnut+J%jj and 3゛λtoha・71shifp*energy i figure
+Me・tsu↑IIR Sudo \゛Work half 2nd eye l7II vLh fold offering; Keshireshi”21j1a7-〉Shima Ene [G 118 Figure 7 + q Engineering, f, fI Reizu No. 911
Claims (1)
無電解銅メッキ層(8)、電解銅メッキ層(9)を順次
形成し、更に該基板(6)上に所定パターンのレジスト
パターン(10)を形成し、該レジストパターン(10
)をマスクとして、該基板(6)上にパターン銅メッキ
層(11)、半田メッキ層(12)を順次形成後、前記
レジストパターン(10)を除去し、該レジストパター
ン(10)の下部に形成されていた電解銅メッキ層(9
)、無電解銅メッキ層(8)、銅箔(1B)を前記半田
メッキ層(12)をマスクとしてエッチング除去する工
程を有するプリント基板の製造方法に於いて、 前記レジストパターン(10)下の電解銅メッキ層(9
)、無電解銅メッキ層(8)銅箔(1B)をエッチング
除去する工程より以前に、前記半田メッキ層(12)を
溶融する工程を付与したことを特徴とするプリント基板
の製造方法。[Claims] An electroless copper plating layer (8) and an electrolytic copper plating layer (9) are sequentially formed on a substrate (6) on which a copper foil (1B) is formed. ), a resist pattern (10) having a predetermined pattern is formed on the resist pattern (10).
) as a mask, after sequentially forming a patterned copper plating layer (11) and a solder plating layer (12) on the substrate (6), the resist pattern (10) is removed, and a pattern is formed below the resist pattern (10). The electrolytic copper plating layer (9
), a printed circuit board manufacturing method comprising a step of etching away an electroless copper plating layer (8) and a copper foil (1B) using the solder plating layer (12) as a mask, Electrolytic copper plating layer (9
), Electroless copper plating layer (8) A method for manufacturing a printed circuit board, characterized in that a step of melting the solder plating layer (12) is provided before the step of etching away the copper foil (1B).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15660785A JPS6216595A (en) | 1985-07-15 | 1985-07-15 | Manufacture of printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15660785A JPS6216595A (en) | 1985-07-15 | 1985-07-15 | Manufacture of printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6216595A true JPS6216595A (en) | 1987-01-24 |
Family
ID=15631434
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15660785A Pending JPS6216595A (en) | 1985-07-15 | 1985-07-15 | Manufacture of printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6216595A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01206692A (en) * | 1988-02-15 | 1989-08-18 | Matsushita Electric Works Ltd | Manufacture of printed wiring board |
US5222126A (en) * | 1987-11-16 | 1993-06-22 | Canon Kabushiki Kaisha | Communication apparatus connected to other communication terminals |
-
1985
- 1985-07-15 JP JP15660785A patent/JPS6216595A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5222126A (en) * | 1987-11-16 | 1993-06-22 | Canon Kabushiki Kaisha | Communication apparatus connected to other communication terminals |
JPH01206692A (en) * | 1988-02-15 | 1989-08-18 | Matsushita Electric Works Ltd | Manufacture of printed wiring board |
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